Decoding method, memory storage device and memory control circuit unit

Abstract

The present application provides a decoding method, comprising: sending a first read instruction sequence corresponding to a host system to read a first physical unit of a physical unit group to obtain a first data frame; in response to a first single-frame decoding failure performed on the first data frame, sending a plurality of second read instruction sequences to read a plurality of second physical units in the physical unit group to obtain a plurality of second data frames; performing second single-frame decoding on the plurality of second data frames respectively; performing exclusive OR operation on data frames corresponding to each physical unit of the physical unit group to obtain first error evaluation information; generating reinforced first error evaluation information according to the first error evaluation information; and performing third single-frame decoding on the first data frame according to the reinforced first error evaluation information.

Description

Technical Field

[0001] This invention relates to a decoding technology, and more particularly to a decoding method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Some types of memory storage devices support single-frame decoding for a single data frame and multi-frame decoding for multiple data frames. For example, under normal circumstances, errors in a single data frame can be corrected through single-frame decoding. If a data frame has too many error bits, causing single-frame decoding to fail, multi-frame decoding can be used in conjunction with other data frames in the same coding group to correct errors in the target data frame. However, if too many data frames in the same coding group cannot be corrected by single-frame decoding, multi-frame decoding for that coding group cannot guarantee complete correction of errors in the target data frame, resulting in reduced decoding efficiency. Furthermore, the error assessment information used in current technology can be interfered with by error bits in data frames other than the target data frame, reducing accuracy. Summary of the Invention

[0004] This invention provides a decoding method, a memory storage device, and a memory control circuit unit, which can improve decoding efficiency.

[0005] An exemplary embodiment of the present invention provides a decoding method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units, and the decoding method includes: sending a first read instruction sequence, wherein the first read instruction sequence indicates reading a first physical unit among the multiple physical units, and the first physical unit belongs to a group of physical units; performing a first single-frame decoding on a first data frame read from the first physical unit; in response to the failure of the first single-frame decoding, obtaining first soft bit information corresponding to the first data frame, and sending multiple second read instruction sequences, wherein the multiple second read instruction sequences respectively indicate reading multiple second physical units other than the first physical unit in the group of physical units; performing a second single-frame decoding on multiple second data frames read from the multiple second physical units respectively; performing an XOR operation on the data frame corresponding to each physical unit in the group of physical units after the first single-frame decoding or the second single-frame decoding to obtain first error assessment information corresponding to the group of physical units; generating enhanced first error assessment information based on the first error assessment information; and performing a third single-frame decoding on the first data frame based on the enhanced first error assessment information and first reliability information corresponding to the first physical unit.

[0006] In an exemplary embodiment of the present invention, the first error assessment information includes a plurality of bits, and each of the plurality of bits has a first value or a second value. The step of generating the enhanced first error assessment information based on the first error assessment information includes: adjusting one or more target first bits of the plurality of bits of the first error assessment information having a first value to a second value to obtain the enhanced first error assessment information.

[0007] In an exemplary embodiment of the present invention, the step of adjusting one or more target first bits of the plurality of bits of the first error evaluation information having the first value to the second value includes: randomly selecting one or more target first bits from the plurality of first bits to adjust the selected one or more target first bits to the second value.

[0008] In an exemplary embodiment of the present invention, the step of performing the first single-frame decoding on the first data frame read from the first entity unit includes: performing the first single-frame decoding on the first data frame using the first reliability information corresponding to the first entity unit via a Low Density Parity Check code (LDPC code) algorithm.

[0009] In an exemplary embodiment of the present invention, in response to successful decoding of the second single frame corresponding to the third data frame among the plurality of second data frames, the decoded third data frame is obtained, wherein the third data frame corresponds to the third entity unit among the plurality of second entity units; the decoded third data frame is stored in another third entity unit among the plurality of entity units, and the other third entity unit is added to the entity unit group to replace the third entity unit in the entity unit group; in response to failed decoding of the second single frame corresponding to the fourth data frame among the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to the third entity unit in the entity unit group. The step of generating the enhanced first error assessment information based on the first error assessment information includes: obtaining the first soft bit information corresponding to the first data frame; obtaining the one or more fourth soft bit information respectively corresponding to the one or more fourth data frames; and adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information, wherein the number of one or more first bits in the enhanced first error assessment information is less than the number of one or more first bits in the first error assessment information, and the value of each first bit is a first value.

[0010] In an exemplary embodiment of the present invention, the step of adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information includes: performing an OR operation on the one or more fourth soft bit information to obtain a first vector; performing a NOT operation on the first soft bit information to obtain inverted first soft bit information; performing an AND operation on the inverted first soft bit information and the first vector to obtain a second vector; and performing a NOT operation on the second vector to obtain an inverted second vector, and using the inverted second vector as a mask corresponding to the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information.

[0011] In an exemplary embodiment of the present invention, the step of using the inverse second vector as a mask corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information includes: performing an AND operation on the inverse second vector and the first error evaluation information to obtain the enhanced first error evaluation information.

[0012] In an exemplary embodiment of the present invention, the step of performing the third single-frame decoding on the first data frame according to the enhanced first error assessment information includes: adjusting the first reliability information corresponding to the first entity unit according to the enhanced first error assessment information to obtain adjusted first reliability information; and using the adjusted first reliability information to perform the third single-frame decoding on the first data frame via the low-density parity check algorithm.

[0013] Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is electrically connected to a host system. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: send a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit among the plurality of entity units, and the first entity unit belongs to an entity unit group; perform a first single-frame decoding on a first data frame read from the first entity unit; in response to a failure of the first single-frame decoding, obtain first soft bit information corresponding to the first data frame, and send a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate reading a plurality of second entity units other than the first entity unit in the entity unit group; perform a second single-frame decoding on a plurality of second data frames read from the plurality of second entity units respectively; perform an XOR operation on the data frame corresponding to each entity unit in the entity unit group after the first single-frame decoding or the second single-frame decoding to obtain first error assessment information corresponding to the entity unit group; generate enhanced first error assessment information based on the first error assessment information; and perform a third single-frame decoding on the first data frame based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit.

[0014] Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface, a memory interface, a decoding circuit, and a memory management circuit. The host interface is electrically connected to a host system. The memory interface is electrically connected to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface, and the decoding circuit. The memory management circuit is configured to: send a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit among the plurality of entity units, and the first entity unit belongs to an entity unit group; instruct the decoding circuit to perform a first single-frame decoding on a first data frame read from the first entity unit; in response to the failure of the first single-frame decoding, obtain first soft bit information corresponding to the first data frame, and send a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate reading a plurality of second entity units other than the first entity unit in the entity unit group; instruct the decoding circuit to perform a second single-frame decoding on a plurality of second data frames read from the plurality of second entity units; perform an XOR operation on the data frame corresponding to each entity unit in the entity unit group after the first single-frame decoding or the second single-frame decoding to obtain first error assessment information corresponding to the entity unit group; generate enhanced first error assessment information based on the first error assessment information; and instruct the decoding circuit to perform a third single-frame decoding on the first data frame based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit.

[0015] Based on the above, the decoding method, memory storage device, and memory control circuit unit proposed in the exemplary embodiments of the present invention can improve the decoding success rate of target data frames and / or non-target data frames in a specific group of entity units by continuously updating and generating first error assessment information and enhanced first error assessment information corresponding to a specific group of entity units. Furthermore, by alternately performing single-frame decoding on target data frames and non-target data frames in the same group of entity units and updating the first error assessment information and enhanced first error assessment information based on the decoding results, the decoding success rate of subsequent single-frame decoding can also be improved. Moreover, by adjusting the reliability information used in subsequent decoding operations on target data frames using enhanced first error assessment information that better reflects the target data frame, the decoding success rate for the target data frame can be further improved, thereby enhancing the efficiency and accuracy of the memory storage device's read operations. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of multi-frame encoding as shown in an exemplary embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, the acquisition of a count value used to represent the total number of UECC frames in a group of entity units;

[0024] Figure 9 This is a schematic diagram illustrating the acquisition of first error assessment information according to an exemplary embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the critical voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of a reliability information table according to an exemplary embodiment of the present invention;

[0027] Figure 12 This is a flowchart illustrating the decoding method according to an exemplary embodiment of the present invention;

[0028] Figure 13 This is a schematic diagram of the enhanced decoding operation using enhanced error evaluation information generated via masking, as shown in an exemplary embodiment of the present invention.

[0029] Figure 14 This is a schematic diagram illustrating the generation of enhanced error evaluation information via random masking information and error evaluation information, as shown in an exemplary embodiment of the present invention.

[0030] Figure 15This is a schematic diagram of the enhanced decoding operation using enhanced error evaluation information generated via another mask, as shown in an exemplary embodiment of the present invention.

[0031] Figure 16 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, the generation of masking information via multiple soft information, and the generation of enhanced error evaluation information via the masking information and error evaluation information. Detailed Implementation

[0032] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0033] Generally, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0034] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0035] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be electrically connected to a system bus 110.

[0036] In one exemplary embodiment, the host system 11 can be electrically connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be electrically connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0037] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be electrically connected to the memory storage device 10 via wired or wireless means.

[0038] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be electrically connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0039] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0040] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly electrically connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0041] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0042] The connection interface unit 41 is used to electrically connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0043] The memory control circuit unit 42 is electrically connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0044] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0045] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0046] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If each memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0047] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, a physical erase unit is a physical block.

[0048] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53, and an error checking and correction circuit 54.

[0049] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0050] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0051] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0052] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are electrically connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0053] The host interface 52 is electrically connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. Furthermore, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 can also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0054] The memory interface 53 is electrically connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0055] The error checking and correction circuit 54 is electrically connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on this error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0056] The error checking and correction circuit 54 performs encoding / decoding in a basic unit called a frame (also called a data frame). A frame may include multiple data bits. In one example embodiment, a frame includes 256 bits. However, in another example embodiment, a frame may include more (e.g., 4K bytes) or fewer bits.

[0057] The error checking and correction circuit 54 can perform single-frame encoding and decoding of data in a single frame, and it can also perform multi-frame encoding and decoding of data in multiple frames. In one exemplary embodiment, the error checking and correction circuit 54 performs single-frame encoding and decoding based on LDPC codes, but the invention is not limited thereto. In one exemplary embodiment, the error checking and correction circuit 54 performs multi-frame encoding and decoding based on BCH codes, RS codes, and / or XOR codes, but the invention is not limited thereto. Depending on the encoding / decoding algorithm used, the error checking and correction circuit 54 can encode the data to be protected to generate corresponding error correction codes and / or error check codes. Subsequently, the error correction codes and / or error check codes generated by encoding can be used to correct errors in the data to be protected. For ease of explanation, the error correction codes and / or error check codes generated by encoding are collectively referred to as parity data below.

[0058] In one exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is electrically connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is electrically connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0059] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0060] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical cells 610(0)~610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0061] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may also include one or more entity erase units.

[0062] The physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0063] The memory management circuit 51 can configure logic units 612(0)~612(C) to map physical units 610(0)~610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0064] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0065] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0066] In one exemplary embodiment, memory management circuitry 51 may use physical cell groups to manage physical cells 610(0) to 610(A). A physical cell group may contain multiple physical cells. A physical cell group may be used to store multiple frames. A physical cell may be used to store one or more frames. A single physical cell group may contain physical cells in the same (or different) memory planes, the same (or different) memory dies, and / or the same (or different) Chip Enabled (CE) regions.

[0067] In one exemplary embodiment, the error checking and correction circuit 54 can perform multi-frame encoding on multiple frames stored in a group of entity units to protect the data in these frames with parity data generated by the multi-frame encoding. Furthermore, the error checking and correction circuit 54 can perform multi-frame decoding on multiple frames read from a group of entity units to correct errors in these frames with parity data generated by the multi-frame encoding.

[0068] In one exemplary embodiment, the error checking and correction circuit 54 can perform single-frame encoding on a single frame stored in a certain entity unit, using the parity data generated by the single-frame encoding to protect the data in that single frame. Furthermore, the error checking and correction circuit 54 can perform single-frame decoding on a single frame read from a certain entity unit, using the parity data generated by the single-frame encoding to correct errors in that single frame.

[0069] Figure 7 This is a schematic diagram illustrating multi-frame encoding according to an exemplary embodiment of the present invention. Please refer to... Figure 7 Frames 710(1) to 710(n) contain data stored in a group of entity units. For example, this group of entity units may contain... Figure 6 Multiple entity units in the memory. For example, frame 710(k) contains data to be stored in entity unit 610(k), where k is an integer between 1 and n. The data in frames 710(1) to 710(n) may contain data to be stored as indicated by a write instruction from host system 10. Alternatively, the data in frames 710(1) to 710(n) may also contain data read from rewritable nonvolatile memory module 43 and awaiting write-back to rewritable nonvolatile memory module 43.

[0070] In one exemplary embodiment, the error checking and correction circuit 54 may perform multi-frame encoding on frames 710(1) to 710(n) to generate frame 710(p). The data in frame 710(p) includes parity data to protect frames 710(1) to 710(n). For example, when multi-frame decoding is performed on frames 710(1) to 710(n), the parity data in frame 710(p) may be used to detect and / or correct errors in frames 710(1) to 710(n).

[0071] In one exemplary embodiment, in multi-frame encoding, the data in frames 710(1) to 710(n) is encoded based on the position of each bit (or bit group). For example, bits b(11), b(21), ..., b(n1) located at position 701(1) can be encoded to obtain bit b(p1) in frame 710(p); bits b(12), b(22), ..., b(n2) located at position 701(2) can be encoded to obtain bit b(p2) in frame 710(p); and so on, bits b(1m), b(2m), ..., b(nm) located at position 701(m) can be encoded to obtain bit b(pm) in frame 710(p). Subsequently, in multi-frame decoding, the bits in frame 710(p) (also called parity bits) can be used to detect and / or correct erroneous bits in frames 710(1) to 710(n). For example, bit b (p2) in frame 710 (p) can be used to detect or correct one or more erroneous bits in position 701 (2).

[0072] It should be noted that, in one exemplary embodiment, the arrangement of the multiple bits covered by any of positions 701(1) to 701(m) may differ from... Figure 7 The arrangement shown may vary, but this invention is not limited thereto. Furthermore, in one exemplary embodiment, the number of frames 710(p) containing parity data may also be two or more to provide different or better multi-frame decoding capabilities, and this invention is not limited thereto.

[0073] In one exemplary embodiment, the error checking and correction circuit 54 may perform single-frame encoding on frame 710(j) of frames 710(1) to 710(n) and 710(p) to generate parity data for protecting frame 710(j), where j is an integer between 1 and n or j may be p. Subsequently, in single-frame decoding, the parity data generated by performing single-frame encoding on frame 710(j) may be used to detect and / or correct error bits in frame 710(j).

[0074] In one exemplary embodiment, the parity data generated in frame 710(p) through multi-frame encoding is also referred to as Redundant Array of Independent Disks (RAID) error correction code. In one exemplary embodiment, frames 710(1) to 710(n) and 710(p) can also be combined and considered as a single block code. Frames 710(1) to 710(n) and 710(p) can be stored in multiple entity units belonging to the same entity unit group.

[0075] In one exemplary embodiment, the memory management circuit 51 may send a read instruction sequence. This read instruction sequence may instruct the reading of a specific entity cell (also referred to as the first entity cell) within a group of entity cells. For example, the memory management circuit 51 may send this read instruction sequence to the rewritable non-volatile memory module 43. The rewritable non-volatile memory module 43 may then return the data read from the first entity cell to the memory management circuit 51 according to this read instruction sequence. The decoding circuit in the error checking and correction circuit 54 may perform single-frame decoding on the frame containing the data. For example, if the data in this frame is encoded in a single frame based on LDPC codes, the decoding circuit may perform single-frame decoding on this frame based on LDPC codes. If the single-frame decoding is successful (indicating that the data in this frame is correct and / or errors have been corrected), the error checking and correction circuit 54 may output the successfully decoded data (also referred to as the decoded frame or decoded data frame).

[0076] In one exemplary embodiment, memory management circuitry 51 may obtain a read instruction from host system 11. This read instruction may instruct the reading of data belonging to a specific logical unit (also referred to as a first logical unit), and the first logical unit is mapped to a first physical unit. Based on this read instruction, memory management circuitry 51 may send the read instruction sequence (also referred to as a first read instruction sequence) to rewritable nonvolatile memory module 43 to read the data from the first physical unit.

[0077] In one exemplary embodiment, even without receiving a read instruction from the host system 11, the memory management circuit 51 may proactively send the read instruction sequence to the rewritable non-volatile memory module 43 to read the data from a specific physical cell of the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may proactively read the data from a specific physical cell during enhanced decoding operations, data merging operations (e.g., garbage collection), wear leveling (WL) operations, handling read disturb, and / or handling data retention.

[0078] In one exemplary embodiment, if the aforementioned single-frame decoding fails (indicating that this frame cannot be corrected by single-frame decoding), the decoding circuit in the error checking and correction circuit 54 can perform multi-frame decoding on multiple frames containing this frame, provided that preset conditions are met. For example, if this frame was originally encoded using XOR codes, the error checking and correction circuit 54 can also perform multi-frame decoding on this frame using XOR codes, provided that preset conditions are met. In one exemplary embodiment, a frame that cannot be corrected by single-frame decoding is also called a UECC frame.

[0079] It is important to note that in XOR-based multi-frame decoding, at most one UECC frame can exist among the multiple frames to be decoded at any given time. If the multiple frames to be decoded contain two or more UECC frames simultaneously, XOR-based multi-frame decoding will be unable to correct errors in these frames.

[0080] In one exemplary embodiment, before performing multi-frame decoding, the memory management circuit 51 may determine whether a preset condition is met. This preset condition is used to trigger multi-frame decoding of the entity unit group. In one exemplary embodiment, in response to the preset condition being met, the memory management circuit 51 may instruct the error checking and correction circuit 54 to perform multi-frame decoding of the entity unit group. Furthermore, if the preset condition is not met, the memory management circuit 51 may disallow the multi-frame decoding. This ensures the correctness of the decoding result of the performed multi-frame decoding.

[0081] In one exemplary embodiment, the memory management circuit 51 may use a count value to represent the total number of UECC frames in the entity unit group. For example, this count value may be equal to the total number of UECC frames in the entity unit group. In one exemplary embodiment, in response to this count value reaching (e.g., less than or equal to) a threshold, the memory management circuit 51 may determine that the preset condition has been met. Furthermore, if this count value does not reach (e.g., greater than) this threshold, the memory management circuit 51 may determine that the preset condition has not been met.

[0082] Figure 8 This is a schematic diagram illustrating the acquisition of a count value representing the total number of UECC frames in an entity unit group, as shown in an exemplary embodiment of the present invention. Please refer to... Figure 8 Frames 810(1) to 810(p) represent multiple frames read from the entity unit group. After performing single-frame decoding on each of frames 810(1) to 810(p), the UECC frames in frames 810(1) to 810(p) (e.g., frame 810(i)) can be recorded, such as Figure 8As shown. The memory management circuit 51 can count the total number of UECC frames in frames 810(1) to 810(p) and obtain a count value N based on this total number. That is, the count value N can be equal to or reflect the total number of UECC frames in frames 810(1) to 810(p).

[0083] In one exemplary embodiment, assuming that the error checking and correction circuit 54 performs multi-frame encoding and decoding based on XOR codes, this threshold value can be set to "1". Therefore, if the count value N equals "1", the memory management circuit 51 can determine that the preset condition has been met.

[0084] In one exemplary embodiment, the memory management circuit 51 may instruct the decoding circuit in the error checking and correction circuit 54 to perform single-frame decoding (also known as first single-frame decoding) on ​​a frame (also known as a first data frame) read from the first physical unit to correct errors in the first data frame. In one exemplary embodiment, if the first single-frame decoding is successful, the memory management circuit 51 may output the successfully decoded data. For example, the memory management circuit 51 may transmit the successfully decoded data to the host system 11 in response to the read instruction. Alternatively, during data merging operations (e.g., garbage collection operations), performing wear leveling operations, handling read interference, and / or handling data maintenance, the memory management circuit 51 may store the successfully decoded data in a specific physical unit and / or perform corresponding operations on the successfully decoded data. In one exemplary embodiment, if the first single-frame decoding fails, but the preset condition has been met, the decoding circuit may perform multi-frame decoding on the first data frame to correct errors in the first data frame.

[0085] In one exemplary embodiment, if the decoding of the first single frame fails and the preset condition is not met, the memory management circuit 51 may obtain error assessment information (also referred to as first error assessment information) corresponding to the entity cell group. The first error assessment information is related to the bit error rate of the entity cell group. For example, the first error assessment information may roughly reflect the total number of erroneous bits contained in the data read from the entity cell group.

[0086] In one exemplary embodiment, if the first single-frame decoding fails, the memory management circuit 51 and the decoding circuit can further perform a reinforced decoding operation to attempt to decode the first data frame again. Specifically, the memory management circuit 51 generates reinforced first error assessment information based on the first error assessment information. Then, the memory management circuit 51 can instruct the decoding circuit to perform single-frame decoding again on the first data frame based on the reinforced first error assessment information (also known as third single-frame decoding) to attempt to correct the errors in the first data frame based on the reinforced first error assessment information.

[0087] In one exemplary embodiment, the memory management circuit 51 can obtain or update reliability information based on enhanced first error assessment information. For example, this reliability information may include a log-likelihood ratio (LLR) that can be used in single-frame decoding. Furthermore, the memory management circuit 51 can adjust the first reliability information corresponding to the first entity unit based on the enhanced first error assessment information to obtain adjusted first reliability information. The decoding circuit can perform a third single-frame decoding on the first data frame of the first entity unit using a decoding algorithm (e.g., a low-density parity-checking algorithm) based on this adjusted first reliability information. It should be noted that the reliability information used in the third single-frame decoding is dynamically obtained or updated based on the enhanced first error assessment information; therefore, the third single-frame decoding may have a higher decoding success rate compared to the first single-frame decoding. That is, compared to the first single-frame decoding, the third single-frame decoding has a higher probability of completely correcting errors in the first data frame.

[0088] In one exemplary embodiment, both the first error assessment information and the enhanced first error assessment information include an assessment value. This assessment value may be positively correlated with the overall bit error rate of the entity unit group. For example, a higher overall bit error rate of the entity unit group indicates a greater total number of erroneous bits in the data read from the entity unit group, thus resulting in a larger assessment value. Alternatively, the assessment value may be positively correlated with the total number of erroneous bits in the data read from the entity unit group.

[0089] In one exemplary embodiment, memory management circuitry 51 may perform a logical operation on multiple frames (including a first data frame) read from a group of physical units to obtain first error assessment information. For example, this logical operation may include an XOR operation. For example, after performing this logical operation, memory management circuitry 51 may obtain a data sequence reflecting the result of the logical operation. Memory management circuitry 51 may count the total number of specific bits (e.g., bits "1" or "0") in this data sequence and obtain the first error assessment information based on this total number.

[0090] Figure 9 This is a schematic diagram illustrating the acquisition of first error assessment information according to an exemplary embodiment of the present invention. Please refer to... Figure 9Frames 910(1) to 910(p) represent multiple frames read from the entity unit group. After performing a logical operation including an XOR operation on frames 910(1) to 910(p), a data sequence 920 (also called error evaluation information) can be obtained. For example, the data sequence 920 may include bits b(r1) to b(rm). For example, bit b(r1) reflects the XOR result of bits b(11), b(21)... to b(p1); bit b(r2) reflects the XOR result of bits b(12), b(22)... to b(p2); and bit b(rm) reflects the XOR result of bits b(1m), b(2m)... to b(pm), and so on. The memory management circuit 51 can count the total number of bits "1" in the data sequence 920 and obtain an evaluation value M based on this total number. For example, the evaluation value M may be equal to or reflect the total number of bits "1" in the data sequence 920. Furthermore, the evaluation value M can be positively correlated with the overall bit error rate of the entity unit group. That is, the more error bits there are in frames 910(1) to 910(p), the larger the evaluation value M will be. Alternatively, if there are no error bits in frames 910(1) to 910(p), the evaluation value M can be zero. It is worth mentioning that since the error evaluation information reflects the state of error bits in the data frames of all entity units in the entity unit group, it is not easy to determine the distribution of error bits in the data frame corresponding to a single entity unit (e.g., the first data frame corresponding to the first entity unit) through the error evaluation information. In order to more effectively determine the distribution of error bits in the data frame of a single entity unit, this embodiment proposes to enhance the error evaluation information, thereby strengthening the error evaluation information, reducing the interference caused by error bits of other entity units to the error evaluation information, and thus more effectively determining the distribution of error bits in the data frame of a single entity unit.

[0091] Figure 10 This is a schematic diagram illustrating the critical voltage distribution of a memory cell according to an exemplary embodiment of the present invention. Please refer to... Figure 10 Assume that the critical voltage distribution of the memory cells in the group of physical cells includes states 1010 and 1020. State 1010 can be used to represent the distribution of critical voltages of the memory cells used to store the first bit (or the first bit combination). State 1020 can be used to represent the distribution of critical voltages of the memory cells used to store the second bit (or the second bit combination). For example, the first bit can be bit "0" (or the first bit combination can be bit "000", etc.), and the second bit can be bit "1" (or the second bit combination can be bit "101", etc.). Furthermore, the present invention does not limit the bits or bit combinations corresponding to states 1010 and 1020 respectively.

[0092] In one exemplary embodiment, memory management circuitry 51 may send a sequence of read instructions to rewritable non-volatile memory module 43 to instruct it to read memory cells using read voltage levels 1001 to 1005. The total number of read voltage levels 1001 to 1005 may be more or less. Based on the reading results of these memory cells using read voltage levels 1001 to 1005, memory management circuitry 51 may identify the critical voltage of each memory cell as belonging to one of voltage ranges A to F. Subsequently, assuming that the critical voltage of a memory cell belongs to voltage range A, the reliability information (e.g., LLR) corresponding to voltage range A can be used in single-frame decoding to decode the data bits read from this memory cell. Alternatively, assuming that the critical voltage of a memory cell belongs to voltage range C, the reliability information (e.g., LLR) corresponding to voltage range C can be used in single-frame decoding to decode the data bits read from this memory cell, and so on.

[0093] Figure 11 This is a schematic diagram of a reliability information table according to an exemplary embodiment of the present invention. Please refer to... Figure 11 Assume that table data 1101 records reliability information corresponding to different first error assessment information. In an exemplary embodiment, if the assessment value M = M(1) in the first error assessment information is strengthened, then according to table data 1101, the parameter value (e.g., LLR value) corresponding to the voltage range A~F in the reliability information LLR(0) can be used in the third single-frame decoding to decode the data read from the first entity unit (i.e., the first data frame). Similarly, if the assessment value M = M(2) or M(3) in the first error assessment information is strengthened, then according to table data 1101, the parameter value (e.g., LLR value) corresponding to the voltage range A~F in the reliability information LLR(1) or LLR(2) can be used in the third single-frame decoding to decode the data read from the first entity unit (i.e., the first data frame).

[0094] In one exemplary embodiment, assume that the reliability information used for the first single-frame decoding is LLR(0). After obtaining the latest evaluation value M=M(2) corresponding to the enhanced error evaluation information, the reliability information used for the third single-frame decoding can be adjusted from LLR(0) to LLR(1). Subsequently, in the third single-frame decoding, the decoding circuit can decode the first data frame based on the reliability information LLR(1). Under the bit error state corresponding to the evaluation value M=M(2), performing single-frame decoding based on the reliability information LLR(1) can improve the decoding success rate of single-frame decoding compared to the reliability information LLR(0). Thus, even if the first single-frame decoding fails, the first data frame still has a high probability of being successfully decoded in the third single-frame decoding (i.e., correcting all errors in the first data frame). It should be noted that even if the decoding success rate of the third single-frame decoding is higher than that of the first single-frame decoding, the third single-frame decoding may still fail (i.e., it may not be able to correct all errors in the first data frame).

[0095] Please refer to Figure 12 In step S1210, the memory control circuit unit 42 sends a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit (also referred to as a target entity unit) among the plurality of entity units, and the first entity unit belongs to a group of entity units. In one embodiment, the memory control circuit unit 42 generates the first read instruction sequence based on a read instruction from the host system 11. In another embodiment, the memory control circuit unit 42 may also generate the first read instruction sequence based on various operations used to manage the storage device 10. The group of entity units further includes a parity entity unit for storing parity data (e.g., Figure 7 The data frame 710(p) shown above, wherein the parity data is based on multiple other entity units (e.g., in the entity unit group other than the check entity unit) in the entity unit group. Figure 7 The data stored in the data frames 710(1) to 710(n) shown is generated. In an exemplary embodiment, the parity data is a fault-tolerant array of disks (RAID) error correction code, which is the result of performing an XOR operation on the data frames stored in each of the plurality of other entity units.

[0096] Next, in step S1220, the memory control circuit unit 42 performs first single-frame decoding on the first data frame read from the first physical unit. Then, in step S1230, in response to a failure of the first single-frame decoding, the memory control circuit unit 42 obtains first soft bit information corresponding to the first data frame and sends a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate the reading of a plurality of second physical units in the group of physical units other than the first physical unit. It is worth noting that when using a read voltage to read a physical unit, the obtained multiple sets of soft bit information can be used to reflect the voltage range in which the critical voltage of each memory cell in the physical unit is located. In this embodiment, the memory control circuit unit 42 uses the first set of soft bit information to generate enhanced first error assessment information for enhanced decoding. In other embodiments, other sets of soft bit information may also be used to generate enhanced first error assessment information. On the other hand, in response to a successful first single-frame decoding, the memory control circuit unit 42 obtains the decoded first data frame. The decoded first data frame can be transmitted to the host system 11 in response to the read instruction. Furthermore, the memory control circuit unit 42 can store the decoded first data frame to another first entity unit, replacing the mapping relationship of the first entity unit with the other first entity unit. In addition, it can further classify the other first entity unit into the entity unit group and remove the first entity unit from the entity unit group.

[0097] In this exemplary embodiment, the plurality of second read instruction sequences are not generated based on one or more read instructions from the host system 11. Instead, the plurality of second read instruction sequences are read instruction sequences actively generated and sent by the memory control circuit unit 42 to enhance the decoding of the first entity unit.

[0098] Next, in step S1240, the memory control circuit unit 42 performs second single-frame decoding on the multiple second data frames read from the multiple second entity units.

[0099] In one exemplary embodiment, the step of performing the first single-frame decoding on the first data frame read from the first entity unit includes: the memory control circuit unit 42 performing the first single-frame decoding on the first data frame using first reliability information corresponding to the first entity unit via a Low Density Parity Check (LDPC) code algorithm. Furthermore, in one embodiment, the step of performing the second single-frame decoding on the second data frame read from each second entity unit includes: the memory control circuit unit 42 performing a hardware decoding operation on the second data frame, wherein in response to a failure of the hardware decoding operation, the memory control circuit unit 42 performs a software decoding operation on the second data frame using a Low Density Parity Check (LDPC) code algorithm to perform the second single-frame decoding using second reliability information corresponding to the second entity unit.

[0100] Next, after completing the decoding of the multiple second single frames, in step S1250, the memory control circuit unit 42 performs an XOR operation on the data frame corresponding to each entity unit in the entity unit group after the first single frame decoding (e.g., for the first entity unit) or the second single frame decoding (e.g., for multiple second entity units) to obtain the first error assessment information corresponding to the entity unit group. That is, the memory control circuit unit 42 performs an XOR operation on the bit value of each data frame belonging to the entity unit group (including the original data frame that failed to be decoded and the decoded data frame that was successfully decoded) (e.g., Figure 9 (as shown in the diagram) to obtain the first error assessment information corresponding to the group of entity units.

[0101] More specifically, in an exemplary embodiment, in response to the successful decoding of the second single frame corresponding to the third data frame among the plurality of second data frames, the memory control circuit unit 42 obtains the decoded third data frame, wherein the third data frame corresponds to the third entity unit among the plurality of second entity units. Then, the memory control circuit unit 42 stores the decoded third data frame to another third entity unit among the plurality of entity units, adding this other third entity unit to the entity unit group to replace the third entity unit in the entity unit group (i.e., the third entity unit is removed from the entity unit group, and the third logic unit mapped to the third entity unit is also changed to be mapped to the other third entity unit).

[0102] Conversely, in response to the failure of decoding the second single frame corresponding to the fourth data frame among the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to the fourth entity unit among the plurality of second entity units.

[0103] In other words, if the data frame of one entity unit (e.g., the third entity unit) in the second entity unit is successfully decoded, the corresponding decoded data frame is stored in other entity units, and these other entity units replace the original entity unit in the entity unit group (the data frame of the entity unit group is updated); if the data frame of one entity unit (e.g., the fourth entity unit) in the second entity unit fails to decode, the data frame is retained in the entity unit group until it is successfully decoded. Then, after completing the first single-frame decoding and the multiple second single-frame decodings, the memory control circuit unit 42 performs an XOR operation on each data frame currently corresponding to the entity unit group to obtain first error evaluation information corresponding to the entity unit group. This error evaluation information is also called an XOR vector.

[0104] In this way, single-frame decoding is performed on multiple entity units other than the first entity unit in the entity unit group. By replacing the original data frame with the decoded data frame, interference from possible erroneous bits on the error evaluation information generated by the entity unit group can be reduced.

[0105] Next, in step S1260, the memory control circuit unit 42 generates enhanced first error assessment information based on the first error assessment information. Then, in step S1270, the memory control circuit unit 42 performs third single-frame decoding on the first data frame based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit.

[0106] Specifically, the step of generating the enhanced first error assessment information based on the first error assessment information includes: adjusting one or more target first bits of one or more first bits having a first value in the plurality of bits of the first error assessment information to a second value to obtain the enhanced first error assessment information. In one embodiment, the first value is 1 and the second value is 0, but the invention is not limited thereto. For example, in another embodiment, the first value is 0 and the second value is 1. In detail, the bits having a first value in the first error assessment information and the enhanced first error assessment information are called first bits. When the first value is adjusted to a second value, it is no longer a first bit. Therefore, the number of first bits in the enhanced first error assessment information will be less than the number of first bits in the corresponding first error assessment information.

[0107] In one exemplary embodiment, the reinforcement of the first error assessment information can be generated using a random method. For example, one or more target first bits can be randomly selected from the one or more first bits to adjust the selected one or more target first bits to the second value. In one embodiment, the memory control circuit unit 42 can generate masking information having randomly distributed first values, and the total number and arrangement of the masking information are equivalent to the first error assessment information. The memory control circuit unit 42 can perform an AND operation between the masking information and the first error assessment information to use the result of the operation as the reinforcement of the first error assessment information.

[0108] Please refer to Figure 13 Suppose that multiple entity units belonging to the entity unit group PUG store data frames DF1, DF2(1) to DF2(N). Among them, DF2(N) is, for example, the parity data generated by the XOR algorithm of data frames DF1, DF2(1) to DF2(N-1).

[0109] According to the read instruction from the host system 11, the memory control circuit unit 42 sends a first read instruction sequence to read the first data frame DF1 of the first entity unit (as shown by arrow A1200). During the read process, the memory control circuit unit 42 can obtain the first reliability information LLR1 of the corresponding first entity unit (as shown by arrow A1201).

[0110] The memory control circuit unit 42 then performs the first single-frame decoding of the first data frame DF1 via the LDPC algorithm / decoding circuit (B1301) (as shown by arrow A1202).

[0111] In response to the failure of the first single-frame decoding, the memory control circuit unit 42 sends a second read instruction sequence to read data frames DF2(1)~DF2(N) and performs the second single-frame decoding on the data frames DF2(1)~DF2(N) (as shown by arrow A1203).

[0112] As shown by arrows A1204 and A1205, after completing the decoding of the first single frame and multiple second single frames, the memory control circuit unit 42 identifies multiple data frames DF1, DF2(1)~DF2(N) (gray background) of the corresponding entity unit group PUG. Each data frame is different depending on whether the decoding of the corresponding single frame is successful. For example, if the first data frame DF1 corresponds to the first single frame decoding that failed, the first data frame DF1 (gray background) will be the original first data frame DF1 (i.e., raw data). As another example, if the Nth second data frame DF2(N) (gray background) corresponds to the second single frame decoding that was successfully decoded, the Nth second data frame DF2(N) (gray background) is not the original Nth second data frame DF2(N), but the Nth second data frame DF2(N) that has been decoded / successfully decoded (i.e., decoded data).

[0113] Next, as indicated by arrow A1206, the memory control circuit unit 42 performs an XOR operation on each data frame DF1, DF2(1)~DF2(N) (gray background) of the entity unit group PUG to obtain first error assessment information EI1. Then, the memory control circuit unit 42 generates enhanced first error assessment information EI2 (A1207) based on the first error assessment information EI1, for example, by using a random mask (B1302). Details of the random mask can be found in the corresponding... Figure 14 Explanation.

[0114] Next, the memory control circuit unit 42 adjusts the first reliability information LLR1 of the corresponding first entity unit according to the enhanced first error assessment information EI2 to obtain the adjusted first reliability information LLR2 (as shown by arrows A1208 and A1209). This operation of adjusting the reliability information is also called LLR remap (B1303), and details can be found in the above-mentioned corresponding... Figure 11 Explanation.

[0115] Next, the memory control circuit unit 42 uses the adjusted first reliability information LLR2 (as shown by arrow A1211) to perform the first single-frame decoding again on the first data frame DF1 (as shown by arrow A1210). The first single-frame decoding performed again is also called the third single-frame decoding.

[0116] Please refer to Figure 14Assuming an entity element group has two UECCs, its possible error bit information might be, for example, error bit information Err0 corresponding to a first data frame and error bit information Err1 corresponding to a fourth data frame ("1" represents an error bit). The first error assessment information generated for each data frame of this entity element group can be considered as the XOR result of the error bit information Err0 and Err1 (A1401). Figure 14 As shown, compared to the error bit information Err0 of the first data frame, the bit values ​​of the first error evaluation information are different from those of Err0. These bit values ​​at the same position but with different values ​​can be regarded as noise (Noise1). For example, the first error evaluation information has five noise bit values ​​due to the influence of the error bit information Err1. This makes it impossible to directly identify the distribution of error bits in the error bit information Err0 of the first data frame from the first error evaluation information.

[0117] In this exemplary embodiment, the memory control circuit unit 42 performs a masking operation on the first error evaluation information. First, it generates mask information with a random first value distribution. Then, it performs an AND operation (A1403) on the first error evaluation information and the random mask. As shown by arrow A1404, the obtained operation result is used as the enhanced error evaluation information (Adv. XOR vector). Figure 14 As shown, compared to the error bit information Err0 of the first data frame, the bit values ​​of the enhanced first error assessment information portion are different from those of Err0. These bit values ​​at the same position but with different values ​​can be regarded as noise Noise2. It should be noted that the number of noise bit values ​​in noise Noise2 (i.e., two) is less than the number of noise bit values ​​in the first error assessment information (i.e., five). In other words, through the random method provided in the above embodiment, enhanced error assessment information can be generated, which can more effectively reflect the distribution of error bits in the first data frame.

[0118] In another exemplary embodiment, the memory control circuit unit 42 may utilize soft bit information to generate masking information to generate the enhanced first error assessment information. Specifically, the step of generating the enhanced first error assessment information according to the first error assessment information includes: identifying the first soft bit information corresponding to the first data frame; identifying one or more fourth soft bit information corresponding to one or more fourth data frames, wherein the one or more fourth data frames are read from one or more fourth entity units among the plurality of second entity units of the entity unit group, and the second single-frame decoding performed on each of the one or more fourth data frames has failed; and adjusting the first error assessment information to the enhanced first error assessment information according to the first soft bit information and the one or more fourth soft bit information, wherein the number of one or more first bits in the enhanced first error assessment information is less than the number of one or more first bits in the first error assessment information, wherein the value of each first bit is a first value.

[0119] Please refer to Figure 15 , Figure 15 and Figure 13 The difference lies in that, after completing the decoding of the first single frame and multiple second single frames, as shown by arrow A1501, the memory control circuit unit 42 identifies the first soft bit information and one or more fourth soft bit information (if the decoding of one or more fourth data frames of the corresponding one or more fourth entity units fails). Next, in the step of performing a masking operation (B1602) to generate enhanced first error assessment information, the memory control circuit unit 42 generates masking information (A1502) based on the first soft bit information and one or more fourth soft bit information.

[0120] More specifically, the memory control circuit unit 42 performs an OR operation on the one or more fourth soft bit information to obtain a first vector; performs a NOT operation on the first soft bit information to obtain inverted first soft bit information; performs an AND operation on the inverted first soft bit information and the first vector to obtain a second vector; and performs a NOT operation on the second vector to obtain an inverted second vector, and uses the inverted second vector as a mask (mask information) corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information, for example, performing an AND operation on the inverted second vector and the first error evaluation information to obtain the enhanced first error evaluation information.

[0121] Please refer to Figure 16 Assuming the bit value of the unreliable soft bit information is "1", in addition to recognizing the soft bit information SB0 corresponding to the first data frame, the memory control circuit unit 42 also recognizes the three soft bit information SB1~SB3 corresponding to the three fourth data frames (UECC frames).

[0122] First, as shown by arrow A1601, the memory control circuit unit 42 performs an OR operation on the soft bit information SB1~SB3 to obtain a first vector (vector1). The first vector (vector1) can reflect the distribution of unreliable bits of other UECC soft bit information.

[0123] Next, the memory control circuit unit 42 performs a NOT operation on the soft bit information SB0 to obtain the inverse of the first soft bit information. (As shown by arrow A1602). Next, as shown by arrow A1603, the memory control circuit unit 42 reverses the first soft bit information. The first vector (vector1) is ANDed to obtain the second vector (vector2). The second vector (vector2) reflects the distribution of unreliable bits at the same positions as the reliable bits corresponding to the first soft bit information.

[0124] Next, as shown by arrow A1604, the memory control circuit unit 42 performs a NOT operation on the second vector (vector2) to obtain the inverse second vector (vector2). The inverse second vector ( () can be used as masking information.

[0125] Here, it is assumed that the memory control circuit unit 42 has been configured as follows: Figure 14 The method described uses the error bit information of the first data frame and the error bit information of three fourth data frames to generate the first error evaluation information (XOR vector).

[0126] Next, as shown by arrows A1605 and A1606, the memory control circuit unit 42 processes the first error evaluation information (XOR vector) and the inverse second vector ( An AND operation is performed to obtain enhanced error assessment information (Adv. XORvector) (A1607). This enhanced error assessment information takes into account the distribution of reliable bit values ​​of the first entity unit and unreliable bit values ​​of other UECC frames, reducing the interference caused by unreliable bit values ​​of other UECC frames (it can be seen that the number of first bits in this enhanced error assessment information is less than the number of first bits in the error assessment information), thereby improving the accuracy of the error bit distribution reflected by the enhanced error assessment information.

[0127] In one exemplary embodiment, in response to the successful decoding of the third single frame (i.e., all errors in the first data frame are corrected), the memory control circuit unit 42 continuously updates the first error assessment information based on the decoding result of the third single frame. The updated first error assessment information can roughly reflect the latest bit error rate of multiple entity units in the entity unit group. Then, the memory control circuit unit 42 can select a data frame (UECC frame) that has not yet been successfully decoded as the new first data frame to perform the first single frame decoding, or preferentially select the UECC frame with the lowest or relatively low bit error rate to perform the first single frame decoding. In addition, in response to the failure of the first single frame decoding, the memory control circuit unit 42 can also perform the enhanced decoding operation for the first data frame of the first entity unit as described above on the selected UECC frame based on the updated enhanced first error assessment information to improve the decoding success rate. Thus, the total number of UECC frames in the entity unit group can be gradually reduced.

[0128] In one exemplary embodiment, in response to the successful decoding of a UECC frame read from any entity in the entity group, the memory management circuit 51 may update the count value (e.g., Figure 8 The updated count value (N) reflects the total number of the latest UECC frames in the entity unit group. In one exemplary embodiment, if the updated count value reaches the threshold, the memory management circuit 51 can determine that the preset condition is met and multi-frame decoding can be performed. Furthermore, if the updated count value still does not reach the threshold, the memory management circuit 51 may not allow the multi-frame decoding to be performed.

[0129] In other words, the decoding method provided in this exemplary embodiment can gradually and successfully decode UECC frames. Once the total number of UECC frames in the entity element group reaches a critical value, multi-frame decoding of the entity element group can be initiated to ensure that the remaining UECC frames in the entity element group can be successfully decoded.

[0130] In one exemplary embodiment, the first entity unit is also referred to as the target entity unit. In one exemplary embodiment, entity units read in the entity unit group to assist in decoding the first data frame (i.e., the second entity unit) and / or entity units read to reduce the total number of UECC frames in the entity unit group are also referred to as non-target entity units. In one exemplary embodiment, frames read from target entity units are also referred to as target data frames, and / or frames read from non-target entity units are also referred to as non-target data frames.

[0131] In one exemplary embodiment, in response to the successful decoding of the third single frame corresponding to the target entity, the memory control circuit unit 42 obtains the decoded first data frame corresponding to the target entity. The decoded first data frame corresponding to the target entity can be transmitted to the host system 11 in response to the read command. Furthermore, in response to the successful decoding of the third single frame corresponding to the target entity, the memory control circuit unit 42 can select other UECC frames corresponding to non-target entity units as new first data frames to perform the enhanced decoding operation of steps S1210 to S1270, attempting to successfully decode UECC frames other than the original first data frames to update and enhance the error assessment information.

[0132] In other words, regardless of whether the target data frame is successfully decoded, single-frame decoding can continue to be performed on non-target data frames belonging to the UECC frame stored in the entity unit group until the target data frame is successfully decoded, all UECC frames in the entity unit group are successfully decoded, the preset conditions are met, or the decoding limit is reached (e.g., the maximum number of iterations is reached). Furthermore, frames corrected from UECC frames can be used to replace frames originally stored in the entity unit group to improve the decoding success rate of those frames in the future.

[0133] It is worth noting that, Figures 12 to 16 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figures 12 to 16 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0134] In summary, the decoding method, memory storage device, and memory control circuit unit proposed in the exemplary embodiments of the present invention can improve the decoding success rate of target data frames and / or non-target data frames in a specific group of entity units by continuously updating and generating first error assessment information and strengthening the first error assessment information corresponding to a specific group of entity units. Furthermore, by alternately performing single-frame decoding on target data frames and non-target data frames in the same group of entity units and updating the first error assessment information and strengthening the first error assessment information based on the decoding results, the decoding success rate of subsequent single-frame decoding can also be improved. Moreover, by adjusting the reliability information used in subsequent decoding operations on target data frames using strengthened first error assessment information that better reflects the target data frame, the decoding success rate for the target data frame can be further improved, thereby enhancing the efficiency and accuracy of the memory storage device's read operations.

[0135] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, characterized in that, The decoding method includes: Send a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit among the plurality of entity units, and the first entity unit belongs to an entity unit group; Perform first single-frame decoding on the first data frame read from the first entity unit; In response to the failure of the first single frame decoding, the first soft bit information corresponding to the first data frame is obtained, and a plurality of second read instruction sequences are sent, wherein the plurality of second read instruction sequences respectively indicate the reading of a plurality of second entity units other than the first entity unit in the entity unit group; Perform second single-frame decoding on each of the multiple second data frames read from the multiple second entity units; For each entity unit in the entity unit group, after the first single-frame decoding or the second single-frame decoding, the corresponding data frame is XORed to obtain the first error evaluation information corresponding to the entity unit group; Based on the first error assessment information, reinforced first error assessment information is generated; and Based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit, the first data frame is subjected to third single-frame decoding.

2. The decoding method according to claim 1, characterized in that, The first error assessment information includes multiple bits, and each of the multiple bits has a first value or a second value. The step of generating the enhanced first error assessment information based on the first error assessment information includes: One or more target first bits of the plurality of bits of the first error assessment information with a first value are adjusted to a second value to obtain the enhanced first error assessment information.

3. The decoding method according to claim 2, characterized in that, The step of adjusting one or more target first bits among the one or more first bits having the first value of the plurality of bits of the first error assessment information to the second value includes: Randomly select one or more target first bits from the one or more first bits to adjust the selected one or more target first bits to the second value.

4. The decoding method according to claim 1, characterized in that, The step of performing the first single-frame decoding on the first data frame read from the first entity unit includes: performing the first single-frame decoding on the first data frame using the first reliability information corresponding to the first entity unit via a low-density parity check algorithm.

5. The decoding method according to claim 4, characterized in that, The method further includes: In response to the successful decoding of the second single frame corresponding to the third data frame among the plurality of second data frames, the decoded third data frame is obtained, wherein the third data frame corresponds to the third entity unit among the plurality of second entity units; The decoded third data frame is stored in another third entity unit among the plurality of entity units, and the other third entity unit is added to the entity unit group to replace the third entity unit in the entity unit group; In response to a second single-frame decoding failure corresponding to the fourth data frame among the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to the fourth entity unit among the plurality of second entity units. The step of generating the enhanced first error assessment information based on the first error assessment information includes: Obtain the first soft bit information corresponding to the first data frame; Obtain the one or more fourth soft bit information corresponding to the one or more fourth data frames respectively; and Based on the first soft bit information and the one or more fourth soft bit information, the first error evaluation information is adjusted to the enhanced first error evaluation information, wherein the number of one or more first bits in the enhanced first error evaluation information is less than the number of one or more first bits in the first error evaluation information, and the value of each first bit is a first value.

6. The decoding method according to claim 5, characterized in that, The step of adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information includes: Perform an OR operation on the one or more fourth soft bit information to obtain a first vector; Perform an inversion operation on the first soft bit information to obtain the inverted first soft bit information; Perform a bitwise AND operation on the inverse first soft bit information and the first vector to obtain a second vector; and The second vector is inverted to obtain an inverse second vector, and the inverse second vector is used as a mask corresponding to the first error evaluation information to adjust the first error evaluation information into the enhanced first error evaluation information.

7. The decoding method according to claim 6, characterized in that, The step of using the inverse second vector as a mask corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information includes: Perform a bitwise AND operation on the inverse second vector and the first error evaluation information to obtain the enhanced first error evaluation information.

8. The decoding method according to claim 4, characterized in that, The step of performing the third single-frame decoding on the first data frame based on the enhanced first error assessment information includes: Based on the enhanced first error assessment information, the first reliability information corresponding to the first entity unit is adjusted to obtain adjusted first reliability information; and The third single-frame decoding is performed on the first data frame using the adjusted first reliability information via the low-density parity check algorithm.

9. A memory storage device, characterized in that, include: A connection interface unit for electrically connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; as well as The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Send a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit among the plurality of entity units, and the first entity unit belongs to a group of entity units; Perform first single-frame decoding on the first data frame read from the first entity unit; In response to the failure of the first single frame decoding, the first soft bit information corresponding to the first data frame is obtained, and a plurality of second read instruction sequences are sent, wherein the plurality of second read instruction sequences respectively indicate the reading of a plurality of second entity units other than the first entity unit in the entity unit group; Perform second single-frame decoding on each of the multiple second data frames read from the multiple second entity units; For each entity unit in the entity unit group, after the first single-frame decoding or the second single-frame decoding, the corresponding data frame is XORed to obtain the first error evaluation information corresponding to the entity unit group; Based on the first error assessment information, reinforce the first error assessment information; as well as Based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit, the first data frame is subjected to third single-frame decoding.

10. The memory storage device according to claim 9, characterized in that, The first error assessment information includes multiple bits, and each of the multiple bits has a first value or a second value. The step of generating the enhanced first error assessment information based on the first error assessment information includes: One or more target first bits of the plurality of bits of the first error assessment information with a first value are adjusted to a second value to obtain the enhanced first error assessment information.

11. The memory storage device according to claim 10, characterized in that, The step of adjusting one or more target first bits among the one or more first bits having the first value of the plurality of bits of the first error assessment information to the second value includes: Randomly select one or more target first bits from the one or more first bits to adjust the selected one or more target first bits to the second value.

12. The memory storage device according to claim 9, characterized in that, The step of performing the first single-frame decoding on the first data frame read from the first entity unit includes: performing the first single-frame decoding on the first data frame using the first reliability information corresponding to the first entity unit via a low-density parity check algorithm.

13. The memory storage device according to claim 12, characterized in that, The memory control circuit unit is further used for: In response to the successful decoding of the second single frame corresponding to the third data frame among the plurality of second data frames, the decoded third data frame is obtained, wherein the third data frame corresponds to the third entity unit among the plurality of second entity units; The decoded third data frame is stored in another third entity unit among the plurality of entity units, and the other third entity unit is added to the entity unit group to replace the third entity unit in the entity unit group; In response to a second single-frame decoding failure corresponding to the fourth data frame among the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to the fourth entity unit among the plurality of second entity units. The step of generating the enhanced first error assessment information based on the first error assessment information includes: Obtain the first soft bit information corresponding to the first data frame; Obtain the one or more fourth soft bit information corresponding to the one or more fourth data frames respectively; and Based on the first soft bit information and the one or more fourth soft bit information, the first error evaluation information is adjusted to the enhanced first error evaluation information, wherein the number of one or more first bits in the enhanced first error evaluation information is less than the number of one or more first bits in the first error evaluation information, and the value of each first bit is a first value.

14. The memory storage device according to claim 13, characterized in that, The step of adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information includes: Perform an OR operation on the one or more fourth soft bit information to obtain a first vector; Perform an inversion operation on the first soft bit information to obtain the inverted first soft bit information; Perform a bitwise AND operation on the inverse first soft bit information and the first vector to obtain a second vector; and The second vector is inverted to obtain an inverse second vector, and the inverse second vector is used as a mask corresponding to the first error evaluation information to adjust the first error evaluation information into the enhanced first error evaluation information.

15. The memory storage device according to claim 14, characterized in that, The step of using the inverse second vector as a mask corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information includes: Perform a bitwise AND operation on the inverse second vector and the first error evaluation information to obtain the enhanced first error evaluation information.

16. The memory storage device according to claim 12, characterized in that, The step of performing the third single-frame decoding on the first data frame based on the enhanced first error assessment information includes: Based on the enhanced first error assessment information, the first reliability information corresponding to the first entity unit is adjusted to obtain adjusted first reliability information; and The third single-frame decoding is performed on the first data frame using the adjusted first reliability information via the low-density parity check algorithm.

17. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, characterized in that, The memory control circuit unit includes: Host interface, used for electrical connection to the host system; A memory interface for electrically connecting to the rewritable non-volatile memory module; Decoding circuit; and The memory management circuit is electrically connected to the host interface, the memory interface, and the decoding circuit. The memory management circuit mentioned above is used for: Send a first read instruction sequence, wherein the first read instruction sequence indicates reading a first entity unit among the plurality of entity units, and the first entity unit belongs to a group of entity units; The decoding circuit is instructed to perform a first single-frame decoding on the first data frame read from the first physical unit; In response to the failure of the first single frame decoding, the first soft bit information corresponding to the first data frame is obtained, and a plurality of second read instruction sequences are sent, wherein the plurality of second read instruction sequences respectively indicate the reading of a plurality of second entity units other than the first entity unit in the entity unit group; The decoding circuit is instructed to perform second single-frame decoding on each of the multiple second data frames read from the multiple second entity units; For each entity unit in the entity unit group, after the first single-frame decoding or the second single-frame decoding, the corresponding data frame is XORed to obtain the first error evaluation information corresponding to the entity unit group; Based on the first error assessment information, reinforced first error assessment information is generated; and The decoding circuit is instructed to perform a third single-frame decoding on the first data frame based on the enhanced first error assessment information and the first reliability information corresponding to the first entity unit.

18. The memory control circuit unit according to claim 17, characterized in that, The first error assessment information includes multiple bits, and each of the multiple bits has a first value or a second value. The step of generating the enhanced first error assessment information based on the first error assessment information includes: One or more target first bits of the plurality of bits of the first error assessment information with a first value are adjusted to a second value to obtain the enhanced first error assessment information.

19. The memory control circuit unit according to claim 18, characterized in that, The step of adjusting one or more target first bits among the one or more first bits having the first value of the plurality of bits of the first error assessment information to the second value includes: Randomly select one or more target first bits from the one or more first bits to adjust the selected one or more target first bits to the second value.

20. The memory control circuit unit according to claim 17, characterized in that, The step of performing the first single-frame decoding on the first data frame read from the first entity unit includes: performing the first single-frame decoding on the first data frame using the first reliability information corresponding to the first entity unit via a low-density parity check algorithm.

21. The memory control circuit unit according to claim 20, characterized in that, The memory management circuit is further used for: In response to the successful decoding of the second single frame corresponding to the third data frame among the plurality of second data frames, the decoded third data frame is obtained, wherein the third data frame corresponds to the third entity unit among the plurality of second entity units; The decoded third data frame is stored in another third entity unit among the plurality of entity units, and the other third entity unit is added to the entity unit group to replace the third entity unit in the entity unit group; In response to a second single-frame decoding failure corresponding to the fourth data frame among the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to the fourth entity unit among the plurality of second entity units. The step of generating the enhanced first error assessment information based on the first error assessment information includes: Obtain the first soft bit information corresponding to the first data frame; Obtain the one or more fourth soft bit information corresponding to the one or more fourth data frames respectively; and Based on the first soft bit information and the one or more fourth soft bit information, the first error evaluation information is adjusted to the enhanced first error evaluation information, wherein the number of one or more first bits in the enhanced first error evaluation information is less than the number of one or more first bits in the first error evaluation information, and the value of each first bit is a first value.

22. The memory control circuit unit according to claim 21, characterized in that, The step of adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information includes: Perform an OR operation on the one or more fourth soft bit information to obtain a first vector; Perform an inversion operation on the first soft bit information to obtain the inverted first soft bit information; Perform a bitwise AND operation on the inverse first soft bit information and the first vector to obtain a second vector; and The second vector is inverted to obtain an inverse second vector, and the inverse second vector is used as a mask corresponding to the first error evaluation information to adjust the first error evaluation information into the enhanced first error evaluation information.

23. The memory control circuit unit according to claim 22, characterized in that, The step of using the inverse second vector as a mask corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information includes: Perform a bitwise AND operation on the inverse second vector and the first error evaluation information to obtain the enhanced first error evaluation information.

24. The memory control circuit unit according to claim 20, characterized in that, The step of performing the third single-frame decoding on the first data frame based on the enhanced first error assessment information includes: The memory management circuit adjusts the first reliability information corresponding to the first entity cell based on the enhanced first error assessment information to obtain adjusted first reliability information; and The decoding circuit is instructed to perform the third single-frame decoding on the first data frame using the adjusted first reliability information via the low-density parity check algorithm.

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