A via arrangement method to reduce current density

Abstract

This invention provides a via arrangement method to reduce current density, relating to the field of PCB circuit design technology. The method includes: screening power networks with current densities exceeding a set threshold as target networks; calibrating the power plate area within the target network; identifying and locating the power pins of the power supply chip and the load chip within the power plate area; determining the shortest path between the power supply chip and the load chip; and arranging network vias outside the target network parallel to the shortest path. This invention achieves high-density and high-efficiency PCB design, reduces power network current density, and avoids the risk of exceeding power network current density limits.

Description

Technical Field

[0001] This invention relates to the field of PCB circuit design technology, and specifically to a via arrangement method for reducing current density. Background Technology

[0002] As electronic devices become increasingly complex, chips are trending towards miniaturization and low-voltage, high-current designs, leading to higher-density PCB designs. Vias are used in PCB design to interconnect signals across different layers. Depending on the signal definition, vias are mainly divided into signal vias and power vias. To ensure product quality, vias in different networks and between vias and power boards must avoid each other. This can result in sharp corners on power boards or vias interrupting current flow, causing excessive current density in the power network. Consequently, this leads to increased PCB temperature rise and reduced PCB reliability and manufacturability. Summary of the Invention

[0003] In view of this, embodiments of this application provide a via arrangement method to reduce current density, which is used to support high-density PCB design and reduce power network current density.

[0004] This application provides the following technical solution: a via arrangement method for reducing current density, comprising:

[0005] Power networks with current densities exceeding a set threshold are selected as target networks;

[0006] The power supply flat panel area within the target network is calibrated;

[0007] The power pins of the power network power supply chip and the power pins of the load chip in the power supply flat area are identified and located.

[0008] Determine the shortest path between the power network chip and the load chip;

[0009] Arrange network vias outside the target network parallel to the shortest path.

[0010] According to one embodiment of this application, determining the shortest path between the power network chip and the load chip includes:

[0011] Based on the power pin positions of the power network chip and the load chip, the geometric centers of the power network chip and the load chip are determined respectively, and the line connecting the two geometric centers is taken as the shortest path.

[0012] According to one embodiment of this application, determining the shortest path between the power network chip and the load chip includes:

[0013] When the power network has one power supply chip and multiple load chips, the geometric center of the power supply chip and each load chip in the power network is determined according to the power pin position of the power supply chip and the power pin position of the load chip, respectively. The geometric center of the power supply chip and the geometric center of each load chip are connected to form multiple power supply current paths.

[0014] Based on the magnitude of the current required for the normal operation of the load chip, the power supply path corresponding to the load chip with the largest required current is taken as the shortest path.

[0015] According to one embodiment of this application, based on the magnitude of the current required for the normal operation of the load chip, the method further includes:

[0016] Based on the magnitude of the current required for the normal operation of the load chip, the power supply paths corresponding to the multiple load chips are sorted, with higher current having higher priority.

[0017] Based on the PCB space constraints, the power supply path corresponding to the load chip with the highest priority under the PCB space constraints is selected as the shortest path.

[0018] According to one embodiment of this application, determining the shortest path between the power network chip and the load chip includes:

[0019] When the power network has multiple power supply chips and one load chip, the geometric center of each power supply chip and the load chip in the power supply network is determined according to the power pin positions of the power supply chips and the power pin positions of the load chip. The geometric center of the load chip and the geometric center of each power supply chip are connected to form multiple power supply current paths.

[0020] Based on the rated power supply current of the power supply chip, the power supply path corresponding to the power supply chip with the largest rated power supply current is taken as the shortest path.

[0021] According to one embodiment of this application, based on the rated power supply current of the power supply chip, it further includes:

[0022] Based on the rated power supply current of the power supply chip, the power supply current paths corresponding to multiple power supply chips are sorted, with higher current having higher priority.

[0023] Based on the rated power supply current of the power supply chip, the power supply path corresponding to the power supply chip with the highest priority corresponding to the rated power supply current is selected as the shortest path.

[0024] According to one embodiment of this application, the power supply plate area within the target network is calibrated in CAD software.

[0025] Compared with existing technologies, the beneficial effects achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: The embodiments of this invention employ a via arrangement method to reduce current density, rationally arranging signal vias parallel to the shortest path, reducing the width of the power supply plate interrupted by different network vias on the shortest current path, and increasing the effective current flow width. After the PCB design is completed, this invention achieves effective control of PCB current density through optimized via arrangement design. The embodiments of this invention can reduce power supply current density, reduce PCB temperature rise, improve system reliability and economy, and provide a plate cutting approach for the low-voltage, high-current design of next-generation high-density PCBs. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of a via arrangement method for reducing current density according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of a via arrangement according to an embodiment of the present invention. Detailed Implementation

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] like Figure 1 As shown, this embodiment of the invention provides a via arrangement method to reduce current density, including the following steps:

[0032] S101. Select power networks whose current density exceeds a set threshold as target networks;

[0033] S102. Calibrate the power supply plate area within the target network;

[0034] S103. Identify and locate the power pins of the power supply network chip and the power pins of the load chip in the power supply flat area;

[0035] S104. Determine the shortest path between the power network chip and the load chip;

[0036] S105. Arrange network vias outside the target network parallel to the shortest path.

[0037] In one embodiment, determining the shortest path between the power network chip and the load chip includes:

[0038] Based on the power pin positions of the power network chip and the load chip, the geometric centers of the power network chip and the load chip are determined respectively, and the line connecting the two geometric centers is taken as the shortest path.

[0039] In one embodiment, determining the shortest path between the power network chip and the load chip includes:

[0040] When the power network has one power supply chip and multiple load chips, the geometric center of the power supply chip and each load chip in the power network is determined according to the power pin position of the power supply chip and the power pin position of the load chip, respectively. The geometric center of the power supply chip and the geometric center of each load chip are connected to form multiple power supply current paths.

[0041] Based on the magnitude of the current required for the normal operation of the load chip, the power supply path corresponding to the load chip with the largest required current is taken as the shortest path.

[0042] Furthermore, based on the magnitude of the current required for the normal operation of the load chip, it also includes:

[0043] Based on the magnitude of the current required for the normal operation of the load chip, the power supply paths corresponding to the multiple load chips are sorted, with higher current having higher priority.

[0044] Based on the PCB space constraints, the power supply path corresponding to the load chip with the highest priority under the PCB space constraints is selected as the shortest path.

[0045] In this embodiment, when PCB space is limited and it is not possible to simultaneously satisfy that all vias are parallel to their respective shortest paths, the design is carried out according to the power supply current path priority, and the current path corresponding to the load chip with the highest priority can be used as the shortest path.

[0046] In one embodiment, determining the shortest path between the power network chip and the load chip includes:

[0047] When the power network has multiple power supply chips and one load chip, the geometric center of each power supply chip and the load chip in the power supply network is determined according to the power pin positions of the power supply chips and the power pin positions of the load chip. The geometric center of the load chip and the geometric center of each power supply chip are connected to form multiple power supply current paths.

[0048] Based on the rated power supply current of the power supply chip, the power supply path corresponding to the power supply chip with the largest rated power supply current is taken as the shortest path.

[0049] Furthermore, based on the rated supply current of the power supply chip, it also includes:

[0050] Based on the rated power supply current of the power supply chip, the power supply current paths corresponding to multiple power supply chips are sorted, with higher current having higher priority.

[0051] Based on the rated power supply current of the power supply chip, the power supply path corresponding to the power supply chip with the highest priority corresponding to the rated power supply current is selected as the shortest path.

[0052] This invention discloses a via arrangement method for reducing current density. First, by precisely locating the power supply chip and load chip in the power network, the shortest DC path of the power network is planned. Based on this, the power supply plate area is marked, and different network signal vias are identified. Finally, the vias are arranged along the shortest DC path of the power network. This via arrangement method reduces current density and allows for the rational arrangement of signal vias, minimizing the possibility of current spikes caused by plate avoidance and vias interrupting current flow in the plate. Utilizing this via design method, device fan-out and plate design can be rationally planned in the early stages of EDA design, achieving high-density and high-efficiency PCB design, reducing the risk of exceeding power network current density limits, increasing the first-time success rate of PCB design, shortening the EDA design iteration cycle, and ultimately achieving the goal of short-cycle, low-cost development of electronic devices.

[0053] In specific implementation, the embodiments of the present invention mainly include the following steps: calibration of the power supply plate area, identification and positioning of the power supply chip and load chip power pins of the power network, determination of the shortest path for DC power supply of the power network, and arrangement of different network vias.

[0054] In this embodiment, the power supply chip for the power supply board includes 6 power pins, and the load chip includes 6 power pins. Geometric calculations determine the center points of the power supply chip and the load chip, respectively. A straight line connection between the geometric centers determines the shortest current path. The via arrangement is adjusted according to the parallel main current path method, such as... Figure 2 As shown.

[0055] The specific steps are as follows:

[0056] Step 1: Calibrating the power plane area. By displaying the power plane in the CAD tool, accurately identify and highlight the area of ​​the target power network.

[0057] Step 2: Identification and location of power supply pins of power supply network chip and load chip. The power supply network must include power supply devices and load devices. According to the law of conservation of energy, the energy supplied by the power supply device is greater than the energy obtained by the load device. In this step, it is necessary to accurately identify the power supply pins of the power supply device and the load device and find the geometric center of the power supply pin group of different devices. Use this center as the geometric position of the power supply chip and the load chip.

[0058] Step 3: Determining the shortest path for DC power supply in the power network. According to basic electrical theory, DC current is transmitted on the PCB or cable according to the shortest path theory. By connecting the geometric center of the power supply chip's power pin and the geometric center of the load chip's power pin, the shortest DC path on the power supply plate area identified in Step 1 is obtained, which is used as the main current path of the entire power supply link.

[0059] Step 4: Arrangement of different network vias. When checking the designed PCB file, different network vias should be arranged to avoid being close to the main current path of the power supply link obtained in Step 3. If the PCB layout and routing are relatively dense, different network vias can be arranged parallel to the main current path of the power supply link to minimize the impact on power supply current.

[0060] In this invention, after the PCB design is completed, the via arrangement is optimized to effectively control the PCB current density. This reduces the power supply current density, decreases PCB temperature rise, and improves system reliability and economy.

[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A via arrangement method for reducing current density, characterized in that, include: Power networks with current densities exceeding a set threshold are selected as target networks; The power supply flat panel area within the target network is calibrated; The power pins of the power network power supply chip and the power pins of the load chip in the power supply flat area are identified and located. Determining the shortest path between the power network chip and the load chip includes: When the power network has one power supply chip and multiple load chips, the geometric center of the power supply chip and each load chip in the power network is determined according to the power pin positions of the power supply chip and the load chips, respectively. The geometric center of the power supply chip and the geometric center of each load chip are connected to form multiple power supply current paths. According to the magnitude of the current required for the normal operation of the load chip, the power supply current path corresponding to the load chip with the largest required current is taken as the shortest path. When the power network has multiple power supply chips and one load chip, the geometric center of each power supply chip and the load chip in the power supply network is determined according to the power pin positions of the power supply chips and the load chip, respectively. The geometric center of the load chip and the geometric center of each power supply chip are connected to form multiple power supply current paths. According to the rated power supply current of the power supply chip, the power supply current path corresponding to the power supply chip with the largest rated power supply current is taken as the shortest path. Arrange network vias outside the target network parallel to the shortest path.

2. The via arrangement method for reducing current density according to claim 1, characterized in that, Based on the current required for the normal operation of the load chip, it also includes: Based on the magnitude of the current required for the normal operation of the load chip, the power supply paths corresponding to the multiple load chips are sorted, with higher current having higher priority. Based on the PCB space constraints, the power supply path corresponding to the load chip with the highest priority under the PCB space constraints is selected as the shortest path.

3. The via arrangement method for reducing current density according to claim 1, characterized in that, Based on the rated power supply current of the power supply chip, it also includes: Based on the rated power supply current of the power supply chip, the power supply current paths corresponding to multiple power supply chips are sorted, with higher current having higher priority. Based on the rated power supply current of the power supply chip, the power supply path corresponding to the power supply chip with the highest priority corresponding to the rated power supply current is selected as the shortest path.

4. The via arrangement method for reducing current density according to claim 1, characterized in that, The power supply plate area within the target network is calibrated in CAD software.

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