Display panel and display device

Abstract

This invention relates to the field of display technology and discloses a display panel and a display device. The display panel includes: a display area and a non-display area, the non-display area including a first pad bonding area, a chip integration area, and a fan-out area, the fan-out area being located between the chip integration area and the display area; along a second direction, at least one side of the chip integration area is provided with the first pad bonding area, the first pad bonding area including a test pad group, the test pad group including multiple test pads; multiple connecting lines electrically connected to the test pads, along a first direction, the connecting lines being located on the side of the first pad bonding area away from the display area; at least one first device group, the first device group including at least one device, along the first direction, the first device group being at least partially located between the first pad bonding area and the fan-out area. This invention is advantageous for achieving narrow bezels and also helps to reduce testing difficulty.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] As the display market continues to develop, consumers are becoming increasingly demanding in terms of the visual effects of displays. They not only require diverse appearance designs but also high screen-to-body ratios. As a result, full-screen technology has emerged to meet these needs through ultra-narrow bezels or even borderless designs. Typically, full-screen technology aims for a screen-to-body ratio of 90% or higher, maximizing the display area and improving the visual effect while keeping the total display area constant.

[0003] Therefore, there is an urgent need for a narrow bezel design solution to meet consumer demand. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and display device that facilitate the realization of narrow bezels and at the same time helps to reduce the difficulty of testing.

[0005] This invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area, the non-display area including a first pad bonding area, a chip integration area, and a fan-out area, the fan-out area being located between the chip integration area and the display area; the display area including a plurality of signal lines extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting; the chip integration area including a driver chip; the fan-out area including a plurality of fan-out traces, the signal lines being electrically connected to the driver chip through the fan-out traces; along the second direction, at least one side of the chip integration area is provided with a first pad bonding area, the first pad bonding area including a test pad group, the test pad group including a plurality of test pads; a plurality of connecting lines electrically connected to the test pads, along the first direction, the connecting lines being located on the side of the first pad bonding area away from the display area; and at least one first device group, the first device group including at least one device, along the first direction, the first device group being at least partially located between the first pad bonding area and the fan-out area.

[0006] Based on the same idea, the present invention also provides a display device, including the display panel provided by the present invention.

[0007] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0008] The display panel provided by this invention includes a first pad bonding area in the non-display area. Along a second direction, at least one side of the chip integration area is provided with the first pad bonding area. The display panel also includes multiple connecting lines electrically connected to test pads. Along a first direction, the connecting lines are located on the side of the first pad bonding area away from the display area. The display panel also includes at least one first device group, which includes at least one device. Along the first direction, at least a portion of the first device group is located between the first pad bonding area and the fan-out area. Since the width of the chip integration area along the second direction is typically smaller than the width of the display area along the second direction, the fan-out area used to set the fan-out traces is typically a fan-shaped structure. Furthermore, the width of the edge of the fan-out area near the display area along the second direction is greater than the width of its edge near the chip integration area along the second direction. Therefore, a certain space exists between the first pad bonding area and the fan-out area, which can be used to set at least a portion of the first device group. In this case, the setting of the first device group does not affect the arrangement of the connecting lines electrically connected to the test pads. Simultaneously, the first device group does not need to be located along the second direction on at least one side of the first pad bonding area, thus facilitating the achievement of a narrow bezel. Meanwhile, the first pad bonding area includes a test pad group, which comprises multiple test pads used to test the performance of the display panel. Along the first direction, the first device group is at least partially located between the first pad bonding area and the fan-out area, thereby increasing the placement space of the test pad group in the second direction. This, in turn, increases the width of each test pad in the test pad group along the second direction, effectively increasing the size of each test pad in the test pad group and thus reducing testing difficulty.

[0009] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0010] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0012] Figure 1 This is a plan view of a display panel provided by the present invention;

[0013] Figure 2 yes Figure 1 A partially enlarged schematic diagram of the display panel;

[0014] Figure 3 yes Figure 1 Another partially enlarged schematic diagram of the display panel;

[0015] Figure 4 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0016] Figure 5 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0017] Figure 6 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0018] Figure 7 This is a partially enlarged schematic diagram of another display panel provided by the present invention;

[0019] Figure 8 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0020] Figure 9 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0021] Figure 10 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0022] Figure 11 yes Figure 1 Another partially enlarged schematic diagram of the aforementioned display panel;

[0023] Figure 12 This is a plan view of a display device provided by the present invention. Detailed Implementation

[0024] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0029] Figure 1 This is a plan view of a display panel provided by the present invention. Figure 2 yes Figure 1 A partially enlarged schematic diagram of the display panel, for reference. Figure 1 and Figure 2 This embodiment provides a display panel, including:

[0030] Display area AA and non-display area NA that at least partially surrounds display area AA, non-display area NA includes first pad bonding area NA1, chip integration area NA2 and fan-out area NA3, fan-out area NA3 is located between chip integration area NA2 and display area AA;

[0031] Display area AA1 includes multiple signal lines S1 extending along a first direction X and arranged along a second direction Y, where the first direction X and the second direction Y intersect.

[0032] The chip integration area NA2 includes the driver chip 10;

[0033] The fan-out area NA3 includes multiple fan-out traces S2, and the signal line S1 is electrically connected to the driver chip 10 through the fan-out traces S2.

[0034] Along the second direction Y, at least one side of the chip integration area NA2 is provided with a first pad bonding area NA1, the first pad bonding area NA1 includes a test pad group 20, and the test pad group 20 includes a plurality of test pads 21.

[0035] Multiple connecting lines 30 are electrically connected to the test pad 21 along the first direction X, and the connecting lines 30 are located on the side of the first pad bonding area NA1 away from the display area AA.

[0036] At least one first device group 40, the first device group 40 including at least one device 41, along a first direction X, the first device group 40 being at least partially located between a first pad bonding area NA1 and a fan-out area NA3.

[0037] Specifically, the display panel provided in this embodiment includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The display area AA generally contains sub-pixels, scan lines, signal lines, pixel electrodes, etc., capable of display functions. Alternatively, when the display panel also has touch functionality, touch electrodes, touch signal lines, etc., may also be provided within the display area AA. The non-display area NA may contain driving circuits such as scan driving circuits. The display panel of this embodiment includes, but is not limited to, the above-described structure. This embodiment does not specifically limit the structure of the display panel; however, for details, please refer to the structures of display panels in related technologies for understanding.

[0038] It should be noted that, Figure 1 The example shows a non-display area NA surrounding a display area AA. In other embodiments of the present invention, the non-display area NA may also partially surround the display area AA, which will not be described in detail here.

[0039] Display area AA1 includes multiple signal lines S1 extending along a first direction X and arranged along a second direction Y. The first direction X and the second direction Y intersect, or optionally, the first direction X and the second direction Y are perpendicular. Non-display area NA includes a chip integration area NA2 and a fan-out area NA3. The fan-out area NA3 is located between the chip integration area NA2 and the display area AA. The chip integration area NA2 includes a driver chip 10, and the fan-out area NA3 includes multiple fan-out traces S2. The signal lines S1 are electrically connected to the driver chip 10 through the fan-out traces S2. That is, the signal lines S1 in display area AA are electrically connected to the fan-out traces S2, and the fan-out traces S2 are electrically connected to the driver chip 10, thereby realizing the electrical connection between the signal lines S1 and the driver chip 10.

[0040] It should be noted that, Figure 1 The example shows a one-to-one correspondence between signal line S1 and fan-out trace S2, and signal line S1 and its corresponding fan-out trace S2 are electrically connected. In other embodiments of the present invention, the fan-out area NA3 may also include a gating circuit. By setting the gating circuit, one fan-out trace S2 can be electrically connected to two or more signal lines S1. The present invention will not be described in detail here.

[0041] In the display panel provided in this embodiment, the non-display area NA further includes a first pad bonding area NA1. Along the second direction Y, at least one side of the chip integration area NA2 is provided with the first pad bonding area NA1. The display panel also includes a plurality of connecting lines 30, which are electrically connected to the test pad 21. Along the first direction X, the connecting lines 30 are located on the side of the first pad bonding area NA1 away from the display area AA. The display panel also includes at least one first device group 40, which includes at least one device (…). Figure 2(Not shown in the diagram), along the first direction X, the first device group 40 is at least partially located between the first pad bonding area NA1 and the fan-out area NA3. Since the width of the chip integration area NA2 along the second direction Y is typically smaller than the width of the display area AA along the second direction Y, the fan-out area NA3 used to set the fan-out trace S2 is typically a fan-shaped structure. Furthermore, the width of the edge of the fan-out area NA3 near the display area AA along the second direction Y is greater than the width of its edge near the chip integration area NA2 along the second direction Y. Therefore, there is a certain space between the first pad bonding area NA1 and the fan-out area NA3, which can be used to set at least a portion of the first device group 40. In this case, the setting of the first device group 40 does not affect the arrangement of the connection line 30 electrically connected to the test pad 21. Simultaneously, the first device group 40 does not need to be set along the second direction Y on at least one side of the first pad bonding area NA1, thus facilitating the achievement of a narrow bezel.

[0042] Meanwhile, the first pad bonding area NA1 includes a test pad group 20, which includes multiple test pads 21. These test pads 21 are used to test the performance of the display panel. Along the first direction X, the first device group 40 is at least partially located between the first pad bonding area NA1 and the fan-out area NA3. This increases the placement space of the test pad group 20 in the second direction Y, thereby increasing the width of each test pad 21 in the test pad group 20 along the second direction Y, and consequently, increasing the size of each test pad 21 in the test pad group 20, thus reducing the difficulty of testing.

[0043] It should be noted that, Figure 2 The example shown illustrates a first device group 40 including 6 test pads 21. In other embodiments of the present invention, the first device group 40 may also include other numbers of test pads 21, and the present invention does not specifically limit this.

[0044] Continue to refer to Figure 1 and Figure 2 In some optional embodiments, the fan-out area NA3 includes a first edge A1, which is located on one side of the fan-out area NA3 along the second direction Y and along the first direction X and toward the direction away from the chip integration area NA2. The distance between the first edge A1 and the display area AA gradually decreases.

[0045] Specifically, since the length of the chip integration area NA2 along the second direction Y is usually less than the width of the display area AA along the second direction Y, the fan-out area NA3 used to set the fan-out trace S2 is usually a fan-shaped structure, and the width of the edge of the fan-out area NA3 near the display area AA along the second direction Y is greater than the width of its edge near the chip integration area NA2 along the second direction Y. Therefore, along the first direction X and in the direction away from the chip integration area NA2, the distance between the first edge A1 in the fan-out area NA3 and the display area AA gradually decreases, so there is a certain space between the first pad bonding area NA1 and the fan-out area NA3, so that at least a part of the first device group 40 can be set in this space.

[0046] Figure 3 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 3 In some alternative embodiments, devices 41 in the same first device group 40 are arranged along the extension direction of the first edge A1 adjacent to them.

[0047] Specifically, along the second direction Y, the first device group 40 and the first edge A1 located on the same side of the chip integration area NA2 are arranged adjacent to each other. The device 41 in the first device group 40 is located between the adjacent first edge A1 and the first pad bonding area NA1. The devices 41 in the same first device group 40 are arranged along the extension direction of the adjacent first edge A1. That is, the devices 41 in the first device group 40 are arranged in accordance with the extension direction of the first edge A1. This is beneficial to maximize the use of the space between the first pad bonding area NA1 and the fan-out area NA3. It can also save the space between the first pad bonding area NA1 and the fan-out area NA3 to increase the length of some test pads 21 in the test pad group 20 along the first direction X. That is, it is beneficial to increase the size of each test pad 21 in the test pad group 20, thereby reducing the difficulty of testing.

[0048] Continue to refer to Figure 1 and Figure 3 In some alternative embodiments, each device 41 in the first device group 40 is configured to correspond to a portion of the test pads 21.

[0049] Specifically, each device 41 in the first device group 40 is set to correspond with a portion of the test pads 21, that is, each device 41 in the first device group 40 can be placed discretely, thereby reducing the overall setting restrictions of the first device group 40. This is beneficial to the length of some test pads 21 in the test pad group 20 along the first direction X, that is, it is beneficial to increase the size of each test pad 21 in the test pad group 20, thereby reducing the difficulty of testing.

[0050] Figure 4 yes Figure 1Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 4 In some alternative embodiments, the display panel includes a second edge A2, which is located on the side of the display panel where the driver chip 10 is located;

[0051] Along the first direction X, and towards the direction away from the chip integration area NA2, the spacing between the test pad 21 and the second edge A2 in the test pad group 20 gradually decreases.

[0052] Specifically, the display panel includes a second edge A2, which is located on the side of the display panel where the driver chip 10 is located. Along the first direction X, and in a direction away from the chip integration area NA2, the distance between the test pads 21 and the second edge A2 in the test pad group 20 gradually decreases. That is, in the test pad group 20, the test pads 21 that are farther away from the chip integration area NA2 along the second direction Y have a smaller distance from the second edge A2 along the first direction X. This results in a larger space between the test pad group 20 and the fan-out area NA3, which is beneficial for setting up more devices and for achieving a narrow bezel.

[0053] Figure 5 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 5 In some optional embodiments, the test pad 21 includes a first test pad 211 and a second test pad 212, wherein the length of the first test pad 211 along the first direction X is greater than the length of the second test pad 212 along the first direction X, and / or, the width of the first test pad 211 along the second direction Y is greater than the width of the second test pad 212 along the second direction Y.

[0054] Specifically, the test pad 21 includes a first test pad 211 and a second test pad 212, wherein the size of the first test pad 211 is larger than the size of the second test pad 212. Specifically, the size of the first test pad 211 can be made larger than the size of the second test pad 212 by setting the length of the first test pad 211 along the first direction X to be greater than the length of the second test pad 212 along the first direction X. Alternatively, the size of the first test pad 211 can be made larger than the size of the second test pad 212 by setting the width of the first test pad 211 along the second direction Y to be greater than the width of the second test pad 212 along the second direction Y. Alternatively, the size of the first test pad 211 can be made larger than the size of the second test pad 212 by simultaneously setting the length of the first test pad 211 along the first direction X to be greater than the length of the second test pad 212 along the first direction X, and the width of the first test pad 211 along the second direction Y to be greater than the width of the second test pad 212 along the second direction Y.

[0055] The size of the first test pad 211 is larger than the size of the second test pad 212, thus meeting different testing requirements. The larger first test pad 211 can be used as the test pad for signals requiring primary attention; for example, the test pads for clock signals, start signals, and power supply voltage signals can be set as the first test pad 211. Of course, in other embodiments of the present invention, test pads for other signals can also be set as the first test pad 211, which will not be elaborated further here. Similarly, the smaller second test pad 212 can be used as the test pad for signals of secondary interest; for example, the test pads for output signals and transistor source-drain signals can be set as the second test pad 212. Of course, in other embodiments of the present invention, test pads for other signals can also be set as the second test pad 212, which will not be elaborated further here.

[0056] Optionally, by reducing the size of the second test pad 212, the space for setting the second test pad 212 can be saved to increase the size of the first test pad 211, thereby increasing the size of the first test pad 211.

[0057] Continue to refer to Figure 1 and Figure 5 In some alternative embodiments, at least two adjacent test pads 21 partially overlap along the first direction X.

[0058] Specifically, along the first direction X, at least two adjacent test pads 21 partially overlap, that is, at least two adjacent test pads 21 are staggered in the second direction Y, that is, at least two adjacent test pads 21 are not arranged along the second direction Y, so that the size of some test pads 21 can be increased with minimal changes to the shape of each test pad 21 in the test pad group 20.

[0059] It should be noted that, Figure 5 The example shows an example of an alternating arrangement of the test pads 21 in the test pad group 20. In other embodiments of the present invention, the test pads 21 in the test pad group 20 may also adopt other alternating arrangement structures, which will not be described in detail here.

[0060] Figure 6 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 6 In some alternative embodiments, the second test pad 212 is a strip structure extending along the first direction X.

[0061] Specifically, the second test pad 212 is a strip structure extending along the first direction X, that is, the width of the second test pad 212 along the second direction Y is small, so the space occupied by the second test pad 212 in the second direction Y is small, thereby increasing the width of the first test pad 211 along the second direction Y, thereby increasing the size of the first test pad 211.

[0062] Figure 7 This is a partially enlarged schematic diagram of another display panel provided by the present invention, for reference. Figure 7 In some alternative embodiments, the display panel includes at least one irregular edge S3, the extension direction of which intersects the first direction X and the second direction Y;

[0063] At least some of the connecting lines 30 adjacent to the irregular edge S3 extend in the direction of extension of the irregular edge S3.

[0064] Specifically, the display panel provided in this embodiment is an irregularly shaped display panel, which includes at least one irregularly shaped edge S3. The extension direction of the irregularly shaped edge S3 intersects with the first direction X and the extension direction of the irregularly shaped edge S3 intersects with the second direction Y. At least a portion of the connecting lines 30 adjacent to the irregularly shaped edge S3 extend at least partially along the extension direction of the irregularly shaped edge S3, thereby enabling the connecting lines 30 adjacent to the irregularly shaped edge S3 to be electrically connected to their corresponding test pads 21 in the irregularly shaped display panel.

[0065] It should be noted that the number and shape of the irregular edges S3 in the irregular display panel are not specifically limited. The irregular edges S3 can be straight or curved, and this invention will not elaborate on them here.

[0066] Figure 8 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 8 In some optional embodiments, the display panel further includes a fan-out trace test pad 50, which is electrically connected to the fan-out trace S2 and is arranged along the extension direction of the second direction Y or the first edge A1.

[0067] Along the first direction X, the fan-out trace test pad 50 is located between the fan-out area NA3 and the connecting line 30, and along the second direction Y, the fan-out trace test pad 50 is located between the chip integration area NA2 and the first pad bonding area NA1.

[0068] Specifically, the display panel also includes a fan-out trace test pad 50, which is electrically connected to the fan-out trace S2. The signal on the fan-out trace S2 can be tested through the fan-out trace test pad 50. The fan-out trace test pad 50 is arranged along the second direction Y and along the first direction X. The fan-out trace test pad 50 is located between the fan-out area NA3 and the connecting line 30. Along the second direction Y, the fan-out trace test pad 50 is located between the chip integration area NA2 and the first pad bonding area NA1. This allows for the efficient placement of the fan-out trace test pad 50 within the space between the fan-out area NA3, the connecting line 30, the chip integration area NA2, and the first pad bonding area NA1, which is beneficial for achieving a narrow bezel.

[0069] It should be noted that, Figure 8 The example shown illustrates fan-out trace test pads 50 arranged along the second direction Y. In other embodiments of the present invention, since the fan-out trace test pads 50 are disposed within the space surrounded by the fan-out area NA3, the connecting line 30, the chip integration area NA2, and the first pad bonding area NA1, the fan-out trace test pads 50 can also be arranged along the extension direction of the first edge A1 of the fan-out area NA3. Of course, in other embodiments of the present invention, the fan-out trace test pads 50 disposed within the space surrounded by the fan-out area NA3, the connecting line 30, the chip integration area NA2, and the first pad bonding area NA1 can also adopt other arrangements, which will not be described in detail here.

[0070] Figure 9 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 9 In some alternative embodiments, the display panel further includes a fingerprint feedback chip 60, which is located at least partially between the first pad bonding area NA1 and the fan-out area NA3 along the first direction X.

[0071] Specifically, the display panel provided in this embodiment has a fingerprint recognition function. The display panel also includes a fingerprint feedback chip 60. Along the first direction X, the fingerprint feedback chip 60 is at least partially located between the first pad bonding area NA1 and the fan-out area NA3. The fingerprint feedback chip 60 can be set in the space between the first pad bonding area NA1 and the fan-out area NA3, which is conducive to achieving a narrow bezel while setting the fingerprint feedback chip 60.

[0072] Figure 10 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 10 In some alternative embodiments, the display panel further includes a marking area 70 along the first direction X, the marking area 70 being at least partially located between the first pad bonding area NA1 and the fan-out area NA3.

[0073] Specifically, the display panel is provided with a marking area 70. Along the first direction X, the marking area 70 is at least partially located between the first pad bonding area NA1 and the fan-out area NA3. The marking area 70 can be set in the space between the first pad bonding area NA1 and the fan-out area NA3, which increases the setting area of ​​the marking area 70 and helps to achieve a narrow bezel.

[0074] Figure 11 yes Figure 1 Another partially enlarged schematic diagram of the display panel, see reference. Figure 1 and Figure 11 In some alternative embodiments, the display panel further includes silver paste 80, which is located at least partially between the first pad bonding area NA1 and the fan-out area NA3 along the first direction X.

[0075] Specifically, the display panel is provided with silver paste 80. Along the first direction X, the silver paste 80 is at least partially located between the first pad bonding area NA1 and the fan-out area NA3. The space between the first pad bonding area NA1 and the fan-out area NA3 can be used to set the silver paste 80, which increases the setting area of ​​the silver paste 80 and helps to achieve a narrow bezel.

[0076] It should be noted that in other embodiments of the present invention, the space between the first pad bonding area NA1 and the fan-out area NA3 along the first direction X can also be used to set other devices, which will not be described in detail here.

[0077] In some alternative embodiments, please refer to Figure 12 , Figure 12 This is a plan view of a display device provided by the present invention. The display device 1000 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 12 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device 1000 provided in this embodiment can also be other display devices 1000 with display functions, such as computers, televisions, and in-vehicle display devices. This invention does not impose specific limitations on these. The display device 1000 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0078] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0079] The display panel provided by this invention includes a first pad bonding area in the non-display area. Along a second direction, at least one side of the chip integration area is provided with the first pad bonding area. The display panel also includes multiple connecting lines electrically connected to test pads. Along a first direction, the connecting lines are located on the side of the first pad bonding area away from the display area. The display panel also includes at least one first device group, which includes at least one device. Along the first direction, at least a portion of the first device group is located between the first pad bonding area and the fan-out area. Since the width of the chip integration area along the second direction is typically smaller than the width of the display area along the second direction, the fan-out area used to set the fan-out traces is typically a fan-shaped structure. Furthermore, the width of the edge of the fan-out area near the display area along the second direction is greater than the width of its edge near the chip integration area along the second direction. Therefore, a certain space exists between the first pad bonding area and the fan-out area, which can be used to set at least a portion of the first device group. In this case, the setting of the first device group does not affect the arrangement of the connecting lines electrically connected to the test pads. Simultaneously, the first device group does not need to be located along the second direction on at least one side of the first pad bonding area, thus facilitating the achievement of a narrow bezel. Meanwhile, the first pad bonding area includes a test pad group, which comprises multiple test pads used to test the performance of the display panel. Along the first direction, the first device group is at least partially located between the first pad bonding area and the fan-out area, thereby increasing the placement space of the test pad group in the second direction. This, in turn, increases the width of each test pad in the test pad group along the second direction, effectively increasing the size of each test pad in the test pad group and thus reducing testing difficulty.

[0080] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized by, include: A display area and a non-display area at least partially surrounding the display area, the non-display area including a first pad bonding area, a chip integration area and a fan-out area, the fan-out area being located between the chip integration area and the display area; The display area includes multiple signal lines extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect. The chip integration area includes a driver chip; The fan-out area includes multiple fan-out traces, and the signal lines are electrically connected to the driver chip through the fan-out traces. Along the second direction, at least one side of the chip integration area is provided with the first pad bonding area, the first pad bonding area includes a test pad group, and the test pad group includes a plurality of test pads; Multiple connecting lines are electrically connected to the test pads, and along the first direction, the connecting lines are located on the side of the first pad bonding area away from the display area; At least one first device group, the first device group comprising at least two devices, wherein the first device group is at least partially located between the first pad bonding area and the fan-out area along the first direction; The fan-out area includes a first edge, which is located on one side of the fan-out area along the second direction and is oriented away from the chip integration area along the first direction. The distance between the first edge and the display area gradually decreases. The devices in the same first device group are arranged along the extension direction of the first edge adjacent to them.

2. The display panel according to claim 1, characterized in that, Each of the devices in the first device group is configured to correspond to a portion of the test pads.

3. The display panel according to claim 1, characterized in that, The display panel includes a second edge, which is located on the side of the display panel where the driver chip is located; Along the first direction and toward a direction away from the chip integration area, the spacing between the test pads and the second edge in the test pad group gradually decreases.

4. The display panel according to claim 1, characterized in that, The test pad includes a first test pad and a second test pad, wherein the length of the first test pad along the first direction is greater than the length of the second test pad along the first direction, and / or the width of the first test pad along the second direction is greater than the width of the second test pad along the second direction.

5. The display panel according to claim 4, characterized in that, Along the first direction, at least two adjacent test pads partially overlap.

6. The display panel according to claim 4, characterized in that, The second test pad is a strip-shaped structure extending along the first direction.

7. The display panel according to claim 1, characterized in that, The display panel includes at least one irregular edge, and the extension direction of the irregular edge intersects with the first direction and the second direction; At least a portion of the connecting lines adjacent to the irregular edge extend at least partially along the extension direction of the irregular edge.

8. The display panel according to claim 1, characterized in that, The display panel also includes a fan-out trace test pad, which is electrically connected to the fan-out trace and is arranged along the extension direction of the second direction or the first edge. Along the first direction, the fan-out trace test pad is located between the fan-out area and the connection line, and along the second direction, the fan-out trace test pad is located between the chip integration area and the first pad bonding area.

9. The display panel according to claim 1, characterized in that, The display panel also includes a fingerprint feedback chip, which is located at least partially between the first pad bonding area and the fan-out area along the first direction.

10. The display panel according to claim 1, characterized in that, The display panel also includes a coding area, which is located at least partially between the first pad bonding area and the fan-out area along the first direction.

11. The display panel according to claim 1, characterized in that, The display panel also includes silver paste, which is located at least partially between the first pad bonding area and the fan-out area along the first direction.

12. A display device comprising: The display device includes the display panel as described in any one of claims 1-11.

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