A large on-chip dual-port synchronous memory

Abstract

The application discloses a large-capacity dual-port synchronous memory on chip, which comprises a port controller, a clock controller, an address decoder, a read-write controller, three storage arrays and a storage array with clock feedback. The port controller receives input data, addresses, write enable signals and the like of two ports, converts the signals into internal signals, converts internal output signals into two-port output data; the clock controller is used for receiving a clock and generating internal clock; the address decoder is used for converting internal address signals into word line driving signals and read-write control signals; the read-write controller is used for receiving read-write control signals, writing internal input signals into the storage array, or reading data in the storage array as internal output signals; the four storage arrays are used for storing data and simultaneously providing a clock feedback path. The application can internally generate timing signals, realize synchronous reading and writing of two ports, has the advantages of flexibility, small area, large capacity and the like, and can realize chip high-capacity data buffering and the like application scenarios.

Description

Technical Field

[0001] This invention relates to an on-chip high-capacity dual-port synchronous memory, and more particularly to an on-chip 4K×72 dual-port synchronous read / write memory, which can be used as a storage buffer for on-chip massive data processing and transmission, and belongs to the field of integrated circuits. Background Technology

[0002] As a vital resource in electronic systems, memory typically plays roles such as input data buffering, intermediate data temporary storage, and output result storage and access. To ensure the normal operation of circuit systems such as processors, AD / DA converters, and high-speed interface managers, a large amount of memory is usually required to achieve high-speed, efficient, and large-scale data processing tasks. It is a crucial circuit module for ensuring the normal operation of high-performance circuit systems.

[0003] With the rapid advancements in 5G technology, artificial intelligence, and big data, there is a growing demand for high-performance, fast-running integrated circuits and electronic systems. This urgent need has spurred the rapid development of integrated circuit technology, primarily reflected in the continuous shrinking of individual transistor sizes. Thanks to this continuous reduction in device size, integrated circuits exhibit advantages such as lower power consumption, faster speeds, and lower prices. On-chip static RAM (SRAM), as a crucial component of integrated circuits, has profoundly benefited from the reduction in process size. However, relying solely on improvements in device performance to enhance memory performance is insufficient to meet the demands of on-chip data processing mechanisms in terms of storage capacity and port control. Therefore, high-capacity, multi-port read / write design methods for memory at new process nodes have remained a hot research topic in the memory field. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a large-capacity on-chip memory that can be synchronously read and written to both ports. It can achieve a storage capacity of 4K×72 and a read / write width, and can internally generate timing control signals for two ports to achieve dual-port read and write. It also has a storage array timing feedback path, which can measure the maximum operating frequency of the storage array in real time to ensure that the memory will not experience timing disorder due to excessively high clock frequency. This ensures high-speed read and write characteristics and the reliability of stored data, and meets the requirements of integrated circuit systems for high-speed, large-capacity, and flexible dual-port read and write of memory.

[0005] The technical solution of this invention is:

[0006] An on-chip high-capacity dual-port synchronous memory includes a port controller, a clock controller, an address decoder, a read / write controller, a memory array with a clock feedback path, a first memory array, a second memory array, and a third memory array.

[0007] Port Controller: Receives address signals, byte-width write enable signals, read / write control signals, and input data signals from two external ports. Based on the internal clock signal from the clock controller, it converts these signals into internal address signals, internal byte-width write enable signals, internal read / write control signals, and internal input data signals. It then sends the internal address signals and internal read / write control signals to the address decoder, and the internal read / write control signals, internal input data signals, and internal byte-width write enable signals to the read / write controller. Simultaneously, it converts the internal output data signals from the read / write controller into external data output signals and outputs them.

[0008] Clock controller: Used to receive external clock and enable signal, generate clock feedback signal and output to memory array with clock feedback path; based on the delayed clock signal fed back from memory array with clock feedback path, generate internal clock signal to drive other memory modules to operate;

[0009] Address decoder: Converts internal address signals and read / write control signals into word line drive signals and read / write control signals according to internal clock signals. The word line drive signals are transmitted to four memory arrays to control word lines to open, and the read / write control signals are transmitted to the read / write controller to control the read / write units to perform write or read operations.

[0010] Read / write controller: Receives internal read / write control signals, internal clock signals, internal input data signals, and internal byte width write enable signals. Based on the signal status, it writes the internal input data signals into the storage array, or reads the data from the storage array and converts it into internal output data signals to send to the port controller.

[0011] First storage array, second storage array, and third storage array: Based on the word line open status and bit line data transmission status, they store the data on the bit lines into the storage cells, or output the data in the storage cells to the bit lines;

[0012] A memory array with a clock feedback path: Based on the word line open status and bit line data transmission status, it stores data on the bit lines into memory cells or outputs data in memory cells to the bit lines; it receives clock feedback signals and feeds back delayed clock signals to the clock controller.

[0013] Preferably, the memory, based on the states of the external clock signal CLK, the external enable signal EN, the A port read / write control signal RDB_WR_A, and the B port read / write control signal RDB_WR_B, writes the A port input data signal DI_A[71:0] into the memory cell corresponding to the A port address ADDR_A[11:0], and writes the B port input data signal DI_B[71:0] into the memory cell corresponding to the B port address ADDR_B[11:0]; or reads the data from the memory cell corresponding to the A port address ADDR_A[11:0] and outputs it through the A port external data output signal DO_A[71:0], and reads the data from the memory cell corresponding to the B port address ADDR_B[11:0] and outputs it through the B port external data output signal DO_B[71:0].

[0014] Read and write operations are performed when EN is 1, and no operations are performed when EN is 0; write or read operations must be performed on the rising edge of CLK.

[0015] When RDB_WR_X is 1, it is a write operation; when it is 0, it is a read operation. BWE_X[7:0] are the byte width write enable signals of port X, which are used to determine whether the corresponding byte is written when port X is in a write operation. X is either A or B.

[0016] The control relationship is as follows: at the start of the write operation, if BWE_X[0] is 1, then DI_X[7:0] and DI_X

[64] are written to memory; if BWE_X[1] is 1, then DI_X[15:8] and DI_X

[65] are written to memory; if BWE_X[2] is 1, then DI_X[23:16] and DI_X

[66] are written to memory; if BWE_X[3] is 1, then DI_X[31:24] and DI_X

[67] are written to memory. Write to memory; if BWE_X[4] is 1, then DI_X[39:32] and DI_X

[68] are written to memory; if BWE_X[5] is 1, then DI_X[47:40] and DI_X

[69] are written to memory; if BWE_X[6] is 1, then DI_X[55:48] and DI_X

[70] are written to memory; if BWE_X[7] is 1, then DI_X[63:56] and DI_X

[71] are written to memory.

[0017] Preferably, the port controller input signals include the external enable signal EN, port A address ADDR_A[11:0], port B address ADDR_B[11:0], port A byte width write enable signal BWE_A[7:0], port B byte width write enable signal BWE_B[7:0], port A read / write control signal RDB_WR_A, port B read / write control signal RDB_WR_B, port A input data signal DI_A[71:0], port B input data signal DI_B[71:0], and internal output data signal DO_T[71:0]. The internal clock signals for port A (CLK_IN_A), port B (CLK_IN_B), and port A / B switching signal (TRANSFER) are used to connect external signals. EN, ADDR_A[11:0], ADDR_B[11:0], BWE_A[7:0], BWE_B[7:0], RDB_WR_A, RDB_WR_B, DI_A[71:0], and DI_B[71:0] are used to connect external signals, while DO_T[71:0], CLK_IN_A, CLK_IN_B, and TRANSFER are used to connect internal signals.

[0018] The port controller output signals include the external data output signal DO_A[71:0] for port A, the external data output signal DO_B[71:0] for port B, the internal input data signal DI_T[71:0], the internal byte width write enable signal BWE_T[7:0], the internal address signal ADDR_T[11:0], and the internal read / write control signal RDB_WR_T. Among them, DO_A[71:0] and DO_B[71:0] are connected to external signals, and DI_T[71:0], BWE_T[7:0], ADDR_T[11:0], and RDB_WR_T are connected to internal signals.

[0019] Preferably, the port controller includes latches LAT9, LAT10, LAT13, LAT14, LAT16, LAT17, LAT19, LAT20, and LAT22; and two-input multiplexers MUX12, MUX15, MUX18, and MUX21.

[0020] DO_T[71:0] is connected to the D terminal of latches LAT9 and LAT10 at the same time, EN is connected to the CD terminal of latches LAT9 and LAT10 at the same time, CLK_IN_A is connected to the CP terminal of latches LAT9, CLK_IN_B is connected to the CP terminal of latches LAT10, the Q terminal of latches LAT9 is connected to DO_A[71:0], and the Q terminal of latches LAT10 is connected to DO_B[71:0].

[0021] DI_A[71:0] connects to the D terminal of LAT11, CLK_IN_A connects to the CP terminal of latch LAT11, EN connects to the CD terminals of latches LAT11 and LAT13, the Q terminal of latch LAT11 connects to the A1 terminal of two-input multiplexer MUX12, DI_B[71:0] connects to the A0 terminal of two-input multiplexer MUX12, TRANSFER connects to the S terminal of two-input multiplexer MUX12, the Z terminal of two-input multiplexer MUX12 connects to the D terminal of latch LAT13, CLK_IN_B connects to the CP terminal of latch LAT13, and the Q terminal of latch LAT13 connects to DI_T[71:0].

[0022] ADDR_A[11:0] connects to the D terminal of latch LAT14, CLK_IN_A connects to the CP terminal of latch LAT14, EN connects to the CD terminals of latches LAT14 and LAT16, the Q terminal of latch LAT14 connects to the A1 terminal of two-input multiplexer MUX15, ADDR_B[11:0] connects to the A0 terminal of two-input multiplexer MUX15, TRANSFER connects to the S terminal of two-input multiplexer MUX15, the Z terminal of two-input multiplexer MUX15 connects to the D terminal of latch LAT16, CLK_IN_B connects to the CP terminal of latch LAT16, and the Q terminal of latch LAT16 connects to ADDR_T[11:0].

[0023] BWE_A[7:0] connects to the D terminal of latch LAT17, CLK_IN_A connects to the CP terminal of latch LAT17, EN connects to the CD terminals of latches LAT17 and LAT19, the Q terminal of latch LAT17 connects to the A1 terminal of two-input multiplexer MUX18, BWE_B[7:0] connects to the A0 terminal of two-input multiplexer MUX18, TRANSFER connects to the S terminal of two-input multiplexer MUX18, the Z terminal of two-input multiplexer MUX18 connects to the D terminal of latch LAT19, CLK_IN_B connects to the CP terminal of latch LAT19, and the Q terminal of latch LAT19 connects to BWE_T[7:0].

[0024] RDB_WR_A is connected to the D terminal of latch LAT20, CLK_IN_A is connected to the CP terminal of latch LAT20, EN is connected to the CD terminals of latches LAT20 and LAT22, the Q terminal of latch LAT20 is connected to the A1 terminal of two-input multiplexer MUX21, RDB_WR_B is connected to the A0 terminal of two-input multiplexer MUX21, TRANSFER is connected to the S terminal of two-input multiplexer MUX21, the Z terminal of two-input multiplexer MUX21 is connected to the D terminal of latch LAT22, CLK_IN_B is connected to the CP terminal of latch LAT22, and the Q terminal of latch LAT22 is connected to RDB_WR_T.

[0025] Preferably, the clock controller includes latches LAT23, LAT26, LAT30, LAT31, register DFF36, delays DLY24, DLY25, DLY27, XOR gate XOR28, PMOS transistor P29, XNOR gate XNOR32, inverters INV33, INV35, and buffer BUF34.

[0026] EN connects to the drain (D) terminals of latches LAT23, LAT26, LAT30, and LAT31; CLK connects to the CP terminal of latch LAT23 and the input terminal of delayer DLY24; the output terminal of delayer DLY24 connects to the CD terminal of latch LAT23; the Q terminal of latch LAT23 connects to the CP terminal of latch LAT31 and one input terminal of XOR gate XOR28; the QN terminal of latch LAT23 connects to the input terminal of delayer DLY25; the output terminal of delayer DLY25 connects to the CP terminal of latch LAT26 and the input terminal of delayer DLY27; the output terminal of delayer DLY27 connects to the CD terminal of latch LAT26; the Q terminal of latch LAT26 connects to the other input terminal of XOR28, the gate of PMOS transistor P29, and the CP terminal of latch LAT30; the output terminal of XOR28 connects to the clock feedback signal C. LK_FEEDBACKOUT; The delayed clock signal CLK_FEEDBACKIN is connected to the drain of PMOS transistor P29 and the CD terminals of latches LAT30 and LAT31. The Q terminal of latch LAT30 is connected to one end of the XNOR gate XNOR32 and CLK_IN_B, and the Q terminal of latch LAT31 is connected to the other end of the XNOR gate XNOR32 and CLK_IN_A. The output of the XNOR gate XNOR32 is connected to the input of buffer BUF34 and CLK_IN. The output of inverter INV33 is connected to the CD terminals of register DFF36. The output of buffer BUF34 is connected to the CP terminal of register DFF36. The Q terminal of register DFF36 is connected to TRANSFER. The QN terminal is connected to the input of inverter INV35. The output of inverter INV35 is connected to the D terminal of register DFF36.

[0027] Preferably, the address decoder consists of a word line decoder and a read / write control decoder;

[0028] The word line decoder converts the internal address signals into word line enable signals based on ADDR_T[11:3] and CLK_IN at each clock cycle, including: a first word line signal WL0[255:0] and a second word line signal WL1[255:0]. Each address code corresponds to a word line enable state. The first word line signal WL0[255:0] connects the memory array with the clock feedback path to the WL[255:0] port of the first memory array, and the second word line signal WL1[255:0] connects the WL[255:0] ports of the second and third memory arrays. [255:0] Port; The read / write control decoder converts the internal address signal into bit line read / write control signals according to ADDR_T[6], ADDR_T[2:0], RDB_WR_T and CLK_IN each time a clock signal arrives, including: the first bit line write control signal WR_S0N[7:0], the second bit line write control signal WR_S1N[7:0], the first bit line read control signal RD_S0N[7:0], and the second bit line read control signal RD_S1N[7:0]; Each address code corresponds to a bit line read / write control active state.

[0029] Preferably, the read / write controller consists of 72 read / write units;

[0030] The internal input data signal DI_T port of the i-th read / write unit is connected to the port controller DI_T[i], the internal output data signal DO_T port is connected to the port controller DO_T[i], the input clock CLK_IN port is connected to the clock controller CLK_IN, the EN port is connected to the external enable signal EN, the first line write control port WR_S0N[7:0] is connected to the first line write control signal WR_S0N[7:0] of the address decoder, the second line write control port WR_S1N[7:0] is connected to the second line write control signal WR_S1N[7:0] of the address decoder, the first line read control port RD_S0N[7:0] is connected to the first line read control signal RD_S0N[7:0] of the address decoder, and the second line read control port RD_S1N[7:0] is connected to the second line read control signal RD_S1N[7:0] of the address decoder;

[0031] The internal byte width write enable signal BWE_T[j] of the port controller connects to the byte width write enable port BWE_T of the j×8 to j×8+7 read / write units, 0≤j≤7, 0≤i≤71;

[0032] When 0≤i≤35, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL1[(i+1)×8-1:i×8] of the first memory array; when 36≤i≤71, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL3[(i+1)×8-1:i×8] of the third memory array;

[0033] When 0≤i≤35, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN1[(i+1)×8-1:i×8] of the first memory array; when 36≤i≤71, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN3[(i+1)×8-1:i×8] of the third memory array.

[0034] Preferably, the first, second, and third storage arrays have the same structure, each containing 256 word lines WL[255:0], 288 bit alignment lines, and 73,728 storage cells. The 288 bit alignment lines include positive bit lines BL[287:0] and negative bit lines BLN[287:0]. Each word line connects to 288 storage cells, and each bit alignment line connects to 256 storage cells. The 73,728 storage cells are arranged in a 256×288 matrix, and each storage cell can store one binary bit.

[0035] Preferably, the memory array with clock feedback includes the entire structure of the first memory array, and additionally includes a clock feedback row. The clock feedback row is used to receive the clock feedback signal from the clock controller, perform delay processing on it, and obtain the delayed clock signal to be fed back to the clock controller.

[0036] Preferably, the memory cell includes NMOS transistors N214 and N217, and inverters INV215 and INV216; the bit line port WL is connected to the gates of NMOS transistors N214 and N217, and the drain of N214 is connected to the positive bit line BL and the negative bit line BLN; the source of NMOS transistor N214 is connected to the input terminal of inverter INV215 and the output terminal of inverter INV216; the source of NMOS transistor N217 is connected to the input terminal of inverter INV216 and the output terminal of inverter INV215.

[0037] Preferably, the clock feedback line includes 6 clock feedback units and 250 fill units;

[0038] The word line port WL of the 6 clock feedback units is connected to the clock feedback signal CLK_FEEDBACKOUT, and the bit line port BL is connected to the delayed clock signal CLK_FEEDBACKIN.

[0039] The output of the 250 fill cells is connected to the delayed clock signal CLK_FEEDBACKIN.

[0040] Preferably, the clock feedback unit includes NMOS transistors N220 and N221, and inverters INV218 and INV219; WL is connected to the gate of N220, the drain of N220 is connected to the output of inverter INV218, and the source is connected to BL; the drain of NMOS transistor N221 is connected to the output of inverter INV219, and the inputs of INV218 and INV219 are connected to a high level.

[0041] Preferably, the filling unit is composed of NMOS transistors N224 and N225, inverters INV222 and INV223. The drain of NMOS transistor N224 is connected to the output terminal of inverter INV222, the drain of NMOS transistor N225 is connected to the output terminal of inverter INV223, and the input terminals of INV222 and INV223 are connected to a high level.

[0042] The principle of the above scheme is as follows: The timing controller receives the clock signal and generates a clock feedback signal. The clock feedback signal returns to the clock controller via the memory array with a clock feedback path, determining the maximum operating delay of the memory array. The clock controller generates internal timing signals based on the maximum operating delay to drive the port controller, read / write controller, and address decoder. The port controller receives address, byte width write enable, read / write control, and input data signals from two external ports. Based on the clock signal, it converts the external signals into internal signals that can drive memory read / write operations and transmits them. Simultaneously, based on the clock signal, it converts the internal output data signals into output data signals and outputs them. The address decoder receives the internal address signal and converts it into word line enable and read / write control signals based on the clock signal and transmits them. The read / write controller uses the clock signal and read / write control signals to write the internal input data signals into the memory array or read data from the memory array and transmit it. All circuit modules are interconnected and cooperate to complete the normal read / write function of the memory under a high-frequency clock.

[0043] The advantages of this invention compared to the prior art are:

[0044] (1) This invention realizes an on-chip large-capacity dual-port synchronous memory under the new process node, realizing a 72-bit read / write width and 4096 read / write depths, realizing on-chip large-capacity data storage, and providing the conditions for massive data throughput and high-speed data processing applications.

[0045] (2) This invention realizes that under the condition of a single clock input port, the maximum operating frequency of the storage array is automatically measured internally, and the control timing of the two ports is automatically generated, realizing dual-port synchronous read and write, and has the characteristics of high-speed operation and flexible read and write. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the overall structure of the on-chip large-capacity dual-port synchronous memory of the present invention;

[0047] Figure 2 This is a circuit diagram of the port controller of the present invention;

[0048] Figure 3 This is a circuit diagram of the clock controller of the present invention;

[0049] Figure 4 This is a circuit diagram of the word line decoder in the address decoder of the present invention;

[0050] Figure 5 This is a circuit diagram of the read / write control decoder in the address decoder of the present invention;

[0051] Figure 6 This is a schematic diagram of the read / write controller of the present invention;

[0052] Figure 7 This is a circuit diagram of the read / write unit in the read / write controller of the present invention;

[0053] Figure 8 This is a schematic diagram of the storage array structure of the present invention;

[0054] Figure 9 This is a schematic diagram of the memory array with clock feedback path according to the present invention;

[0055] Figure 10 This is a circuit diagram of the storage unit of the present invention;

[0056] Figure 11 This is a circuit diagram of the clock feedback unit of the present invention;

[0057] Figure 12 This is a circuit diagram of the filling unit of the present invention;

[0058] Figure 13 This is a waveform diagram of the working state of the present invention. Detailed Implementation

[0059] The features and advantages of the present invention will become clearer and more apparent from the following detailed description.

[0060] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0061] like Figure 1 As shown, this invention proposes an on-chip high-capacity dual-port synchronous memory, which consists of a port controller 1, a clock controller 2, an address decoder 3, a read / write controller 4, a memory array 5 with a clock feedback path, a first memory array 6, a second memory array 7, and a third memory array 8.

[0062] Port controller 1 is used to receive the address, byte width write enable, read / write control, and input data signals of two external ports, and convert them into internal address, internal byte width write enable, internal read / write control, and internal input data signals according to the clock signal issued by the clock controller. At the same time, it converts the internal output data signal output by the read / write controller into an external data output signal and outputs it.

[0063] Clock controller 2 is used to receive external clock and enable signal, generate clock feedback signal, and return to clock controller via clock feedback path. Based on the returned clock feedback signal, it generates internal clock signal to drive the operation of other memory modules.

[0064] Address decoder 3 is used to convert internal address, internal read / write control, and internal clock signals into word line drive signals and read / write control signals. The word line drive signals are transmitted to the memory array to control word line opening, and the read / write control signals are transmitted to the read / write controller to control the read / write unit to perform write or read operations.

[0065] The read / write controller is used to receive internal read / write control signals, internal clock signals, internal input data signals, and internal byte width write enable signals. Based on the signal status, it writes the internal input data signals into the storage array or reads the data from the storage array and converts it into internal output data signals.

[0066] The four memory arrays store data from the bit lines into memory cells or output data from memory cells to the bit lines based on the word line open status and bit line data transmission status. Additionally, the memory array with a clock feedback path can receive clock feedback signals and output them to the clock controller via its internal clock feedback path.

[0067] This memory can write data from ports DI_A[71:0] and DI_B[71:0] to the corresponding memory cells of ADDR_A[11:0] and ADDR_B[11:0], or read data from the corresponding memory cells of ADDR_A[11:0] and ADDR_B[11:0] to ports DO_A[71:0] and DO_B[71:0], depending on the states of CLK, EN, RDB_WR_A, and RDB_WR_B. Read and write operations are allowed when EN is 1, and no operation is allowed when EN is 0. Write and read operations must be performed on the rising edge of CLK. RDB_WR_A and RDB_WR_B are the read / write operation mode selection signals for ports A and B; a value of 1 indicates a write operation, and a value of 0 indicates a read operation. BWE_A[7:0] and BWE_B[7:0] are byte-width write enable, used to determine whether the corresponding byte is written during a write operation on port A or port B. The control relationship is as follows: at the start of a write operation, if BWE_X[0] is 1, then DI_X[7:0] and DI_X

[64] are written to memory; if BWE_X[1] is 1, then DI_X[15:8] and DI_X

[65] are written to memory; if BWE_X[2] is 1, then DI_X[23:16] and DI_X

[66] are written to memory; if BWE_X[1] is 1, then DI_X[23:16] and DI_X

[66] are written to memory; if BWE_X[1] is 1, then DI_X[23:16] and DI_X

[66] are written to memory. If [3] is 1, then DI_X[31:24] and DI_X

[67] are written to memory; if BWE_X[4] is 1, then DI_X[39:32] and DI_X

[68] are written to memory; if BWE_X[5] is 1, then DI_X[47:40] and DI_X

[69] are written to memory; if BWE_X[6] is 1, then DI_X[55:48] and DI_X

[70] are written to memory; if BWE_X[7] is 1, then DI_X[63:56] and DI_X

[71] are written to memory.

[0068] like Figure 2As shown, the input ports of the port controller include EN, ADDR_A[11:0], ADDR_B[11:0], BWE_A[7:0], BWE_B[7:0], RDB_WR_A, RDB_WR_B, DI_A[71:0], DI_B[71:0], DO_T[71:0], CLK_IN_A, CLK_IN_B, and TRANSFER, where EN, ADDR_A[11:0], ADDR_B[11:0], BWE_A[7:0], BWE_B[7:0], RDB_WR_A, RDB_WR_B, DI_A[71:0], and DO_T[71:0] are the input ports of the port controller. I_B[71:0] is the port for connecting external signals, and DO_T[71:0], CLK_IN_A, CLK_IN_B, and TRANSFER are the ports for connecting internal signals. The output ports include DO_A[71:0], DO_B[71:0], DI_T[71:0], BWE_T[7:0], ADDR_T[11:0], and RDB_WR_T, where DO_A[71:0] and DO_B[71:0] are the ports for connecting external signals, and DI_T[71:0], BWE_T[7:0], ADDR_T[11:0], and RDB_WR_T are the ports for connecting internal signals.

[0069] The port controller includes latches LAT9, LAT10, LAT13, LAT14, LAT16, LAT17, LAT19, LAT20, and LAT22; and two-input multiplexers MUX12, MUX15, MUX18, and MUX21. The connection relationships are as follows:

[0070] DO_T[71:0] connects to the D terminal of latches LAT9 and LAT10, EN connects to the CD terminal of latches LAT9 and LAT10, CLK_IN_A connects to the CP terminal of latches LAT9, CLK_IN_B connects to the CP terminal of latches LAT10, the Q terminal of latches LAT9 is connected to DO_A[71:0], and the Q terminal of latches LAT10 is connected to DO_B[71:0].

[0071] DI_A[71:0] connects to the D terminal of latch LAT11, CLK_IN_A connects to the CP terminal of latch LAT11, EN connects to the CD terminals of latches LAT11 and LAT13, the Q terminal of latch LAT11 connects to the A1 terminal of two-input multiplexer MUX12, DI_B[71:0] connects to the A0 terminal of two-input multiplexer MUX12, TRANSFER connects to the S terminal of two-input multiplexer MUX12, the Z terminal of two-input multiplexer MUX12 connects to the D terminal of latch MUX13, CLK_IN_B connects to the CP terminal of latch MUX13, and the Q terminal of latch LAT13 connects to DI_T[71:0].

[0072] ADDR_A[11:0] connects to the D terminal of latch LAT14, CLK_IN_A connects to the CP terminal of latch LAT14, EN connects to the CD terminals of latches LAT14 and LAT16, the Q terminal of latch LAT14 connects to the A1 terminal of two-input multiplexer MUX15, ADDR_B[11:0] connects to the A0 terminal of two-input multiplexer MUX15, TRANSFER connects to the S terminal of two-input multiplexer MUX15, the Z terminal of two-input multiplexer MUX15 connects to the D terminal of latch LAT16, CLK_IN_B connects to the CP terminal of latch LAT16, and the Q terminal of latch LAT16 connects to ADDR_T[11:0].

[0073] BWE_A[7:0] connects to the D terminal of latch LAT17, CLK_IN_A connects to the CP terminal of latch LAT17, EN connects to the CD terminals of latches LAT17 and LAT19, the Q terminal of latch LAT17 connects to the A1 terminal of two-input multiplexer MUX18, BWE_B[7:0] connects to the A0 terminal of two-input multiplexer MUX18, TRANSFER connects to the S terminal of two-input multiplexer MUX18, the Z terminal of two-input multiplexer MUX18 connects to the D terminal of latch LAT19, CLK_IN_B connects to the CP terminal of latch LAT19, and the Q terminal of latch LAT19 connects to BWE_T[7:0].

[0074] RDB_WR_A is connected to the D terminal of latch LAT20, CLK_IN_A is connected to the CP terminal of latch LAT20, EN is connected to the CD terminals of latches LAT20 and LAT22, the Q terminal of latch LAT20 is connected to the A1 terminal of two-input multiplexer MUX21, RDB_WR_B is connected to the A0 terminal of two-input multiplexer MUX21, TRANSFER is connected to the S terminal of two-input multiplexer MUX21, the Z terminal of two-input multiplexer MUX21 is connected to the D terminal of latch LAT22, CLK_IN_B is connected to the CP terminal of latch LAT22, and the Q terminal of latch LAT22 is connected to RDB_WR_T.

[0075] like Figure 3 As shown, the clock controller includes latches LAT23, LAT26, LAT30, and LAT31; register DFF36; delays DLY24, DLY25, and DLY27; an XOR gate XOR28; a PMOS transistor P29; an XNOR gate XNOR32; inverters INV33 and INV35; and a buffer BUF34. The connections are as follows:

[0076] EN connects to the drain (D) terminals of latches LAT23, LAT26, LAT30, and LAT31; CLK connects to the CP terminal of latch LAT23 and the input terminal of delayer DLY24; the output terminal of delayer DLY24 connects to the CD terminal of latch LAT23; the Q terminal of latch LAT23 connects to the CP terminal of latch LAT31 and one input terminal of XOR gate XOR28; the QN terminal of latch LAT23 connects to the input terminal of delayer DLY25; the output terminal of delayer DLY25 connects to the CP terminal of latch LAT26 and the input terminal of delayer DLY27; the output terminal of delayer DLY27 connects to the CD terminal of latch LAT26; the Q terminal of latch LAT26 connects to the other input terminal of XOR gate XOR28, the gate of PMOS transistor P29, and the CP terminal of latch LAT30; the output of XOR gate XOR28... The terminal is connected to CLK_FEEDBACKOUT; CLK_FEEDBACKIN is connected to the drain of PMOS transistor P29 and the CD terminals of latches LAT30 and LAT31. The Q terminal of latch LAT30 is connected to one end of the XNOR gate XNOR32 and CLK_IN_B, and the Q terminal of latch LAT31 is connected to the other end of the XNOR gate XNOR32 and CLK_IN_A. The output terminal of the XNOR gate XNOR32 is connected to the input terminal of buffer BUF34 and CLK_IN. The output terminal of inverter INV33 is connected to the CD terminals of register DFF36. The output terminal of buffer BUF34 is connected to the CP terminal of register DFF36. The Q terminal of register DFF36 is connected to TRANSFER. The QN terminal is connected to the input terminal of inverter INV35. The output terminal of inverter INV35 is connected to the D terminal of register DFF36.

[0077] The address decoder consists of a word line decoder and a read / write control decoder. The word line decoder is as follows: Figure 4 As shown, the read / write control decoder is as follows: Figure 5 As shown.

[0078] The word line decoder converts the address signals into word line enable signals based on ADDR_T[11:3] and CLK_IN at each clock cycle. Each address code corresponds to a word line enable state. The word line decoder consists of 8 inverters, 4 two-input NAND gates, 8 three-input NAND gates, 16 three-input AND gates, 32 two-input NOR gates, and 536 two-input AND gates. The logical relationship of the word line decoder circuit is as follows:

[0079] WL0[255:0]=CLK_IN&ADDR_T[6]&Σ(±ADDR_T[3]&±ADDR_T[4]&±ADDR_T[5]&±ADDR_T[7]&±ADDR_T[8]&±ADDR_T[9]&±ADDR_T

[10] &±ADDR_T

[11] )

[0080] WL1[255:0]=CLK_IN&~ADDR_T[6]&Σ(±ADDR_T[3]&±ADDR_T[4]&±ADDR_T[5]&±ADDR_T[7]&±ADDR_T[8]&±ADDR_T[9]&±ADDR_T

[10] &±ADDR_T

[11] )

[0081] The read / write control decoders ADDR_T[6], ADDR_T[2:0], RDB_WR_T, and CLK_IN convert the address signals into bit-line read / write control signals each time a clock signal arrives. Each address code corresponds to a bit-line read / write control active state. The read / write control decoders consist of 5 inverters, 12 three-input AND gates, and 32 two-input NAND gates. The logical relationship of the read / write control decoders is as follows:

[0082] WR_S0N[7:0]=RDB_WR_T&CLK_IN&ADDR_T[6]&Σ(±ADDR_T[0]&±ADDR_T[1]&±ADDR_T[2])

[0083] RD_S0N[7:0]=~RDB_WR_T&CLK_IN&ADDR_T[6]&Σ(±ADDR_T[0]&±ADDR_T[1]&±ADDR_T[2])

[0084] WR_S1 N[7:0]=RDB_WR_T&CLK_IN&~ADDR_T[6]&Σ(±ADDR_T[0]&±ADDR_T[1]&±ADDR_T[2])

[0085] RD_S1 N[7:0]=~RDB_WR_T&CLK_IN&~ADDR_T[6]&Σ(±ADDR_T[0]&±ADDR_T[1]&±ADDR_T[2])

[0086] Read / write controllers such as Figure 6 As shown, it consists of 72 read / write units. The connection relationships are as follows:

[0087] The internal input data signal DI_T port of the i-th read / write unit is connected to the port controller DI_T[i], the internal output data signal DO_T port is connected to the port controller DO_T[i], the input clock CLK_IN port is connected to the clock controller CLK_IN, the EN port is connected to the external enable signal EN, the first line write control port WR_S0N[7:0] is connected to the first line write control signal WR_S0N[7:0] of the address decoder, the second line write control port WR_S1N[7:0] is connected to the second line write control signal WR_S1N[7:0] of the address decoder, the first line read control port RD_S0N[7:0] is connected to the first line read control signal RD_S0N[7:0] of the address decoder, and the second line read control port RD_S1N[7:0] is connected to the second line read control signal RD_S1N[7:0] of the address decoder;

[0088] The internal byte width write enable signal BWE_T[j] of the port controller connects to the byte width write enable port BWE_T of the j×8 to j×8+8th read / write unit, 0≤j≤7, 0≤i≤71;

[0089] When 0≤i≤35, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL1[(i+1)×8-1:i×8] of the first memory array; when 36≤i≤71, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL3[(i+1)×8-1:i×8] of the third memory array;

[0090] When 0 ≤ i ≤ 35, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN1[(i+1)×8-1:i×8] of the first memory array; when 36 ≤ i ≤ 71, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN3[(i+1)×8-1:i×8] of the third memory array.

[0091] Each read / write unit in the read / write controller, such as Figure 7 As shown, it consists of 3 latches, 2 inverters, 1 buffer, 18 two-input NOR gates, 36 NMOS transistors, and 118 PMOS transistors. The connection relationship is as follows:

[0092] BWE_T connects to the D terminal of latch LAT37; CLK_IN connects to the CP terminals of latches LAT37, LAT38, and LAT213; one input terminal of two-input NOR gates NOR39 and NOR40; the gates of PMOS transistors P90-P136, P201-P203; and the gate of NMOS transistor N208; EN connects to the CD terminals of latches LAT37, LAT38, and LAT213; and DI_T connects to the latch... The D terminal of LAT38 and the Q terminal of latch LAT37 are connected to one input terminal of the two-input inverters INV42, INV45, INV48, INV51, INV54, INV57, INV60, INV63, INV66, INV69, INV72, INV75, INV78, INV81, INV84, and INV87. The other input terminal is connected to WR_S0N[7:0] and WR_S1 in sequence. N[7:0], the output terminal is connected in sequence to the gates of NMOS transistors N43, N44, N46, N47, N49, N50, N52, N53, N55, N56, N58, N59, N61, N62, N64, N65, N67, N68, N70, N71, N73, N74, N76, N77, N79, N80, N82, N83, N85, N86, N88, N89; latch LAT The Q terminal of inverter 38 is connected to the input of inverter INV41 and the other input of two-input NOR39. The output of inverter INV41 is connected to the other input of two-input NOR40. The output of two-input NOR39 is connected to NMOS transistors N43, N46, N49, N52, N55, N58, N61, N64, N67, N70, N73, N76, N79, N82, N85, and N86. The sources of the NMOS transistors N44, N47, N50, N53, N56, N59, N62, N65, N68, N71, N74, N77, N80, N83, N86, and N89 are connected to the sources of the NMOS transistors N44, N47, N50, N53, N56, N59, N62, N65, N68, N71, N74, N77, N80, N83, N86, and N89, and their drains ... respectively. The following connections should be made: The drains of PMOS transistors P90 to P136 should be connected to BL0[7:0], BLN0[7:0], BL1[7:0], and BLN1[7:0] in sequence; the gates of PMOS transistors P137 to P200 should be connected to BL0[7:0] and BLN0[7:0] in sequence; and the drains of PMOS transistors P137 to P200 should be connected to BL1[7:0] and BLN1[7:0] in sequence.The gates of PMOS transistors P169 to P200 are connected sequentially to RD_S0N[7:0] and RD_S1N[7:0], and their sources are connected sequentially to BL0[7:0], BLN0[7:0], BL1[7:0], and BLN1[7:0]. The drains of PMOS transistors P169, P171, P173, P175, P177, and P179 are connected to BL. The drains of PMOS transistors P170, P172, P174, P176, P178, and P200 are connected to BLN. The drain of PMOS transistor P201 is connected to BL, the drain of P203 is connected to BLN, the drain of P203 is connected to BL, and the source of P203 is connected to BLN. The sources of PMOS transistors P201 and P203 are connected to high voltage. The PMOS transistors P204 and P205 have their sources connected to a high level, their drains connected to BL and BLN respectively, and their gates connected to BLN and BL respectively. The NMOS transistors N206 and N207 have their sources connected to BL and BLN respectively, their gates connected to BLN and BL respectively, and their drains connected to the source of NMOS transistor N208. The drain of NMOS transistor N208 is connected to a low level. The input of inverter INV210 is connected to BLN, and its output is connected to the gate of NMOS transistor N212. The sources of PMOS transistors P211 and NMOS transistor N212 are connected to the drain (D) terminal of latch LAT213, and their Q terminal is connected to DO_T.

[0093] The circuit structures of the first, second, and third memory arrays are completely identical, as shown in the diagram. Figure 8 As shown, it contains 256 word lines (WL[255:0]), 288 bit lines (BL[287:0], BLN[287:0]), and 73,728 storage units. Each word line connects to 288 storage units, and each bit line connects to 256 storage units. The 73,728 storage units are arranged in a 256×288 matrix, and each storage unit can store one binary bit.

[0094] Memory arrays with clock feedback, such as Figure 9 As shown, in addition to including all cells, connections, and ports of the memory array, there is an additional clock feedback row consisting of 6 clock feedback units and 250 padding units. The WL terminal of the 6 clock feedback units is connected to WL_CLK, and the BL terminal is connected to BL_CLK; the BL terminal of the 250 padding units is connected to BL_CLK.

[0095] Storage units such as Figure 10As shown, it consists of NMOS transistors N214 and N217, and inverters INV215 and INV216. WL is connected to the gates of NMOS transistors N214 and N217, and their drains are BL and BLN, respectively. The source of NMOS transistor N214 is connected to the input of inverter INV215 and the output of inverter INV216; the source of NMOS transistor N217 is connected to the input of inverter INV216 and the output of inverter INV215.

[0096] Clock feedback unit such as Figure 11 As shown, it consists of NMOS transistors N220 and N221, and inverters INV218 and INV219. WL is connected to the gate of NMOS transistor N220, the drain is connected to the output of inverter INV218, and the source is connected to BL; the drain of NMOS transistor N221 is connected to the output of inverter INV219.

[0097] Filling cells such as Figure 12 As shown, it consists of NMOS transistors N224 and N225, and inverters INV222 and INV223. The drain of NMOS transistor N224 is connected to the output terminal of inverter INV222, and the drain of NMOS transistor N225 is connected to the output terminal of inverter INV223.

[0098] The operating waveform of the on-chip large-capacity dual-port synchronous memory is as follows: Figure 13 As shown, at the first rising edge of the clock, RDB_WR_A is 1 and RDB_WR_B is 0. Therefore, port A performs a write operation, writing D0 to address A0, and port B performs a read operation. Since the memory is initially in an all-zero state, DO_B remains all zeros. At the second rising edge of the clock, both RDB_WR_A and RDB_WR_B are 0. Therefore, both ports A and B perform read operations, reading D0 from address A0. At the third rising edge of the clock, RDB_WR_A is 0 and RDB_WR_B is 1. Therefore, port B performs a write operation, writing D1 to address A1, and port A performs a read operation. Since the memory is initially in an all-zero state, DO_A remains all zeros. At the fourth rising edge of the clock, both RDB_WR_A and RDB_WR_B are 0. Therefore, both ports A and B perform read operations, reading D1 from address A1.

[0099] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

[0100] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. An on-chip high-capacity dual-port synchronous memory, characterized in that: It includes a port controller, a clock controller, an address decoder, a read / write controller, a memory array with a clock feedback path, a first memory array, a second memory array, and a third memory array; Port Controller: Receives address signals, byte-width write enable signals, read / write control signals, and input data signals from two external ports. Based on the internal clock signal from the clock controller, it converts these signals into internal address signals, internal byte-width write enable signals, internal read / write control signals, and internal input data signals. It then sends the internal address signals and internal read / write control signals to the address decoder, and the internal read / write control signals, internal input data signals, and internal byte-width write enable signals to the read / write controller. Simultaneously, it converts the internal output data signals from the read / write controller into external data output signals and outputs them. Clock controller: Used to receive external clock and enable signal, generate clock feedback signal and output to the memory array with clock feedback path; Based on the delayed clock signal fed back from the memory array with clock feedback path, an internal clock signal is generated to drive the operation of other memory modules; Address decoder: Converts internal address signals and read / write control signals into word line drive signals and read / write control signals according to internal clock signals. The word line drive signals are transmitted to four memory arrays to control word lines to open, and the read / write control signals are transmitted to the read / write controller to control the read / write units to perform write or read operations. Read / write controller: Receives internal read / write control signals, internal clock signals, internal input data signals, and internal byte width write enable signals. Based on the signal status, it writes the internal input data signals into the storage array, or reads the data from the storage array and converts it into internal output data signals to send to the port controller. First storage array, second storage array, and third storage array: Based on the word line open status and bit line data transmission status, they store the data on the bit lines into the storage cells, or output the data in the storage cells to the bit lines; Memory array with clock feedback path: Based on the word line open status and bit line data transmission status, it stores the data on the bit line into the memory cell, or outputs the data in the memory cell to the bit line; It receives clock feedback signals and sends delayed clock signals back to the clock controller.

2. The on-chip high-capacity dual-port synchronous memory according to claim 1, characterized in that: Based on the states of the external clock signal CLK, the external enable signal EN, the A port read / write control signal RDB_WR_A, and the B port read / write control signal RDB_WR_B, the memory writes the A port input data signal DI_A[71:0] into the memory cell corresponding to the A port address ADDR_A[11:0], and writes the B port input data signal DI_B[71:0] into the memory cell corresponding to the B port address ADDR_B[11:0]; or reads the data from the memory cell corresponding to the A port address ADDR_A[11:0] and outputs it through the A port external data output signal DO_A[71:0], and reads the data from the memory cell corresponding to the B port address ADDR_B[11:0] and outputs it through the B port external data output signal DO_B[71:0]. Read and write operations are performed when EN is 1, and no operations are performed when EN is 0; write or read operations must be performed on the rising edge of CLK. When RDB_WR_X is 1, it is a write operation; when it is 0, it is a read operation. BWE_X[7:0] are the byte width write enable signals of port X, which are used to determine whether the corresponding byte is written when port X is in a write operation. X is either A or B. The control relationship is as follows: at the start of the write operation, if BWE_X[0] is 1, then DI_X[7:0] and DI_X[64] are written to memory; if BWE_X[1] is 1, then DI_X[15:8] and DI_X[65] are written to memory; if BWE_X[2] is 1, then DI_X[23:16] and DI_X[66] are written to memory; if BWE_X[3] is 1, then DI_X[31:24] and DI_X[67] are written to memory. Write to memory; if BWE_X[4] is 1, then DI_X[39:32] and DI_X[68] are written to memory; if BWE_X[5] is 1, then DI_X[47:40] and DI_X[69] are written to memory; if BWE_X[6] is 1, then DI_X[55:48] and DI_X[70] are written to memory; if BWE_X[7] is 1, then DI_X[63:56] and DI_X[71] are written to memory.

3. The on-chip high-capacity dual-port synchronous memory according to claim 2, characterized in that: The port controller input signals include the external enable signal EN, port A address ADDR_A[11:0], port B address ADDR_B[11:0], port A byte width write enable signal BWE_A[7:0], port B byte width write enable signal BWE_B[7:0], port A read / write control signal RDB_WR_A, port B read / write control signal RDB_WR_B, port A input data signal DI_A[71:0], port B input data signal DI_B[71:0], internal output data signal DO_T[71:0], and port A... The internal clock signal CLK_IN_A of port B, the internal clock signal CLK_IN_B of port B, and the switching signal TRANSFER of port A / B are used to connect external signals. EN, ADDR_A[11:0], ADDR_B[11:0], BWE_A[7:0], BWE_B[7:0], RDB_WR_A, RDB_WR_B, DI_A[71:0], and DI_B[71:0] are used to connect external signals, while DO_T[71:0], CLK_IN_A, CLK_IN_B, and TRANSFER are used to connect internal signals. The port controller output signals include the external data output signal DO_A[71:0] for port A, the external data output signal DO_B[71:0] for port B, the internal input data signal DI_T[71:0], the internal byte width write enable signal BWE_T[7:0], the internal address signal ADDR_T[11:0], and the internal read / write control signal RDB_WR_T. Among them, DO_A[71:0] and DO_B[71:0] are connected to external signals, and DI_T[71:0], BWE_T[7:0], ADDR_T[11:0], and RDB_WR_T are connected to internal signals.

4. The on-chip high-capacity dual-port synchronous memory according to claim 3, characterized in that: The port controllers include latches LAT9, LAT10, LAT13, LAT14, LAT16, LAT17, LAT19, LAT20, and LAT22; and two-input multiplexers MUX12, MUX15, MUX18, and MUX21. DO_T[71:0] is connected to the D terminal of latches LAT9 and LAT10 at the same time, EN is connected to the CD terminal of latches LAT9 and LAT10 at the same time, CLK_IN_A is connected to the CP terminal of latches LAT9, CLK_IN_B is connected to the CP terminal of latches LAT10, the Q terminal of latches LAT9 is connected to DO_A[71:0], and the Q terminal of latches LAT10 is connected to DO_B[71:0]. DI_A[71:0] connects to the D terminal of LAT11, CLK_IN_A connects to the CP terminal of latch LAT11, EN connects to the CD terminals of latches LAT11 and LAT13, the Q terminal of latch LAT11 connects to the A1 terminal of two-input multiplexer MUX12, DI_B[71:0] connects to the A0 terminal of two-input multiplexer MUX12, TRANSFER connects to the S terminal of two-input multiplexer MUX12, the Z terminal of two-input multiplexer MUX12 connects to the D terminal of latch LAT13, CLK_IN_B connects to the CP terminal of latch LAT13, and the Q terminal of latch LAT13 connects to DI_T[71:0]. ADDR_A[11:0] connects to the D terminal of latch LAT14, CLK_IN_A connects to the CP terminal of latch LAT14, EN connects to the CD terminals of latches LAT14 and LAT16, the Q terminal of latch LAT14 connects to the A1 terminal of two-input multiplexer MUX15, ADDR_B[11:0] connects to the A0 terminal of two-input multiplexer MUX15, TRANSFER connects to the S terminal of two-input multiplexer MUX15, the Z terminal of two-input multiplexer MUX15 connects to the D terminal of latch LAT16, CLK_IN_B connects to the CP terminal of latch LAT16, and the Q terminal of latch LAT16 connects to ADDR_T[11:0]. BWE_A[7:0] connects to the D terminal of latch LAT17, CLK_IN_A connects to the CP terminal of latch LAT17, EN connects to the CD terminals of latches LAT17 and LAT19, the Q terminal of latch LAT17 connects to the A1 terminal of two-input multiplexer MUX18, BWE_B[7:0] connects to the A0 terminal of two-input multiplexer MUX18, TRANSFER connects to the S terminal of two-input multiplexer MUX18, the Z terminal of two-input multiplexer MUX18 connects to the D terminal of latch LAT19, CLK_IN_B connects to the CP terminal of latch LAT19, and the Q terminal of latch LAT19 connects to BWE_T[7:0]. RDB_WR_A is connected to the D terminal of latch LAT20, CLK_IN_A is connected to the CP terminal of latch LAT20, EN is connected to the CD terminals of latches LAT20 and LAT22, the Q terminal of latch LAT20 is connected to the A1 terminal of two-input multiplexer MUX21, RDB_WR_B is connected to the A0 terminal of two-input multiplexer MUX21, TRANSFER is connected to the S terminal of two-input multiplexer MUX21, the Z terminal of two-input multiplexer MUX21 is connected to the D terminal of latch LAT22, CLK_IN_B is connected to the CP terminal of latch LAT22, and the Q terminal of latch LAT22 is connected to RDB_WR_T.

5. The on-chip high-capacity dual-port synchronous memory according to claim 1, characterized in that: The clock controller includes latches LAT23, LAT26, LAT30, LAT31, register DFF36, delays DLY24, DLY25, DLY27, XOR gate XOR28, PMOS transistor P29, XNOR gate XNOR32, inverters INV33, INV35, and buffer BUF34. EN connects to the drain (D) terminals of latches LAT23, LAT26, LAT30, and LAT31; CLK connects to the CP terminal of latch LAT23 and the input terminal of delayer DLY24; the output terminal of delayer DLY24 connects to the CD terminal of latch LAT23; the Q terminal of latch LAT23 connects to the CP terminal of latch LAT31 and one input terminal of XOR gate XOR28; the QN terminal of latch LAT23 connects to the input terminal of delayer DLY25; the output terminal of delayer DLY25 connects to the CP terminal of latch LAT26 and the input terminal of delayer DLY27; the output terminal of delayer DLY27 connects to the CD terminal of latch LAT26; the Q terminal of latch LAT26 connects to the other input terminal of XOR28, the gate of PMOS transistor P29, and the CP terminal of latch LAT30; the output terminal of XOR28 connects to the clock feedback signal C. LK_FEEDBACKOUT; The delayed clock signal CLK_FEEDBACKIN is connected to the drain of PMOS transistor P29 and the CD terminals of latches LAT30 and LAT31. The Q terminal of latch LAT30 is connected to one end of the XNOR gate XNOR32 and CLK_IN_B, and the Q terminal of latch LAT31 is connected to the other end of the XNOR gate XNOR32 and CLK_IN_A. The output of the XNOR gate XNOR32 is connected to the input of buffer BUF34 and CLK_IN. The output of inverter INV33 is connected to the CD terminals of register DFF36. The output of buffer BUF34 is connected to the CP terminal of register DFF36. The Q terminal of register DFF36 is connected to TRANSFER. The QN terminal is connected to the input of inverter INV35. The output of inverter INV35 is connected to the D terminal of register DFF36.

6. The on-chip high-capacity dual-port synchronous memory according to claim 4, characterized in that: The address decoder consists of a word line decoder and a read / write control decoder; The word line decoder converts the internal address signals into word line enable signals based on ADDR_T[11:3] and CLK_IN at each clock cycle, including: a first word line signal WL0[255:0] and a second word line signal WL1[255:0]. Each address code corresponds to a word line enable state. The first word line signal WL0[255:0] connects the memory array with the clock feedback path to the WL[255:0] port of the first memory array, and the second word line signal WL1[255:0] connects the WL[255:0] ports of the second and third memory arrays. [255:0] Port; The read / write control decoder converts the internal address signal into bit line read / write control signals according to ADDR_T[6], ADDR_T[2:0], RDB_WR_T and CLK_IN each time a clock signal arrives, including: the first bit line write control signal WR_S0N[7:0], the second bit line write control signal WR_S1N[7:0], the first bit line read control signal RD_S0N[7:0], and the second bit line read control signal RD_S1N[7:0]; Each address code corresponds to a bit line read / write control active state.

7. The on-chip high-capacity dual-port synchronous memory according to claim 3, characterized in that: The read / write controller consists of 72 read / write units; The internal input data signal DI_T port of the i-th read / write unit is connected to the port controller DI_T[i], the internal output data signal DO_T port is connected to the port controller DO_T[i], the input clock CLK_IN port is connected to the clock controller CLK_IN, the EN port is connected to the external enable signal EN, the first line write control port WR_S0N[7:0] is connected to the first line write control signal WR_S0N[7:0] of the address decoder, the second line write control port WR_S1N[7:0] is connected to the second line write control signal WR_S1N[7:0] of the address decoder, the first line read control port RD_S0N[7:0] is connected to the first line read control signal RD_S0N[7:0] of the address decoder, and the second line read control port RD_S1N[7:0] is connected to the second line read control signal RD_S1N[7:0] of the address decoder; The internal byte width write enable signal BWE_T[j] of the port controller connects to the byte width write enable port BWE_T of the j×8 to j×8+7 read / write units, 0≤j≤7, 0≤i≤71; When 0≤i≤35, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL1[(i+1)×8-1:i×8] of the first memory array; when 36≤i≤71, the first bit positive drive port BL0[7:0] of the i-th read / write unit is connected to the positive bit line BL2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit positive drive port BL1[7:0] is connected to the positive bit line BL3[(i+1)×8-1:i×8] of the third memory array; When 0≤i≤35, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN0[(i+1)×8-1:i×8] of the memory array with clock feedback path, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN1[(i+1)×8-1:i×8] of the first memory array; when 36≤i≤71, the first bit line negative drive port BLN0[7:0] of the i-th read / write unit is connected to the negative bit line BLN2[(i-35)×8-1:(i-36)×8] of the second memory array, and the second bit line negative drive port BLN1[7:0] is connected to the negative bit line BLN3[(i+1)×8-1:i×8] of the third memory array.

8. The on-chip high-capacity dual-port synchronous memory according to claim 1, characterized in that: The first, second, and third storage arrays have the same structure, each containing 256 word lines WL[255:0], 288 bit alignment lines, and 73,728 storage cells. The 288 bit alignment lines include positive bit lines BL[287:0] and negative bit lines BLN[287:0]. Each word line connects to 288 storage cells, and each bit alignment line connects to 256 storage cells. The 73,728 storage cells are arranged in a 256×288 matrix, and each storage cell can store one binary bit.

9. The on-chip high-capacity dual-port synchronous memory according to claim 8, characterized in that: In addition to the complete structure of the first memory array, the memory array with clock feedback also includes an additional clock feedback row. The clock feedback row is used to receive the clock feedback signal from the clock controller, perform delay processing on it, and obtain the delayed clock signal to feed back to the clock controller.

10. The on-chip high-capacity dual-port synchronous memory according to claim 9, characterized in that: The memory cell includes NMOS transistors N214 and N217, and inverters INV215 and INV216; the bit line port WL is connected to the gates of NMOS transistors N214 and N217, and the drain of N214 is connected to the positive bit line BL and the negative bit line BLN; the source of NMOS transistor N214 is connected to the input of inverter INV215 and the output of inverter INV216; the source of NMOS transistor N217 is connected to the input of inverter INV216 and the output of inverter INV215.

11. The on-chip high-capacity dual-port synchronous memory according to claim 9, characterized in that: The clock feedback line includes 6 clock feedback units and 250 fill units; The word line port WL of the 6 clock feedback units is connected to the clock feedback signal CLK_FEEDBACKOUT, and the bit line port BL is connected to the delayed clock signal CLK_FEEDBACKIN. The output of the 250 fill cells is connected to the delayed clock signal CLK_FEEDBACKIN.

12. The on-chip high-capacity dual-port synchronous memory according to claim 11, characterized in that: The clock feedback unit includes NMOS transistors N220 and N221, and inverters INV218 and INV219; WL is connected to the gate of N220, the drain of N220 is connected to the output of inverter INV218, and the source is connected to BL; the drain of NMOS transistor N221 is connected to the output of inverter INV219, and the inputs of INV218 and INV219 are connected to a high level.

13. The on-chip high-capacity dual-port synchronous memory according to claim 12, characterized in that: The filling unit consists of NMOS transistors N224 and N225, and inverters INV222 and INV223. The drain of NMOS transistor N224 is connected to the output of inverter INV222, and the drain of NMOS transistor N225 is connected to the output of inverter INV223. The inputs of INV222 and INV223 are connected to a high level.

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