A completely floating type memristor analog circuit based on vdtavdca

Abstract

The application discloses a completely floating type memristor simulation circuit based on VDTA-VDCA. C M R1 , M R2 ) constitute. Among them, M R1 and M R2 constitute a variable resistor of the memristor circuit; the VDTA controls the gate voltage of M R1 and M R2 , changes the current flowing through M R1 and M R2 ; the VDCA generates a switching control signal, and realizes the long-time memory function of the memristor circuit. The designed memristor circuit is compatible with the CMOS process, is beneficial to circuit integration, has the characteristics of long-time retention and complete floating, and can realize the switching between the incremental mode and the decremental mode of the memristor without changing the topological structure of the circuit.​

Description

Technical Field

[0001] This invention belongs to the field of novel devices, specifically relating to a fully floating memristor analog circuit based on VDTA-VDCA. Background Technology

[0002] Memristors, used to characterize the relationship between magnetic flux and charge, are widely used in digital logic circuits, neural networks, and in-memory computing, and are considered a core foundational device for future information storage. However, due to the difficulty of fabricating nanoscale devices, memristors have not yet been commercialized. Therefore, memristor analog circuits have attracted researchers' attention. These circuits can simulate the electrical characteristics of memristors, preparing for commercialization. Current memristor analog circuits suffer from drawbacks such as a large number of passive components, poor circuit adjustability, and short resistive state retention time. Therefore, it is necessary to find new memristor analog circuits that better represent the electrical characteristics of memristors, laying the foundation for future commercialization. Summary of the Invention

[0003] The purpose of this invention is to propose a fully floating memristor analog circuit based on VDTA-VDCA to simulate the electrical characteristics of a memristor.

[0004] To achieve this invention, the technical solution adopted is: a fully floating memristor analog circuit based on VDTA-VDCA, the overall circuit consisting of one VDTA, one VDCA, and one capacitor. C Two PMOS transistors ( M R1 , M R2 It consists of ) . Among them, M R1 and M R2 The variable resistor that makes up the circuit, the memristor circuit, has a resistance value equivalent to the input voltage across the memristor circuit and... M R1 and M R2 The ratio between the currents flowing through it; the current output by VDTA flows into the capacitor. C In the middle, capacitor C Voltage control on M R1 and M R2The current flowing through it; VDCA generates a switching control signal to realize the long-term memory function of the memristor circuit. When the P port of the memristor circuit is used as the input port and the N port as the output port, the memristor circuit operates in the resistance increasing state. When the N port of the memristor circuit is used as the input port and the P port as the output port, the memristor circuit operates in the resistance decreasing state. The designed memristor circuit is compatible with CMOS technology, which is conducive to circuit integration. It has the characteristics of long-term retention and complete floating, and the switching between the increasing and decreasing modes of the memristor circuit can be realized without changing the circuit topology.

[0005] The beneficial effects of this invention are as follows: 1. This invention proposes a fully floating memristor analog circuit based on VDTA-VDCA, featuring long-term memory, full floating, and adjustable modes. 2. This invention can switch the incrementing and decrementing modes of the memristor circuit without changing the circuit topology. 3. This invention maintains its characteristic for a long time when powered off. 4. The range of memristor resistance can be changed by adjusting... V B Size, regulating transistor M R1 and M R2 It is achieved by adjusting the aspect ratio. Attached Figure Description

[0006] Figure 1 This is the overall circuit diagram of a fully floating memristor analog circuit based on VDTA-VDCA according to the present invention.

[0007] Figure 2 This is a structural diagram of the VDTA-VDCA circuit module in the circuit of this invention.

[0008] Figure 3 The capacitor in the circuit of this invention C= A comparison of the input voltage and current characteristic curves when the system is supplied with a sinusoidal voltage signal with a peak value of 0.5 V and frequencies of 1 Hz, 2 Hz, 4 Hz and 8 Hz, respectively.

[0009] Figure 4 The capacitor in the circuit of this invention C= A comparison of the input voltage and current characteristic curves when the system is supplied with a sinusoidal voltage signal with a peak value of 0.5 V and frequencies of 1 MHz, 2 MHz, 4 MHz, and 8 MHz, respectively.

[0010] Figure 5 The circuit of this invention is based on the capacitor. C=The graph shows the input voltage, input current, and equivalent conductance when a pulse voltage signal with a pulse width of 0.1 μs, a period of 1 μs, a high level of 0.5 V, and a low level of 0 V is applied, with a voltage of 100 pF, P port as the input port, and N port as the output port.

[0011] Figure 6 The circuit of this invention is based on the capacitor. C= The graph shows the input voltage, input current, and equivalent conductance when a pulse voltage signal with a pulse width of 0.1 μs, a period of 1 μs, a high level of 0.5 V, and a low level of 0 V is applied, with a voltage of 100 pF, N port as the input port, and P port as the output port. Implementation

[0012] A fully floating memristor analog circuit based on VDTA-VDCA, the overall circuit consists of 1 VDTA, 1 VDCA, and 1 capacitor. C 2 PMOS transistors M R1 , M R2 )constitute.

[0013] Working principle: VDTA-VDCA consists of two circuit modules, VDTA and VDCA, specifically including: 2 PMOS transistors M 4 NMOS transistor M 7 and PMOS transistors M 6 NMOS transistor M 8 The current transmitters are constructed separately, and one is composed of an NMOS transistor. M 15 , M 17 , M 19 , M 21 and PMOS transistors M 14 , M 16 , M 18 , M 20 The complementary voltage amplifier consists of one PMOS transistor. M 12 , M 13 The switching circuit consists of one NMOS transistor. M 1 , M2 , M 9 , M 10 , M 11 and PMOS transistors M 3 , M 5 This constructs a differential amplifier. Both the P and N ports of the differential amplifier serve as the input and output ports of the memristor circuit. The transconductance gain of the differential amplifier is determined by the input voltage at port B. V B Control: The switching circuit is turned on or off by the high or low level of the input Z port; the W port is the output port of the switching circuit; and the X port is the output port of the complementary voltage amplifier.

[0014] When a bias voltage is applied to the memristor circuit V DD , V SS and V B When voltage signals are applied to ports P and N, the differential amplifier transmits the amplified voltage signals to the complementary voltage amplifier and the current transmitter, respectively. The amplification factor of the voltage signals is determined by the circuit's bias voltage. V B The voltage signals output by the differential amplifier are determined by... M 18 , M 19 , M 20 M 21 and M 14 , M 15 , M 16 , M 17 The amplifier amplifies the signal again, generating a pair of complementary square wave signals. These square wave signals are then superimposed and output from port X. Port X is connected to port Z of the switching circuit. The voltage signal output from port X controls the switching circuit's on / off state; when port X outputs a low level, the switching circuit is on; when port X outputs a high level, the switching circuit is off. The voltage signal output from the differential amplifier is transmitted to... M 4 , M 6 , M 7 , M 8 The current transmitter, when the switching circuit is turned on, generates current through it.M 12 and M 13 Flow from port W to capacitor C When the switching circuit is closed, the capacitor C The electrical energy on the capacitor cannot be released. C The charge on the capacitor is preserved; C one end and M R1 gate, M R2 Gate connection, capacitor C Voltage control on M R1 and M R2 The current flowing through it. When the switching circuit is turned on, if the P port of the memristor circuit is used as the input port and the N port as the output port, the memristor circuit operates in a state of increasing resistance. If the N port of the memristor circuit is used as the input port and the P port as the output port, the memristor circuit operates in a state of decreasing resistance. The resistance of the memristor circuit is equivalent to the voltage across the memristor circuit and the resistance of the input circuit. M R1 and M R2 The ratio between the currents flowing through it simulates the resistive-variable characteristic of a memristor; when the switching circuit is off, the capacitor... C The voltage is maintained, simulating the memory characteristics of a memristor.

[0015] The designed memristor circuit is compatible with CMOS technology, which facilitates circuit integration. It has long-term retention characteristics and full floating characteristics, and can switch between memristor increment and decrement modes without changing the circuit topology.

[0016] Specific connection method: the P port of the circuit and M 1 Gate connection; M 1 The source pole and M 2 The source connection, and with M 11 The drain connection, M 1 Drain and M 3 Drain, M 3 The gate connection; the N port of the circuit and M 2 gate connection, M 2 Drain and M 5 Drain, M5 Gate connection; M 3 The source pole and M 4 , M 5 , M 6 , M 14 , M 18 The source pole, M 9 The drain connection, M 3 gate and M 4 , M 18 Gate connection; M 5 gate and M 6 , M 14 The gate connection; the B port of the circuit and M 9 Gate connection; M 9 The source pole and M 10 Drain, M 10 , M 11 , M 15 、M 17 , M 19 , M 21 Gate connection; M 10 The source pole and M 7 , M 8 , M 11 , M 15 , M 17 , M 19 , M 21 The source connection; M 7 gate and M 8 gate, M 4 , M 7Drain connection; M 18 Drain and M 19 Drain, M 20 Gate connection; M 6 Drain and M 8 , M 13 Drain connection; M 14 Drain and M 15 Drain, M 16 Gate connection; M 16 , M 20 The source pole is connected to the ground. M 20 Drain and M 16 , M 17 , M 21 The drain is connected and connected to the X port of the circuit; M 13 The source pole and M 12 The source connection, M 13 gate and M 12 The gate is connected and connected to the Z port of the circuit. M 12 The drain of the circuit is connected to the W port of the circuit; the X port of the circuit is connected to the Z port of the circuit; the W port of the circuit is connected to the capacitor. C Connect one end and with M R1 , M R2 Gate connection; capacitor C The other end is connected to the ground; M R1 The source and the N port of the circuit, M R2 Drain connection; M R2 The source and the P port of the circuit, M R1 The drain connection.

Claims

1. A fully floating memristor analog circuit based on VDTA-VDCA, characterized in that: the overall circuit consists of one VDTA circuit module, one VDCA circuit module, and one capacitor. C 2 PMOS transistors M R1 , M R2 constitute; in, M R1 gate and M R2 The gate is connected, and together with the W port and capacitor C One end is connected to the capacitor. C The other end is grounded; M R1 The source pole and M R2 The drain connection forms the first source-drain common node, and the first source-drain common node is connected with... N Port connection; M R1 Drain and M R2 The source-to-drain connection forms a second source-to-drain common node, which is connected to port P. M R1 and M R2 The variable resistor constituting the memristor circuit is composed of a VDTA circuit module and a VDCA circuit module, specifically including two current transmitters, one complementary voltage amplifier, one switching circuit, and one shared differential amplifier. Both the P and N ports of the differential amplifier can serve as input and output ports for the memristor circuit. The transconductance gain of the differential amplifier is determined by the input voltage at port B. V B Control; the switching circuit is turned on or off by the high or low level of the Z input port, and the W port is for the switching circuit and the external capacitor. C The connected ports; port X is the output port of the complementary voltage amplifier; the VDTA circuit module and the VDCA circuit module share one differential amplifier, and the VDTA circuit module controls... M R1 and M R2 The gate voltage changes M R1 and M R2 The current flowing through it generates a control signal for the switching circuit in the VDCA circuit module, enabling the memristor circuit to perform long-term memory functions; when a bias voltage is applied to the memristor circuit... V DD , V SS and V B When a voltage signal is applied between ports P and N, the differential amplifier processes the differential voltage between ports P and N and transmits the corresponding signals to the complementary voltage amplifier and the current transmitter, respectively. The transconductance gain of the differential amplifier is determined by the circuit's bias voltage. V B The corresponding signal is processed by a complementary voltage amplifier, and the resulting control signal is output from port X. Port X is connected to port Z of the switching circuit. When the signal output from port X to port Z is low, the switching circuit is turned on, and the current generated by the current transmitter flows into the capacitor through port W. C ,capacitance C Voltage control on M R1 and M R2 The current flowing through it; when the signal output from port X to port Z is high, the switching circuit is closed, and the capacitor... C The charge on the capacitor is preserved. C The voltage across the circuit remains constant; the resistance of the memristor circuit is equivalent to the input voltage of the memristor circuit and... M R1 and M R2 The ratio between the currents flowing through it; when the P port of the memristor circuit is used as the input port and the N port is used as the output port, the memristor circuit operates in a state of increasing resistance; when the N port of the memristor circuit is used as the input port and the P port is used as the output port, the memristor circuit operates in a state of decreasing resistance.

2. The fully floating memristor analog circuit based on VDTA-VDCA according to claim 1, characterized in that: the VDTA circuit module includes two current transmitters, one switching circuit, and one shared differential amplifier; when a voltage signal is input to the P port and N port of the differential amplifier, the differential amplifier amplifies the voltage signal and transmits it to the current transmitter; when the switching circuit is turned on, the current generated on the current transmitter flows into the capacitor. C In the middle, capacitor C The voltage control of the memristor circuit allows current to flow through the variable resistor, changing the equivalent resistance of the memristor circuit.

3. A fully floating memristor analog circuit based on VDTA-VDCA according to claim 1, characterized in that: the VDCA circuit module includes a complementary voltage amplifier and a shared differential amplifier; when a voltage signal is input to the P port and N port of the differential amplifier, the differential amplifier amplifies the voltage signal and transmits it to the complementary voltage amplifier; the complementary voltage amplifier further amplifies the voltage signal to generate a pair of complementary square wave signals, and outputs the superimposed square wave signals from the X port; the X port is connected to the Z port of the switching circuit, and the voltage signal output from the X port controls the opening or closing of the switching circuit.

4. A fully floating memristor analog circuit based on VDTA-VDCA according to claim 1, characterized in that: the resistance value of the memristor circuit is equivalent to the input voltage across the memristor circuit and... M R1 and M R2 The ratio between the currents flowing through it.

5. The fully floating memristor analog circuit based on VDTA-VDCA according to claim 1 is characterized by: the designed memristor circuit being compatible with CMOS technology, which is beneficial for circuit integration; the resistance value of the memristor circuit being retained for a long time when power is off; and the switching between memristor increment and decrement modes being achieved without changing the circuit topology.

6. The fully floating memristor analog circuit based on VDTA-VDCA according to claim 1, characterized in that: wherein, The differential amplifier consists of MOSFETs M 1 , M 2 , M 3 , M 5 , M 9 , M 10 and M 11 constitute; M 1 The gate is connected to the P port. M 2 The gate is connected to the N port. M 1 and M 2 The source pole is connected and together with M 11 Drain connection; M 1 Drain and M 3 The drain and gate are connected. M 3 The drain and gate are connected to form a common node. M 3 source and bias voltage V DD connect; M 2 Drain and M 5 The drain and gate are connected. M 5 The drain and gate are connected to form a common node. M 5 source and bias voltage V DD connect; M 9 The gate is connected to the bias port B. M 9 source and bias voltage V DD connect, M 9 Drain and M 10 The drain and gate are connected at a common node; M 10 The gate and drain are connected, and this common node is simultaneously connected to... M 11 , M 19 , M 21 , M 15 and M 17 Gate connection; M 10 and M 11 The source of each is biased by the voltage. V SS connect, M 11 Drain and M 1 and M 2 The common source connection; the first current transmitter is a MOSFET. M 4 and M 7 constitute; M 4 source and bias voltage V DD connect, M 4 The gate and differential amplifier M 3 The gate and drain are connected at a common node. M 4 Drain and M 7 The drain and gate are connected at a common node; M 7 The gate and drain are connected, and this common node is simultaneously connected to... M8 gate connection, M 7 source and bias voltage V SS Connection; the second current transmitter is a MOSFET. M 6 and M 8 constitute; M 6 source and bias voltage V DD connect, M 6 The gate and differential amplifier M 5 The gate and drain are connected at a common node. M 6 Drain and M 8 The drain connection of the two is such that their common drain node is simultaneously connected to the switch circuit. M 13 Drain connection; M 8 gate and M 7 The gate and drain are connected at a common node. M 8 source and bias voltage V SS Connection; complementary voltage amplifier consists of MOSFETs M 14 , M 15 , M 16 , M 17 , M 18 , M 19 , M 20 and M 21 constitute; in, M 18 source and bias voltage V DD connect, M 18 gate and M 4 gate and M 3 The gate and drain are connected at a common node. M 18 Drain and M 19 The drain connection between the two, and the common drain node of the two is M 20 Gate connection; M 19 gate and M 9 Drain, M 10 The gate and drain and M 11 The gates are connected to the common node. M 19 source and bias voltage V SS connect; M 20 gate and M 18 and M 19 The common drain node connection, M 20 The source terminal is connected to the ground terminal. M 20 The drain is connected to the X port; M 21 gate and M 9 Drain, M 10 The gate and drain and M 11 The gates are connected to the common node. M 21 source and bias voltage V SS connect, M 21 The drain is connected to the X port; M 14 source and bias voltage V DD connect, M 14 gate and M 6 gate and M 5 The gate and drain are connected at a common node. M 14 Drain and M 15 The drain connection between the two, and the common drain node of the two is M 16 Gate connection; M 15 gate and M 9 Drain, M 10 The gate and drain and M 11 The gates are connected to the common node. M 15 source and bias voltage V SS connect; M 16 gate and M 14 and M 15 The common drain node connection, M 16 The source terminal is connected to the ground terminal. M 16 The drain is connected to the X port; M 17 gate and M 9 Drain, M 10 The gate and drain and M 11 The gates are connected to the common node. M 17 source and bias voltage V SS connect, M 17 The drain is connected to the X port; the switching circuit consists of a MOSFET. M 12 and M 13 constitute, M 12 and M 13 It adopts a back-to-back series structure with the source terminals connected; M 12 and M 13 The gates are connected together and are connected to the Z port; M 12 The drain is connected to the W port. M 12 The source pole and M 13 The source connection, M 13 Drain and M 6 and M 8 The common drain node is connected.

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