Configurable multi-bit memory-compute integrated array, memory-compute integrated chip and electronic device

Abstract

The application provides a configurable multi-bit memory-computing integrated array, a memory-computing integrated chip and an electronic device. When a memory-computing unit is configured as a low-resistance state weight structure, the input of the memory-computing unit is a low-level data signal or a high-level data signal, and the output is a low-resistance state. When the memory-computing unit is configured as a high-resistance state weight structure, the input of the memory-computing unit is a low-level data signal, and the output is a low-resistance state. The input is a high-level data signal, and the output is a high-resistance state, so as to realize the multiplication logic between 0 and 1. In combination with an array control logic and a multi-bit data output unit, multi-bit calculation is realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit technology, and in particular to a configurable multi-bit in-memory computing array, an in-memory computing chip, and an electronic device. Background Technology

[0002] In the post-Moore's Law era, the explosive growth of data-intensive applications has led to the separation of storage and computation in the traditional von Neumann architecture, resulting in data access overhead far exceeding data processing overhead, creating a "memory wall" and power consumption bottlenecks. In recent years, in-memory computing (CIM) has emerged as a promising technology capable of breaking down this "memory wall." CIM refers to combining storage and computation, thereby reducing the power consumption caused by frequent data transfers between processing and in-memory computing units.

[0003] To date, due to the promising future of in-memory computing, almost all types of memory media have been used in CIM research, including Flash, DRAM, SRAM, RRAM, MRAM, PCM, and FeRAM. Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory device with superior read / write speeds and reliability, making it a promising candidate for CIM research. However, current technologies, especially MRAM CIM chips based on cascaded arrays, typically only support binary neural networks, which limits its applicability. Summary of the Invention

[0004] This invention provides a configurable multi-bit in-memory computing array, an in-memory computing chip, and an electronic device, which supplements the multiplication logic between 0 and 1 in the in-memory computing chip to achieve multi-bit computation.

[0005] In a first aspect, the present invention provides a configurable multi-bit in-memory computing array, comprising: multiple in-memory computing units, input signal units, bit lines, and data output units;

[0006] The memory computing unit array is arranged such that the memory computing units in each column are connected in series; the first end of the first memory computing unit in each column is connected to the bit line; the bit line is used to input a reference voltage signal.

[0007] The signal input terminal of the memory-based computing unit in the same row is connected to the signal output terminal of the input signal unit corresponding to the current row; the input signal unit is used to output a low-level data signal or a high-level data signal to the memory-based computing unit in each row;

[0008] The data output unit is connected to the second end of the storage unit at the end of each column; the data output unit is used to perform post-processing operations on the output signal of the storage unit in each column.

[0009] The in-memory computing unit is configured as a low-impedance weighted structure or a high-impedance weighted structure. When the in-memory computing unit is configured as the low-impedance weighted structure, the output of the in-memory computing unit is low-impedance when the signal input terminal of the in-memory computing unit receives the low-level data signal or the high-level data signal. When the in-memory computing unit is configured as the high-impedance weighted structure, the output of the in-memory computing unit is low-impedance when the signal input terminal of the in-memory computing unit receives the low-level data signal, and the output of the in-memory computing unit is high-impedance when the signal input terminal of the in-memory computing unit receives the high-level data signal.

[0010] Optionally, the low-resistivity weighting structure includes a first weighting unit, a second weighting unit, a first switching unit, and a second switching unit; the first weighting unit is configured in a low-resistivity state, and the second weighting unit is configured in a low-resistivity state.

[0011] The first end of the first weighting unit serves as the first end of the memory-computing unit, and the second end of the first weighting unit is connected to the first end of the first switching unit. The second end of the first switching unit serves as the second end of the memory-computing unit. The control end of the first switching unit is connected to the signal output end of the input signal unit. The first switching unit is used to be in a cutoff state according to the low-level data signal and in a conduction state according to the high-level data signal.

[0012] The first end of the second weighting unit is connected to the first end of the first weighting unit, the second end of the second weighting unit is connected to the first end of the second switching unit, and the second end of the second switching unit is connected to the second end of the first switching unit; the control end of the second switching unit is connected to the signal output end of the input signal unit; the second switching unit is used to be in a conducting state according to the low-level data signal and in a cut-off state according to the high-level data signal.

[0013] Optionally, the high-resistivity weighting structure includes a third weighting unit, a fourth weighting unit, a third switching unit, and a fourth switching unit; the third weighting unit is configured in a high-resistivity state, and the fourth weighting unit is configured in a low-resistivity state.

[0014] The first end of the third weighting unit serves as the first end of the storage unit, and the second end of the third weighting unit is connected to the first end of the third switching unit. The second end of the third switching unit serves as the second end of the storage unit. The control end of the third switching unit is connected to the signal output end of the input signal unit. The third switching unit is used to be in a cutoff state according to the low-level data signal and in a conduction state according to the high-level data signal.

[0015] The first end of the fourth weighting unit is connected to the first end of the third weighting unit, the second end of the fourth weighting unit is connected to the first end of the fourth switching unit, and the second end of the fourth switching unit is connected to the second end of the third switching unit; the control end of the fourth switching unit is connected to the signal output end of the input signal unit; the fourth switching unit is used to be in a conducting state according to the low-level data signal and in a cut-off state according to the high-level data signal.

[0016] Optionally, the first and third switching units are NMOS switches; the second and fourth switching units are PMOS switches.

[0017] Optionally, the signal output terminal of the input signal unit corresponding to each row includes a first output terminal and a second output terminal; the first output terminal outputs low-level data, and the second output terminal outputs high-level data to form the low-level data signal; or the first output terminal outputs high-level data, and the second output terminal outputs low-level data to form the high-level data signal.

[0018] The low-resistance weighting structure includes a first weighting unit, a second weighting unit, a first switching unit, and a second switching unit; the first weighting unit is configured in a low-resistance state, and the second weighting unit is configured in a low-resistance state.

[0019] The first end of the first weighting unit is connected as the first end of the in-memory computing unit, the second end of the first weighting unit is connected to the first end of the first switching unit, and the second end of the first switching unit is the second end of the in-memory computing unit; the control end of the first switching unit is connected to the first output end.

[0020] The first end of the second weighting unit is connected to the first end of the first weighting unit, the second end of the second weighting unit is connected to the first end of the second switching unit, and the second end of the second switching unit is connected to the second end of the first switching unit; the control end of the second switching unit is connected to the second output end.

[0021] The first switching unit is configured to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data; the second switching unit is configured to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data.

[0022] Optionally, the high-resistivity weighting structure includes a third weighting unit, a fourth weighting unit, a third switching unit, and a fourth switching unit; the third weighting unit is configured in a high-resistivity state, and the fourth weighting unit is configured in a low-resistivity state.

[0023] The first end of the third weighting unit serves as the first end of the storage unit, the second end of the third weighting unit is connected to the first end of the third switching unit, and the second end of the third switching unit serves as the second end of the storage unit; the control end of the third switching unit is connected to the first output end.

[0024] The first end of the fourth weighting unit is connected to the first end of the third weighting unit, the second end of the fourth weighting unit is connected to the first end of the fourth switching unit, and the second end of the fourth switching unit is connected to the second end of the third switching unit; the control end of the fourth switching unit is connected to the second output end.

[0025] The third switching unit is used to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data; the fourth switching unit is used to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data.

[0026] Optionally, the first switching unit, the second switching unit, the third switching unit, and the fourth switching unit are all NMOS switching transistors.

[0027] Optionally, the first weighting unit, the second weighting unit, the fourth weighting unit, and the third weighting unit are magnetoresistive random access memories.

[0028] Secondly, the present invention provides an in-memory computing chip, including the configurable multi-bit in-memory computing array described in any embodiment of the present invention.

[0029] Thirdly, the present invention provides an electronic device comprising the in-memory computing chip described in any embodiment of the present invention.

[0030] The technical solution provided by this invention uses an array of memory computing units, with multiple memory computing units connected in series in each column. The multiple columns of memory computing units form an integrated memory computing array. Each memory computing unit is configured as a low-impedance weighted structure or a high-impedance weighted structure. Each row of memory computing units is connected to an input signal unit, which sends a low-level data signal or a high-level data signal to each row of memory computing units. When the memory computing unit is configured as a low-impedance weighted structure, the input of the memory computing unit is a low-level data signal (corresponding to 0) or a high-level data signal (corresponding to 1), and the output is a low-impedance state RL (corresponding to 0). When the memory computing unit is configured as a high-impedance weighted structure, the input of the memory computing unit is a low-impedance data signal (corresponding to 0), and the output is a high-impedance state RH (corresponding to 1). The input is a high-impedance data signal (corresponding to 1), and the output is a high-impedance state RH (corresponding to 1), thereby realizing the multiplication logic between 0 and 1 and achieving multi-bit computation. Since the storage units of each column are connected in series, the data output unit can map the output results of each column according to the parameters such as resistance and current at the output end of each column, and perform post-processing calculations on the output results to obtain the final output data. Attached Figure Description

[0031] Figure 1 A schematic diagram of a cross-array CIM chip provided for related technologies;

[0032] Figure 2 This is a structural diagram illustrating the weight combination of related technologies;

[0033] Figure 3 This is a schematic diagram of the structure of a configurable multi-bit in-memory computing array provided in an embodiment of the present invention;

[0034] Figure 4 This provides a schematic diagram of another configurable multi-bit in-memory computing array for embodiments of the present invention;

[0035] Figure 5 This provides a schematic diagram of another configurable multi-bit in-memory computing array for embodiments of the present invention;

[0036] Figure 6 This is a schematic diagram of a low-resistivity weighted structure provided in an embodiment of the present invention;

[0037] Figure 7 This invention provides a schematic diagram of the weight design for yet another low-resistivity weight structure.

[0038] Figure 8 This is a schematic diagram of a high-resistivity weighted structure provided in an embodiment of the present invention;

[0039] Figure 9 This invention provides a schematic diagram of the weight design for yet another high-resistivity weight structure.

[0040] Figure 10 This provides a schematic diagram of another configurable multi-bit in-memory computing array for embodiments of the present invention;

[0041] Figure 11 This invention provides a schematic diagram of the weight design for yet another low-resistivity weight structure.

[0042] Figure 12 This invention provides a schematic diagram of the weight design for yet another high-resistivity weight structure.

[0043] Figure 13 This is a schematic diagram of a nonlinear adjustment output circuit provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Magnetic random access memory (MRAM) typically takes the form of a magnetic tunnel junction (MTJ), consisting of two ferromagnetic layers (a free layer and a reference layer) with a tunneling barrier layer in between. When current is input from the reference layer, electrons with the same spin polarization direction as the reference layer's magnetization direction will pass through the reference layer and enter the tunneling layer. When the free layer and the reference layer have different magnetization directions, these spin-polarized electrons, after tunneling, exert a spin-transfer torque on the free layer, thereby flipping the free layer's magnetization direction to be parallel to the reference layer. By changing the current polarity, i.e., inputting current from the free layer, an antiparallel arrangement of the free layer and the reference layer's magnetization directions can be achieved.

[0046] MRAM possesses superior read / write speed characteristics and reliability, making it a promising candidate for application in CIM research. However, due to the low resistance of magnetic tunnel junctions (MTJs), traditional cross-arrays exhibit considerable power consumption. To address this issue, Figure 1 A schematic diagram of a cross-array CIM chip is provided for related technologies. Figure 2 See the structural diagram of the weight combination of related technologies. Figure 1 and Figure 2The cross array can include multiple row lines IN0, IN1, IN2, ..., INm, multiple column lines, and MRAM cells 110 corresponding to the intersections between the row and column lines. Based on the data stored in the MRAM cells 110, each MRAM cell 110 can have different weights. When the input IN is -1 and the weight is -1, the output is in a high-impedance state RH (corresponding to 1); when the input IN is -1 and the weight is 1, the output is in a low-impedance state RL (corresponding to -1); when the input IN is 1 and the weight is -1, the output is in a low-impedance state RL (corresponding to -1); and when the input IN is 1 and the weight is 1, the output is in a high-impedance state RH (corresponding to 1). The multi-bit input is converted into a binary code input. Since the MRAM cells 110 are connected in series, the equivalent resistance of each column at the output is the sum of the resistances of all cells in that column, thus achieving the multiplication and addition function. The overall array performs vector and matrix multiplication. However, this chip's memory cell design can only handle binary multiplication between -1 and 1, and can only support binary neural networks. Furthermore, since a single MRAM cell 110 can only store two states, corresponding to 1 bit, it cannot achieve multi-bit weighted resistance mapping in the memory-computing array, which greatly limits its applicability.

[0047] In view of this, Figure 3 This is a schematic diagram of a configurable multi-bit in-memory computing array provided in an embodiment of the present invention. See [link / reference]. Figure 3 It includes: multiple memory processing units 310, input signal units 320, bit lines 330 and data output units 340;

[0048] The memory computing units 310 are arranged in an array, with each column of memory computing units 310 connected in series; the first end of the first memory computing unit 310 in each column is connected to the bit line 330; the bit line 330 is used to input a reference voltage signal.

[0049] The signal input terminal of the storage unit 310 in the same row is connected to the signal output terminal of the input signal unit 320 corresponding to the current row; the input signal unit 320 is used to output a low-level data signal or a high-level data signal to each row storage unit 310;

[0050] The data output unit 340 is connected to the second end of the end-of-column storage unit 310; the data output unit 340 is used to perform post-processing operations on the output signal of each column storage unit 310.

[0051] The memory-based computing unit 310 is configured as either a low-impedance weighted structure or a high-impedance weighted structure. When the memory-based computing unit 310 is configured as a low-impedance weighted structure, its output is always in a low-impedance state when its signal input terminal receives a low-level data signal or a high-level data signal. When the memory-based computing unit 310 is configured as a high-impedance weighted structure, its output is in a low-impedance state when its signal input terminal receives a low-level data signal, and in a high-impedance state when its signal input terminal receives a high-level data signal.

[0052] Specifically, the in-memory computing array structure includes multiple row-oriented signal lines IN0, IN1, IN2, ..., INm. The signal output terminals of the input signal unit 320 are connected to the corresponding in-memory computing unit 310 through the signal lines of each row. Each row of n in-memory computing units can serve as an n-bit input weight, where n is an integer greater than or equal to 1. For example, taking four columns, the first column BL0 in each row represents the weight of the most significant bit in the binary value, the fourth column BL3 represents the weight of the least significant bit, and the other columns can be defined with input weights sequentially. Alternatively, the first column BL0 can be the weight of the least significant bit in the binary value, and the fourth column BL3 can be the weight of the most significant bit.

[0053] The input signal unit 320 sends data signals to the memory-processing unit 310 of each row via the signal lines of each row. The data signals include low-level data signals and high-level data signals. Since multi-bit multiplication requires the implementation of multiplication logic between 0 and 1, the low-level data signal can represent "0" and the high-level data signal can represent "1". The signal output terminal of the input signal unit 320 forms a multi-bit input data by sequentially inputting low-level or high-level data signals from low to high or from high to low. Each memory-processing unit 310 is configured as a low-impedance weight structure (corresponding to 0) or a high-impedance weight structure (corresponding to 1) according to the data being processed. The weight structure of each memory-processing unit 310 can be programmed into the memory-processing unit 310 through a programming circuit, thereby realizing the programmability of the array. When the memory-based computing unit 310 is configured with a low-impedance weight structure (corresponding to 0), the input to the memory-based computing unit 310 is either a low-level data signal (corresponding to 0) or a high-level data signal (corresponding to 1), and the output is always a low-impedance RL (corresponding to 0). When the memory-based computing unit 310 is configured with a high-impedance weight structure (corresponding to 1), the input to the memory-based computing unit 310 is a low-impedance data signal (corresponding to 0), and the output is a low-impedance RL (corresponding to 0); the input is a high-impedance data signal (corresponding to 1), and the output is a high-impedance RH (corresponding to 1), thus realizing the multiplication logic between 0 and 1 in each memory-based computing unit. Since the memory-based computing units 310 in each column are connected in series, the data output unit 340 can map the output result of each column according to the resistance, current, and other parameters of the output terminal of each column, and perform post-processing operations on the output result to obtain the final output data. Each column can be defined as a binary numerical weight from the least significant bit to the most significant bit.

[0054] For ease of understanding, Figure 4 A schematic diagram of another configurable multi-bit in-memory computing array is provided for embodiments of the present invention. See [link to schematic diagram]. Figure 4 In this embodiment of the invention, taking the multiplication of a 1*4 4-bit vector by a 4*1 4-bit vector as an example, the calculation is as follows: Vector multiplication and addition logic;

[0055] According to the array The memory-based computing unit 310 is configured, for example, in each column, the first column BL0 represents the weight of the most significant bit in the binary value, the fourth column BL3 represents the weight of the least significant bit in the binary value, and the other columns are defined sequentially. Alternatively, the first column BL0 can represent the weight of the least significant bit in the binary value, and the fourth column BL3 can represent the weight of the most significant bit in the binary value. In this embodiment of the invention, taking the example of the first column BL0 representing the weight of the most significant bit in the binary value and the fourth column BL3 representing the weight of the least significant bit in the binary value, each memory-based computing unit 310 is configured as follows: Figure 4The low-impedance or high-impedance weighted structure shown in the diagram allows the input signal unit 320 to output high-level data signals, low-level data signals, and high-level data signals to signal lines IN0, IN1, IN2, and IN3, respectively, forming a multi-bit input data, i.e., (1, 1, 0, 1). Based on the multiplication logic between 0 and 1 in the low-impedance and high-impedance weighted structures, the output state of each memory unit 310 can be obtained. Since the memory units 310 in each column are connected in series, the equivalent resistance of each column at the output terminal is the sum of the resistances of all memory units 310 in that column. Based on the equivalent resistance of each column, the corresponding output current can be generated. The data output unit 340 can obtain the output result of each column based on the current mapping at the output terminal of each column, and then perform post-processing operations on the output results of each column to obtain the final output data.

[0056] The technical solution provided by this invention uses an array of memory computing units, with multiple memory computing units connected in series in each column. The multiple columns of memory computing units form an integrated memory computing array. Each memory computing unit is configured as a low-impedance weighted structure or a high-impedance weighted structure. Each row of memory computing units is connected to an input signal unit, which sends a low-level data signal or a high-level data signal to each row of memory computing units. When the memory computing unit is configured as a low-impedance weighted structure, the input of the memory computing unit is a low-level data signal (corresponding to 0) or a high-level data signal (corresponding to 1), and the output is a low-impedance RL (corresponding to 0). When the memory computing unit is configured as a high-impedance weighted structure, the input of the memory computing unit is a low-impedance data signal (corresponding to 0), and the output is a low-impedance RL (corresponding to 0). When the input is a high-impedance data signal (corresponding to 1), the output is a high-impedance RH (corresponding to 1), thereby realizing the multiplication logic between 0 and 1. Since the storage units in each column are connected in series, the data output unit can map the output result of each column according to the parameters such as resistance and current at the output end of each column, perform post-processing operations on the output result to obtain the final output data, and realize multi-bit calculation.

[0057] In some embodiments, the signal output of the input signal unit 320 corresponding to each row can use the same input signal. That is, the signal output terminal of the input signal unit 320 outputs low-level data to form a low-level data signal, or outputs high-level data to form a high-level data signal. The signal output terminals corresponding to each row are respectively denoted as IN0, IN1, IN2, ..., INm. Figure 5 This invention provides a schematic diagram of another configurable multi-bit in-memory computing array. Figure 6 This is a schematic diagram of a low-resistivity weighted structure provided in an embodiment of the present invention. Figure 7 A schematic diagram of the weight design for another low-resistivity weight structure is provided for embodiments of the present invention. See [link to schematic diagram]. Figure 5-7The low-resistance weight structure includes a first weight unit 311, a second weight unit 312, a first switch unit 313, and a second switch unit 314; the first weight unit 311 is configured in a low-resistance state, and the second weight unit 312 is configured in a low-resistance state.

[0058] The first end of the first weighting unit 311 serves as the first end of the storage unit 310. The second end of the first weighting unit 311 is connected to the first end of the first switching unit 313, and the second end of the first switching unit 313 serves as the second end of the storage unit 310. The control end of the first switching unit 313 is connected to the signal output end of the input signal unit 320. The first switching unit 313 is used to be in a cutoff state according to a low-level data signal and in a conduction state according to a high-level data signal.

[0059] The first end of the second weighting unit 312 is connected to the first end of the first weighting unit 311, the second end of the second weighting unit 312 is connected to the first end of the second switching unit 314, and the second end of the second switching unit 314 is connected to the second end of the first switching unit 313; the control end of the second switching unit 314 is connected to the signal output end of the input signal unit 320; the second switching unit 314 is used to be in the on state according to the low level data signal and in the off state according to the high level data signal.

[0060] Specifically, both the first weighting unit 311 and the second weighting unit 312 are configured in a low-resistance state. For example, the first weighting unit 311 and the second weighting unit 312 are made of magnetoresistive random access memory (MRAM), so that the state of the first weighting unit 311 and the second weighting unit 312 can be configured by changing the current polarity.

[0061] The first weighting unit 311 and the first switching unit 313, the second weighting unit 312 and the second switching unit 314 are connected in parallel in the circuit. The signal output terminal of the input signal unit 320 is connected to the control terminals of the first switching unit 313 and the second switching unit 314, respectively. The first switching unit 313 is turned off according to the low-level data signal output by the input signal unit 320, and the second switching unit 314 is turned on according to the low-level data signal output by the input signal unit 320; the first switching unit 313 is turned on according to the high-level data signal output by the input signal unit 320, and the second switching unit 314 is turned off according to the high-level data signal output by the input signal unit 320. Thus, under the low-impedance weighting structure, the output of the storage unit 310 is always in a low-impedance state when the input signal unit 320 outputs a low-impedance data signal or a high-impedance data signal. The first switching unit 313 and the second switching unit 314 can be MOSFETs. For example, the first switching unit 313 is an NMOS switching unit, and the second switching unit 314 is a PMOS switching unit. Therefore, the first switching unit 313 is in the off state when a low-level data signal (corresponding to 0) is received at its control terminal, and in the on state when a high-level data signal (corresponding to 1) is received at its control terminal. Similarly, the second switching unit 314 is in the on state when a low-level data signal (corresponding to 0) is received at its control terminal, and in the off state when a high-level data signal (corresponding to 1) is received at its control terminal.

[0062] For example, the working principle of the memory-based computing unit 310 under the low-impedance weighted structure is as follows: a low-level data signal can be represented as "0", and a high-level data signal can be represented as "1". The first weighted unit 311 is configured in a low-impedance state, and the second weighted unit 312 is configured in a low-impedance state, that is, the weight of the memory-based computing unit 310 is 0. When the low-level data signal (corresponding to 0) is output by the input signal unit 320, the first switch unit 313 is turned off, and the second switch unit 314 is turned on. Therefore, the output of the memory-based computing unit 310 under the low-impedance weighted structure is the low-impedance state RL of the second weighted unit 312 (corresponding to 0). That is to say, at this time, the input is 0, the weight of the memory-based computing unit 310 is 0, and the output is 0. When the input signal unit 320 outputs a high-level data signal (corresponding to 1), the first switch unit 313 is turned on and the second switch unit 314 is turned off. Therefore, the output of the storage unit 310 under the low-impedance weight structure is the low-impedance state RL of the first weight unit 311 (corresponding to 0). That is to say, at this time, the input is 1, the weight of the storage unit 310 is 0, and the output is 0, realizing the multiplication logic between 0 and 1.

[0063] Based on the above embodiments, Figure 8 This is a schematic diagram of a high-resistivity weighted structure provided in an embodiment of the present invention. Figure 9 A schematic diagram of the weight design for another high-resistivity weight structure is provided for embodiments of the present invention. See [link to schematic diagram]. Figure 8-9The high-resistivity weighted structure includes a third weighting unit 321, a fourth weighting unit 322, a third switching unit 323, and a fourth switching unit 324; the third weighting unit 321 is configured in a high-resistivity state, and the fourth weighting unit 322 is configured in a low-resistivity state.

[0064] The first end of the third weighting unit 321 serves as the first end of the storage unit 310. The second end of the third weighting unit 321 is connected to the first end of the third switching unit 323. The second end of the third switching unit 323 serves as the second end of the storage unit 310. The control end of the third switching unit 323 is connected to the signal output end of the input signal unit 320. The third switching unit 323 is used to be in a cutoff state according to a low-level data signal and in a conduction state according to a high-level data signal.

[0065] The first end of the fourth weighting unit 322 is connected to the first end of the third weighting unit 321, the second end of the fourth weighting unit 322 is connected to the first end of the fourth switching unit 324, and the second end of the fourth switching unit 324 is connected to the second end of the third switching unit 323; the control end of the fourth switching unit 324 is connected to the signal output end of the input signal unit 320; the fourth switching unit 324 is used to be in the on state according to the low level data signal and in the off state according to the high level data signal.

[0066] Specifically, the third weighting unit 321 is configured in a high-resistance state, and the fourth weighting unit 322 is configured in a low-resistance state. For example, the third weighting unit 321 and the fourth weighting unit 322 employ magnetoresistive random access memory (MRAM), so that the states of the third weighting unit 321 and the fourth weighting unit 322 can be configured by changing the current polarity.

[0067] The third weighting unit 321 and the third switching unit 323, and the fourth weighting unit 322 and the fourth switching unit 324 are connected in parallel in the circuit. The signal output terminal of the input signal unit 320 is connected to the control terminals of the third switching unit 323 and the fourth switching unit 324, respectively. The third switching unit 323 is turned off according to the low-level data signal output by the input signal unit 320, and the fourth switching unit 324 is turned on according to the low-level data signal output by the input signal unit 320. Thus, under the high-low impedance weighting structure, the input signal unit 320 outputs a low-level data signal, and the storage unit 310 outputs a low-impedance state.

[0068] The third switching unit 323 is turned on based on the high-level data signal output by the input signal unit 320, and the fourth switching unit 324 is turned off based on the high-level data signal output by the input signal unit 320, outputting a low-impedance state. This achieves a high-level data signal output by the input signal unit 320 and a high-impedance output by the storage unit 310 under the high-low impedance weighting structure. The third switching unit 323 and the fourth switching unit 324 can be MOSFETs. For example, the third switching unit 323 is an NMOS switching unit, and the fourth switching unit 324 is a PMOS switching unit. Therefore, the control terminal of the third switching unit 323 is in the off state when a low-level data signal (corresponding to 0) is received, and in the on state when a high-level data signal (corresponding to 1) is received. Similarly, the control terminal of the fourth switching unit 324 is in the on state when a low-level data signal (corresponding to 0) is received, and in the off state when a high-level data signal (corresponding to 1) is received.

[0069] For example, the working principle of the memory-based unit 310 under the high-impedance weighted structure is as follows: a low-level data signal can be represented as "0", and a high-level data signal can be represented as "1". The third weighting unit 321 is configured in a high-impedance state, and the fourth weighting unit 322 is configured in a low-impedance state, that is, the weight of the memory-based unit 310 is 1. When the low-level data signal (corresponding to 0) is output by the input signal unit 320, the third switch unit 323 is turned off, and the fourth switch unit 324 is turned on. Therefore, the output of the memory-based unit 310 under the high-impedance weighted structure is the low-impedance state RL (corresponding to 0) of the fourth weighting unit 322. That is to say, at this time, the input is 0, the weight of the memory-based unit 310 is 1, and the output is 0. When the input signal unit 320 outputs a high-level data signal (corresponding to 1), the third switch unit 323 is turned on and the fourth switch unit 324 is turned off. Therefore, the output of the storage unit 310 under the high-impedance weight structure is the high-impedance state RH of the third weight unit 321 (corresponding to 1). That is to say, at this time, the input is 1, the weight of the storage unit 310 is 1, and the output is also 1, realizing the multiplication logic between 0 and 1.

[0070] Based on the above embodiments, in the in-memory computing array, the in-memory computing unit 310 needs to be programmed into a low-resistance weight structure or a high-resistance weight structure. Within both the low-resistance and high-resistance weight structures, one weight unit always remains in a low-resistance state. Therefore, when the low-resistance and high-resistance weight structures are reprogrammed, the weights do not need to be reprogrammed. This means that when the weight structure is updated, more than half of the weights in the in-memory computing array do not need to be changed, thus significantly reducing the latency associated with weight updates. Furthermore, since writing weights requires a large operating current, it can adversely affect the device's durability. Embodiments of the present invention can also achieve double the equivalent durability by alternately updating the weights of the weight units.

[0071] In some embodiments, the signal output of the input signal unit 320 corresponding to each row can adopt a shared complementary input signal. That is, the signal output terminal of the input signal unit 320 includes a first output terminal and a second output terminal. The first output terminal and the second output terminal corresponding to each row are respectively denoted as IN0(0), IN0(1); IN1(0), IN1(1); IN2(0), IN2(1)...INm(0), INm(1). When the first output terminal outputs low-level data, the second output terminal complementaryly outputs high-level data, and the output signals of the first output terminal and the second output terminal form a low-level data signal; when the first output terminal outputs high-level data, the second output terminal complementaryly outputs low-level data, and the output signals of the first output terminal and the second output terminal form a high-level data signal. Figure 10 This invention provides a schematic diagram of another configurable multi-bit in-memory computing array. Figure 11 This is a schematic diagram of the weight design for a low-resistivity weight structure according to an embodiment of the present invention. See [link / reference]. Figure 10-11 The low-resistance weight structure includes a first weight unit 311, a second weight unit 312, a first switch unit 313, and a second switch unit 314; the first weight unit 311 is configured in a low-resistance state, and the second weight unit 312 is configured in a low-resistance state.

[0072] The first end of the first weighting unit 311 is connected as the first end of the storage unit 310. The second end of the first weighting unit 311 is connected to the first end of the first switching unit 313. The second end of the first switching unit 313 is connected as the second end of the storage unit 310. The control end of the first switching unit 313 is connected to the first output end.

[0073] The first end of the second weighting unit 312 is connected to the first end of the first weighting unit 311; the second end of the second weighting unit 312 is connected to the first end of the second switching unit 314; the second end of the second switching unit 314 is connected to the second end of the first switching unit 313; the control end of the second switching unit 314 is connected to the second output end.

[0074] The first switching unit 313 is used to be in the off state according to low-level data and in the on state according to high-level data; the second switching unit 314 is used to be in the off state according to low-level data and in the on state according to high-level data.

[0075] Specifically, both the first weighting unit 311 and the second weighting unit 312 are configured in a low-resistance state. For example, the first weighting unit 311 and the second weighting unit 312 are made of magnetoresistive random access memory (MRAM), so that the state of the first weighting unit 311 and the second weighting unit 312 can be configured by changing the current polarity.

[0076] The first weighting unit 311 and the first switching unit 313, as well as the second weighting unit 312 and the second switching unit 314, are connected in parallel in the circuit. The first output terminal of the input signal unit 320 is connected to the control terminal of the first switching unit 313, and the second output terminal of the input signal unit 320 is connected to the control terminal of the second switching unit 314. When the first switching unit 313 outputs low-level data at its first output terminal, it is cut off. At this time, the second output terminal outputs high-level data, and the second switching unit 314 is turned on. When the first switching unit 313 outputs high-level data at its first output terminal, it is turned on. At this time, the second output terminal outputs low-level data, and the second switching unit 314 is cut off. Thus, under the low-impedance weighting structure, whether the input signal unit 320 outputs a low-impedance data signal or a high-impedance data signal, the output of the storage unit 310 is always in a low-impedance state. The first switching unit 313 and the second switching unit 314 can be MOS switches. For example, both the first switching unit 313 and the second switching unit 314 can be NMOS switches. Using the same switching unit can reduce the data impact caused by differences between products during the fabrication of the memory computing unit 310. The control terminals of the first switching unit 313 and the second switching unit 314 are the signal input terminals of the memory computing unit.

[0077] For example, the working principle of the memory-based computing unit 310 under the low-impedance weighted structure is as follows: when the first output terminal outputs low-level data, the second output terminal outputs high-level data in a complementary manner, and the output signals of the first output terminal and the second output terminal form a low-level data signal; the first weighted unit 311 is configured in a low-impedance state, and the second weighted unit 312 is configured in a low-impedance state, that is, the weight of the memory-based computing unit 310 is 0. When the first output terminal outputs low-level data, the second output terminal outputs high-level data in a complementary manner, the first switch unit 313 is turned off, and the second switch unit 314 is turned on. Therefore, the output of the memory-based computing unit 310 under the low-impedance weighted structure is the low-impedance state RL (corresponding to 0) of the second weighted unit 312. That is to say, at this time, the input is 0, the weight of the memory-based computing unit 310 is 0, and the output is 0. When the first output terminal outputs high-level data, the second output terminal outputs low-level data in a complementary manner. The output signals of the first and second output terminals form a high-level data signal. At this time, the first switching unit 313 is turned on and the second switching unit 314 is turned off. Therefore, the output of the storage unit 310 under the low-impedance weight structure is the low-impedance state RL (corresponding to 0) of the first weight unit 311. That is to say, at this time, the input is 1, the weight of the storage unit 310 is 0, and the output is 0, realizing the multiplication logic between 0 and 1.

[0078] Figure 12 This is a schematic diagram of the weight design for a high-resistivity weight structure according to an embodiment of the present invention. See [link / reference]. Figure 12The high-resistivity weighted structure includes a third weighting unit 321, a fourth weighting unit 322, a third switching unit 323, and a fourth switching unit 324; the third weighting unit 321 is configured in a high-resistivity state, and the fourth weighting unit 322 is configured in a low-resistivity state.

[0079] The first end of the third weighting unit 321 serves as the first end of the storage unit 310. The second end of the third weighting unit 321 is connected to the first end of the third switching unit 323. The second end of the third switching unit 323 serves as the second end of the storage unit 310. The control end of the third switching unit 323 is connected to the first output end.

[0080] The first end of the fourth weighting unit 322 is connected to the first end of the third weighting unit 321, the second end of the fourth weighting unit 322 is connected to the first end of the fourth switching unit 324, the second end of the fourth switching unit 324 is connected to the second end of the third switching unit 323; the control end of the fourth switching unit 324 is connected to the second output end.

[0081] The third switch unit 323 is used to be in the off state according to low-level data and in the on state according to high-level data; the fourth switch unit 324 is used to be in the off state according to low-level data and in the on state according to high-level data.

[0082] Specifically, the third weighting unit 321 is configured in a high-resistance state, and the fourth weighting unit 322 is configured in a low-resistance state. For example, the third weighting unit 321 and the fourth weighting unit 322 employ magnetoresistive random access memory (MRAM), so that the states of the third weighting unit 321 and the fourth weighting unit 322 can be configured by changing the current polarity.

[0083] The third weighting unit 321 and the third switch unit 323, and the fourth weighting unit 322 and the fourth switch unit 324 are connected in parallel in the circuit. The first output terminal of the input signal unit 320 is connected to the control terminal of the third switch unit 323, and the second output terminal of the input signal unit 320 is connected to the control terminal of the fourth switch unit 324. When the third switch unit 323 outputs low-level data at its first output terminal, it is cut off. At this time, the second output terminal outputs high-level data, and the fourth switch unit 324 is turned on. Thus, under the high-low impedance weighting structure, the input signal unit 320 outputs a low-level data signal, and the storage unit 310 outputs a low-impedance state.

[0084] The third switching unit 323 is turned on when the first output terminal outputs high-level data. At this time, the second output terminal outputs low-level data, and the fourth switching unit 324 is turned off. This achieves a high-level data signal output from the input signal unit 320 and a high-impedance output from the memory unit 310 under the high-low impedance weighting structure. The third switching unit 323 and the fourth switching unit 324 can be MOS switches; for example, they can be NMOS switches. The control terminals of the third switching unit 323 and the fourth switching unit 324 are the signal input terminals of the memory unit.

[0085] For example, the working principle of the memory-based computing unit 310 under the high-impedance weighted structure is as follows: When the first output terminal outputs low-level data, the second output terminal outputs high-level data in a complementary manner, and the output signals of the first and second output terminals form a low-level data signal; the third weighted unit 321 is configured in a high-impedance state, and the fourth weighted unit 322 is configured in a low-impedance state, that is, the weight of the memory-based computing unit 310 is 1. When the first output terminal outputs low-level data, the second output terminal outputs high-level data in a complementary manner, the third switch unit 323 is turned off, and the fourth switch unit 324 is turned on. Therefore, the output of the memory-based computing unit 310 under the high-impedance weighted structure is the low-impedance state RL (corresponding to 0) of the second weighted unit 312. That is to say, at this time, the input is 0, the weight of the memory-based computing unit 310 is 1, and the output is 0. When the first output terminal outputs high-level data, the second output terminal outputs low-level data in a complementary manner. The third switch unit 323 is turned on, and the fourth switch unit 324 is turned off. Therefore, the output of the storage unit 310 under the high-impedance weight structure is the high-impedance state RH (corresponding to 1) of the third weight unit 321. That is to say, at this time, the corresponding input is 1, the weight of the storage unit 310 is 1, and the output is also 1, realizing the multiplication logic between 0 and 1.

[0086] In some embodiments, the data output unit 340 may employ a current-to-voltage conversion module and an analog-to-digital conversion module. Since the calculated equivalent resistance of each column in the array is different, the output current is also different. First, the output current of each column is passed through a current-to-voltage conversion module. Assuming the input current to the array current-to-voltage module is I, the output voltage value is I*R. Then, an analog-to-digital conversion module converts the output voltage value into a digital code value, and finally, a shift-and-add method is used to obtain the final output result.

[0087] In some embodiments, Figure 13 A schematic diagram of the output circuit provided in an embodiment of the present invention is shown below. Figure 13The data output unit 340 can adopt a structure of charging unit 120 + statistics unit 110 + output unit 130. The charging unit 120 is used to charge according to the current signal output by the storage array; the statistics unit 110 is used to obtain the time parameter value of the current column charging unit 120 to complete charging according to the voltage of the charging unit 120; the output unit 130 is used to shift and add the time parameter value of each column to obtain multi-bit data of a specific position; the output unit 130 is also used to shift and add the multi-bit data of other specific positions to obtain the final output data.

[0088] Specifically, the output terminal of each column in the memory array is connected to the first terminal of a charging unit 120, and the second terminal of the charging unit 120 is grounded; the first terminal of a statistics unit 110 is connected to the first terminal of the charging unit 120 of the corresponding column, and the second terminal of the statistics unit 110 is connected to the input terminal of the output unit 130.

[0089] In the memory array, the equivalent resistance of each column is different after weight calculation, resulting in different output currents for each column. Each column's output is connected to a charging unit 120 to charge the unit. Due to the different charging currents, the time parameter value for each charging unit 120 to reach the preset voltage is also different. For example, the charging unit 120 can be a charging capacitor. After the charging unit 120 is charged to the preset voltage, the statistics unit 110 can statistically determine the time parameter value for the charging unit 120 to complete charging based on the current voltage of the charging unit 120. For instance, the statistics unit 110 can consist of a comparator and a counter. The counter starts timing after each column outputs a current signal. As the charging unit 120 charges, the comparator compares the charging voltage with the preset voltage. When the charging voltage reaches the preset voltage, the counter stops timing, thus allowing the statistical determination of the time parameter value.

[0090] The output unit 130 shifts and adds the output data of each column to obtain multi-bit data with a specific position, where the specific position refers to the data bit of the output data. Then, the output data with data bits shifted from low to high is added to obtain the final output data.

[0091] For ease of understanding, the following calculations are exemplified in the embodiments of the present invention:

[0092] but,

[0093] a=1101*1000+1011*1011+0110*0000+0101*0101;

[0094] Combination Figure 4 In embodiments of the present invention, based on the array The memory-based computing unit 310 is configured, for example, in each column, the first column BL0 represents the weight of the most significant bit in the binary value, the fourth column BL3 represents the weight of the least significant bit in the binary value, and the other columns are defined sequentially. Alternatively, the first column BL0 can represent the weight of the least significant bit in the binary value, and the fourth column BL3 can represent the weight of the most significant bit in the binary value. In this embodiment of the invention, taking the example of the first column BL0 representing the weight of the most significant bit in the binary value and the fourth column BL3 representing the weight of the least significant bit in the binary value, each memory-based computing unit 310 is configured as follows: Figure 4 The low-resistivity weights or high-resistivity weights are shown below. For the input vector, the least significant bit multiplier in the input vector is first calculated to obtain the least significant bit sum, i.e. That is, multiplying a 1*4 4-bit vector by a 4*1 4-bit vector results in the current output corresponding to the equivalent resistance of each column, charging the charging unit. The statistics unit can calculate the time parameter value for each column. For example, the time parameter value for the first column BL0 is 10, the time parameter value for the second column BL1 is 01, the time parameter value for the third column BL2 is 01, and the time parameter value for the fourth column BL3 is 10. The output unit 130 then performs a shift and summation based on the data bits in each column, resulting in a shift and summation of 11000, obtaining the sum of the least significant bits. This process is repeated for subsequent inputs. Up to the highest position After obtaining the output data of the four specific positions, the results of each position are shifted and added together to obtain the final output data. It should be noted that the row and column parameters of the in-memory computing array in this embodiment of the invention are only for illustration and are not specifically limited. The in-memory computing array can be extended, for example, with n columns and m rows, where n and m are both integers greater than or equal to 1.

[0095] In this embodiment of the invention, by connecting the output terminal of each column in the storage array to a charging unit, the equivalent resistance of each column is different after calculation. The statistics unit calculates the charging time of the charging unit to obtain the time parameter value. The output unit shifts and adds the output data of each column to obtain multi-bit data of a specific position. Here, the specific position refers to the data bit of the output data. Then, the output data of the data bits from low to high is shifted and added to obtain the final output data.

[0096] This invention also provides an in-memory computing chip, which includes any configurable multi-bit in-memory computing array according to this invention, and therefore has the same beneficial effects, which will not be described in detail here.

[0097] This invention also provides an electronic device that may include the aforementioned in-memory computing chip. Since it includes any configurable multi-bit in-memory computing array as described in this invention, it has the same beneficial effects, and will not be repeated here. The electronic device may be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A configurable multi-bit in-memory computing array, characterized in that, include: Multiple memory processing units, input signal units, bit lines, and data output units; The memory computing unit array is arranged such that the memory computing units in each column are connected in series; the first end of the first memory computing unit in each column is connected to the bit line; the bit line is used to input a reference voltage signal. The signal input terminal of the memory-based computing unit in the same row is connected to the signal output terminal of the input signal unit corresponding to the current row; the input signal unit is used to output a low-level data signal or a high-level data signal to the memory-based computing unit in each row; The data output unit is connected to the second end of the storage unit at the end of each column; the data output unit is used to perform post-processing operations on the output signal of the storage unit in each column. The in-memory computing unit is configured as a low-impedance weighted structure or a high-impedance weighted structure. When the in-memory computing unit is configured as a low-impedance weighted structure, its output is in a low-impedance state when its signal input terminal receives either a low-level data signal or a high-level data signal. When the in-memory computing unit is configured as a high-impedance weighted structure, its output is in a low-impedance state when its signal input terminal receives a low-level data signal, and in a high-impedance state when its signal input terminal receives a high-level data signal. The low-resistivity weight structure includes a first low-resistivity weight structure or a second low-resistivity weight structure; The first low-impedance weighting structure includes a first weighting unit, a second weighting unit, a first switching unit, and a second switching unit. The first weighting unit is configured in a low-impedance state, and the second weighting unit is also configured in a low-impedance state. A first terminal of the first weighting unit serves as the first terminal of the memory-based computing unit, and a second terminal of the first weighting unit is connected to the first terminal of the first switching unit, serving as the second terminal of the memory-based computing unit. A control terminal of the first switching unit is connected to the signal output terminal of the input signal unit. The first switching unit is configured to be in a cutoff state based on a low-level data signal and a conduction state based on a high-level data signal. The first terminal of the second weighting unit is connected to the first terminal of the first weighting unit, and the second terminal of the second weighting unit is connected to the first terminal of the second switching unit, as is the second terminal of the second switching unit. A control terminal of the second switching unit is connected to the signal output terminal of the input signal unit. The second switching unit is configured to be in a conduction state based on a low-level data signal and a cutoff state based on a high-level data signal. The second low-impedance weighting structure includes a first weighting unit, a second weighting unit, a first switching unit, and a second switching unit; the first weighting unit is configured in a low-impedance state, and the second weighting unit is configured in a low-impedance state; the signal output terminals of the input signal units corresponding to each row include a first output terminal and a second output terminal; the first output terminal outputs low-level data, and the second output terminal outputs high-level data to form the low-level data signal; the first output terminal outputs high-level data, and the second output terminal outputs low-level data to form the high-level data signal; the first terminal of the first weighting unit serves as the first terminal of the memory unit, and the second terminal of the first weighting unit is connected to the first terminal of the first switching unit. The first switch unit is connected to the second terminal of the storage unit, and the second terminal of the first switch unit is connected to the first output terminal. The first terminal of the second weight unit is connected to the first terminal of the first weight unit, the second terminal of the second weight unit is connected to the first terminal of the second switch unit, and the second terminal of the second switch unit is connected to the second terminal of the first switch unit. The control terminal of the second switch unit is connected to the second output terminal. The first switch unit is used to be in a cutoff state according to the low-level data and in a conduction state according to the high-level data. The second switch unit is used to be in a cutoff state according to the low-level data and in a conduction state according to the high-level data.

2. The configurable multi-bit in-memory computing array according to claim 1, characterized in that, When the low-resistivity weight structure is the first low-resistivity weight structure, the high-resistivity weight structure includes a third weight unit, a fourth weight unit, a third switching unit, and a fourth switching unit; the third weight unit is configured in a high-resistivity state, and the fourth weight unit is configured in a low-resistivity state. The first end of the third weighting unit serves as the first end of the storage unit, and the second end of the third weighting unit is connected to the first end of the third switching unit. The second end of the third switching unit serves as the second end of the storage unit. The control end of the third switching unit is connected to the signal output end of the input signal unit. The third switching unit is used to be in a cutoff state according to the low-level data signal and in a conduction state according to the high-level data signal. The first end of the fourth weighting unit is connected to the first end of the third weighting unit, the second end of the fourth weighting unit is connected to the first end of the fourth switching unit, and the second end of the fourth switching unit is connected to the second end of the third switching unit; the control end of the fourth switching unit is connected to the signal output end of the input signal unit; the fourth switching unit is used to be in a conducting state according to the low-level data signal and in a cut-off state according to the high-level data signal.

3. The configurable multi-bit in-memory computing array according to claim 2, characterized in that, The first and third switching units are NMOS switches; the second and fourth switching units are PMOS switches.

4. The configurable multi-bit in-memory computing array according to claim 1, characterized in that, When the low-resistivity weight structure is the second low-resistivity weight structure, the high-resistivity weight structure includes a third weight unit, a fourth weight unit, a third switch unit, and a fourth switch unit; the third weight unit is configured in a high-resistivity state, and the fourth weight unit is configured in a low-resistivity state. The first end of the third weighting unit serves as the first end of the storage unit, the second end of the third weighting unit is connected to the first end of the third switching unit, and the second end of the third switching unit serves as the second end of the storage unit; the control end of the third switching unit is connected to the first output end. The first end of the fourth weighting unit is connected to the first end of the third weighting unit, the second end of the fourth weighting unit is connected to the first end of the fourth switching unit, and the second end of the fourth switching unit is connected to the second end of the third switching unit; the control end of the fourth switching unit is connected to the second output end. The third switching unit is used to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data; the fourth switching unit is used to be in a cutoff state based on the low-level data and in a conduction state based on the high-level data.

5. The configurable multi-bit in-memory computing array according to claim 4, characterized in that, The first switching unit, the second switching unit, the third switching unit, and the fourth switching unit are all NMOS switching transistors.

6. The configurable multi-bit in-memory computing array according to claim 2 or 4, characterized in that, The first weighting unit, the second weighting unit, the fourth weighting unit, and the third weighting unit are magnetoresistive random access memories.

7. A memory computing chip, characterized in that, Includes the configurable multi-bit in-memory array as described in any one of claims 1-6.

8. An electronic device, characterized in that, Including the in-memory computing chip as described in claim 7.

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