Memory programming methods, memory and storage systems

Abstract

This application provides a method for programming a memory, a memory, and a memory system, relating to the field of memory technology. The memory includes n storage surfaces, where n ≥ 2 and n is an integer. The method includes: determining a target programming mode corresponding to a programming task from multiple programming modes; and, in response to the target programming mode being a non-full-process programming mode, applying an additional load to the storage surface where programming is performed under the target programming mode. This additional load is used to balance the programming load between the target programming mode and the full-process programming mode. By applying an additional load to the target programming process, the difference in programming efficiency between the target programming mode and the full-process programming mode is reduced. When the difference in programming efficiency between the various programming modes is small, each programming mode can share some parameters related to programming efficiency, thereby reducing the need for parameter debugging and the number of tests.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a programming method for a memory, a memory, and a storage system. Background Technology

[0002] Three-dimensional (3D) memory supports multiple programming modes during programming, such as: Single Plane (SP) programming mode, Double Plane (DP) programming mode, Quadra Plane (QP) programming mode, and All Plane (AP) programming mode. The memory is programmed using one programming mode at a time. Different programming modes can adapt to different product needs, thus providing a more flexible programming solution.

[0003] However, when collecting experimental data from multiple different modes, it was found that the programming efficiency differed between the different modes due to the RC delay. Under these programming differences, the programming parameters corresponding to different modes need to be adjusted independently, and the process of determining the programming parameters is inefficient. Summary of the Invention

[0004] This application provides a method for programming a memory, a memory, and a storage system, which can reduce the difference in programming efficiency between different programming modes. The technical solution is as follows:

[0005] On one hand, a method for programming a memory is provided, the memory comprising n storage surfaces, n ≥ 2 and n is an integer, the method comprising:

[0006] The target programming mode corresponding to the programming task is determined from multiple programming modes, including a full programming mode and a non-full programming mode. The full programming mode refers to the mode of programming the n storage surfaces in the programming task, and the non-full programming mode refers to the mode of programming a portion of the n storage surfaces in the programming task.

[0007] In response to the target programming mode belonging to the non-full-scale programming mode, an additional load is applied to the storage surface where programming is performed in the target programming mode. This additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

[0008] In some alternative embodiments, applying additional load to the storage surface where programming is performed in the target programming mode includes:

[0009] The storage surface for programming in the target programming mode is connected to a designated load element, which provides the additional load to the storage surface for programming in the target programming mode.

[0010] In some optional embodiments, connecting the storage surface for programming in the target programming mode to a designated load element includes:

[0011] Connect the storage surface for programming in the target programming mode to the specified capacitor element;

[0012] or,

[0013] Connect the storage surface that performs programming in the target programming mode to the specified resistive element.

[0014] In some optional embodiments, the method further includes:

[0015] The specified load element is connected to the storage surface that performs programming in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection state between the specified load element and the storage surface that changes according to the requirements of the programming task.

[0016] In some optional embodiments, the method further includes:

[0017] During the testing of the memory, the memory surface for programming in the target programming mode is connected to the designated load element based on the active connection method, and the programming process is executed to generate the first programming test data;

[0018] Based on the active connection method, the storage surface for programming in the target programming mode is disconnected from the designated load element, and the programming process is executed to generate second programming test data;

[0019] Based on the data comparison relationship between the first programming test data and the second programming test data, the connection status of the specified load element with the storage surface for programming in the target programming mode is determined.

[0020] In some optional embodiments, determining the connection state of the specified load element with the storage surface performing programming in the target programming mode based on the data comparison relationship between the first programming test data and the second programming test data includes:

[0021] In response to the fact that the data performance corresponding to the first programming test data is better than the data performance corresponding to the second programming test data, it is determined that the specified load element is connected to the storage surface for programming in the target programming mode;

[0022] In response to the fact that the data performance corresponding to the second programming test data is better than the data performance corresponding to the first programming test data, it is determined that the specified load element is disconnected from the storage surface where programming is performed in the target programming mode.

[0023] In some alternative embodiments, applying additional load to the storage surface where programming is performed in the target programming mode includes:

[0024] The programming phase of the full programming mode is executed, wherein invalid programming of the deselected memory blocks is performed on the other memory surfaces among the n memory surfaces, and the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode;

[0025] Perform effective programming on the selected memory block for the memory surface that is being programmed under the target programming mode.

[0026] In some optional embodiments, the method further includes:

[0027] During the verification phase, a programming verification voltage is applied to the selected memory block, which is used to verify the programming phase of the selected memory block; wherein, the verification phase is omitted during the programming process of the deselected memory block.

[0028] In some alternative embodiments, the memory includes a six-sided memory;

[0029] The non-comprehensive programming mode includes at least one of the following: single-sided programming mode, double-sided programming mode, and four-sided programming mode.

[0030] On the other hand, a memory is provided, the memory comprising: a control circuit and n storage surfaces, where n≥2 and n is an integer, and the storage surfaces include storage blocks;

[0031] The control circuit is configured to determine the target programming mode corresponding to the programming task from a variety of programming modes, including a full programming mode and a non-full programming mode. The full programming mode refers to the mode of programming the n memory surfaces in the programming task, and the non-full programming mode refers to the mode of programming a portion of the n memory surfaces in the programming task.

[0032] The control circuit is configured to apply an additional load to the memory surface where programming is performed in the target programming mode in response to the target programming mode belonging to the non-full-scale programming mode. The additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

[0033] In some alternative embodiments, the control circuitry is configured to connect the storage surface for programming in the target programming mode to the designated load element.

[0034] In some alternative embodiments, the control circuit is configured to connect the memory surface for programming in the target programming mode to a designated capacitive element; or,

[0035] The control circuit is configured to connect the storage surface for programming in the target programming mode to a designated resistive element.

[0036] In some optional embodiments, the control circuit is configured to connect the designated load element to the storage surface that performs programming in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection state between the designated load element and the storage surface that changes as needed.

[0037] In some optional embodiments, the control circuit is configured to, during the testing of the memory, connect the memory surface to be programmed in the target programming mode to the designated load element based on the active connection method, and execute the programming process to generate first programming test data;

[0038] The control circuit is configured to disconnect the storage surface that performs programming in the target programming mode from the designated load element based on the active connection method, and execute the programming process to generate second programming test data;

[0039] The control circuit is configured to determine the connection state of the specified load element with the storage surface for programming in the target programming mode based on the data comparison relationship between the first programming test data and the second programming test data.

[0040] In some optional embodiments, the control circuit is configured to determine that the specified load element is connected to the storage surface for programming in the target programming mode in response to the data performance corresponding to the first programming test data being better than the data performance corresponding to the second programming test data.

[0041] The control circuit is configured to determine, in response to the data performance corresponding to the second programming test data being better than the data performance corresponding to the first programming test data, that the designated load element is disconnected from the storage surface where programming is performed in the target programming mode.

[0042] In some alternative embodiments, the control circuit is configured to perform a programming phase of the full programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among the n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed under the target programming mode, wherein the other memory surfaces are memory surfaces other than the memory surfaces that are programmed under the target programming mode.

[0043] In some alternative embodiments, the control circuit is configured to apply a programming verification voltage to the selected memory block, the programming verification voltage being used to verify the programming stage of the selected memory block; wherein the programming verification stage is omitted during the programming process of the deselected memory block.

[0044] In some alternative embodiments, the memory includes a six-sided memory;

[0045] The non-comprehensive programming mode includes at least one of the following: single-sided programming mode, double-sided programming mode, and four-sided programming mode.

[0046] On the other hand, a storage system is provided, the storage system comprising:

[0047] One or more memories, the memories comprising n memory surfaces, where n ≥ 2 and n is an integer, and,

[0048] A load element is specified for connection to the storage surface where programming is performed in the target programming mode, and the additional load is provided to the storage surface where programming is performed in the target programming mode. The target programming mode is a non-full-scale programming mode, and the additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

[0049] A memory controller coupled to the memory and configured to control the memory.

[0050] On the other hand, a storage system is provided, the storage system comprising:

[0051] One or more memories, the memories comprising n memory surfaces, where n ≥ 2 and n is an integer, and,

[0052] A memory controller coupled to and configured to control the memory, wherein the memory controller is configured to control the memory to perform a full programming phase when programming is performed in a target programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed in the target programming mode, wherein the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode.

[0053] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a control circuit, implement the memory programming method as described in any of the above embodiments.

[0054] The technical solution provided in this application may include the following beneficial effects:

[0055] By imposing additional load on the target programming mode, the difference in programming efficiency between the target and full programming modes is reduced, such as by reducing differences in programming time and margin. On one hand, when the differences in programming efficiency between the various programming modes are small, they can share some efficiency-related parameters, such as the programming pulse width, thereby reducing the need for parameter debugging and the number of tests. On the other hand, because the various programming modes can share some efficiency-related parameters, the space occupied by parameter storage is reduced. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of test data for a 3D memory product provided in an illustrative embodiment of this application;

[0058] Figure 2 This is a schematic diagram of the structure of a 3D memory provided in an illustrative embodiment of this application;

[0059] Figure 3 This is a flowchart of a multifaceted programming process provided in an exemplary embodiment of this application;

[0060] Figure 4 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application;

[0061] Figure 5 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application;

[0062] Figure 6 This is a schematic diagram illustrating the programming differences between the target programming mode and the comprehensive programming mode provided in an exemplary embodiment of this application;

[0063] Figure 7 This is a schematic diagram illustrating the programming differences between the target programming mode and the comprehensive programming mode provided in another exemplary embodiment of this application;

[0064] Figure 8 This is a schematic diagram of the structure of a memory provided in an exemplary embodiment of this application;

[0065] Figure 9 This is a schematic diagram of the structure of a storage system provided in an exemplary embodiment of this application. Detailed Implementation

[0066] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0067] The memory programming method provided in this application embodiment can be applied to memory. The memory can be a three-dimensional (3D) memory, such as a 3D NAND flash memory.

[0068] Optionally, the 3D memory includes peripheral circuitry and n memory planes, wherein each memory plane includes multiple memory blocks, each memory block includes multiple memory pages, and each memory page includes multiple memory cells. In some embodiments, a memory page is the smallest unit for reading and programming, and a memory block is the smallest unit for erasing. Memory cells in a memory plane can be addressed via word lines and bit lines.

[0069] Peripheral circuitry can include any digital, analog, or mixed-signal circuitry configured to perform various operations on the memory, such as read, write, and erase operations. Examples of peripheral circuitry include control logic, data buffers, decoders, drivers, and read / write circuits.

[0070] For the multiple storage surfaces contained in a 3D memory, the 3D memory can provide a single-plane programming mode or a multi-plane programming mode.

[0071] In this context, single-plane (SP) programming mode refers to programming a memory block on a single memory plane in a 3D memory; multi-plane programming mode refers to programming memory blocks on multiple memory planes simultaneously in a 3D memory. Taking a memory cell array comprising six memory planes as an example, multi-plane programming mode includes at least one of the following modes:

[0072] Double-plane (DP) programming mode refers to programming memory blocks on two memory planes in a 3D memory.

[0073] The Quadra Plane (QP) programming mode refers to programming the memory blocks in the four memory planes of a 3D memory.

[0074] All Plane (AP) programming mode, also known as HP programming mode, refers to programming the memory blocks in all memory planes of a 3D memory. Taking a memory with 6 memory planes as an example, AP programming mode means programming the memory blocks in all 6 memory planes simultaneously.

[0075] However, for the aforementioned single-sided and multi-sided programming modes, the programming load differs between the modes. For example, in single-sided programming mode, the voltage only needs to pass through one storage surface, so the programming load is the resistance generated by that storage surface when the voltage flows through it. In full-sided programming mode, the voltage needs to reach and pass through all storage surfaces, so the programming load is the resistance generated by each storage surface when the voltage flows through all storage surfaces. This leads to an imbalance in load due to RC delays in different programming modes. (For illustrative purposes, please refer to...) Figure 1 In the test data of 3D memory products, there are obvious differences in programming time and programming efficiency among different programming modes. For example, the programming speed of full programming mode is about 354.16 microseconds / page, while the programming speed of single-sided programming mode is about 369.9 microseconds / page, with a difference of about 15 microseconds per page.

[0076] 3D memory is a multi-layered stacked memory, where memory cells in the aforementioned memory planes can form memory strings based on the connections of bit lines and source lines. Illustratively, this 3D memory is a 3D NAND flash memory. For example... Figure 2 As shown, the 3D memory 100 includes multiple memory strings 110 arranged in a direction parallel to the substrate's bearing surface, and multiple memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the substrate's bearing surface. That is, the multiple memory cells included in the 3D memory are arranged in a three-dimensional array on the substrate, forming a memory array.

[0077] One end of the storage string 110 is connected to the bit line (BL), and the other end is connected to the source line (SL).

[0078] The memory cells in each memory string are also connected to memory cells in other memory strings via word lines (WL). For example, if each memory string can include 64 memory cells, then the 3D memory can include 64 word lines WL<63:0>, and each word line is connected to a portion of memory cells located on the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells is only a specific example, and the application is not limited to this. In some embodiments, each memory string can include more than 64 memory cells, such as 128, 196, etc. In the 3D memory, the memory cells connected to the same word line constitute a memory page, all memory strings sharing a set of word lines constitute a memory block, and multiple memory blocks form a memory surface.

[0079] The memory string 110 also includes an upper select transistor connected to the drain of the first memory cell and a lower select transistor connected to the source of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor. The lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0080] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell, and the drain of the TSG is connected to the bit line.

[0081] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell, and the source of the BSG is connected to the source line.

[0082] Depend on Figure 1 It is known that the memory cells in memory string 110 share a set of memory lines (WL) with the memory cells in other memory strings. Assuming each memory string includes m+1 memory cells, the 3D memory can include m+1 WLs: WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., at the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell located on the same layer, and the gate connection lines between each control gate, constitute a WL.

[0083] Based on the amount of data that a storage unit can store, storage units can be classified into single-level cells (SLC), multi-level cells (MLC), tri-level cells (TLC), and quadri-level cells (QLC). Each SLC can store 1 bit of data, each MLC can store 2 bits, each TLC can store 3 bits, and each QLC can store 4 bits. In 3D memory, the data stored in storage units located in the same layer can form k storage pages, where k is the number of bits of data that each storage unit can store.

[0084] In this embodiment, the storage cell in the 3D memory can be a floating-gate field-effect transistor (FET) or a charge-trap FET, or other data-storing FET. The TSG and BSG can be ordinary FETs or data-storing FETs. The floating-gate FET includes a source, a drain, and two gates. Both gates are conductors, and one is a control gate (CG), while the other is a floating gate (FG), referred to simply as a floating gate. The control gate is used to connect word lines, and the floating gate is used as a data storage cell. The charge-trap FET includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is used as a data storage cell and is made of an insulating material such as silicon nitride. The following section uses a floating-gate FET as an example to introduce the data writing principle, i.e., the programming principle, of the storage cell.

[0085] When writing data into a memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor (FET), causing electrons in the FET's channel to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that different threshold voltages Vth require different voltages applied to the control gate to turn the FET on. Therefore, the magnitude of the threshold voltage Vth of the FET reflects the content of the stored data.

[0086] It should be understood that in 3D memory, the channels of each memory cell in each memory string can be connected sequentially to form a columnar structure perpendicular to the substrate.

[0087] Currently, the main programming method used in memory programming is Increment Step Pulse Program (ISPP). During the programming phase, the programming voltage is not applied all at once, but is increased step by step until the voltage meets the programming requirements.

[0088] In this embodiment of the application, to address the issue of differences in programming efficiency among different programming modes, the load between different programming modes is balanced by increasing the load on the programming stage, thereby reducing the differences in programming efficiency among different programming modes.

[0089] Indicative, Figure 3 This is a flowchart illustrating a multifaceted programming process provided in an exemplary embodiment of this application. For example... Figure 3As shown, the process includes the following steps.

[0090] Step 301: Determine the target programming mode corresponding to the programming task from multiple programming modes.

[0091] Multiple programming modes include full programming mode and non-full programming mode. Full programming mode refers to programming n storage surfaces in a programming task, where n≥2 and n is an integer. Non-full programming mode refers to programming a portion of the n storage surfaces in a programming task.

[0092] Taking a memory with 6 memory surfaces as an example, the full programming mode refers to the mode of programming all 6 memory surfaces, which is the AP programming mode mentioned above; the non-full programming mode refers to the mode of programming some of the 6 memory surfaces, which is any one of the SP programming mode, DP programming mode, and QP programming mode mentioned above.

[0093] Optionally, the target programming mode can be either a full programming mode or a non-full programming mode, that is, the target programming mode can be any one of the AP programming mode, SP programming mode, DP programming mode, and QP programming mode.

[0094] When determining the target programming mode, it may be determined based on the programming requirements of the programming task, or it may be determined randomly; this embodiment does not limit this. The methods for determining the programming mode include, but are not limited to, any of the following:

[0095] 1. Determine the target programming mode based on the amount of programming data corresponding to the programming task. For example, if the amount of programming data corresponding to the programming task is large, determine the AP programming mode or QP programming mode as the target programming mode; if the amount of programming data corresponding to the programming task is small, determine the SP programming mode or DP programming mode as the target programming mode.

[0096] 2. Determine the target programming mode based on the preset selection order of programming modes and the programming mode selected in the most recent programming task. For example, the preset selection order is AP programming mode, SP programming mode, DP programming mode, QP programming mode. If the programming mode selected in the most recent programming task is SP programming mode, then DP programming mode is determined as the target programming mode.

[0097] 3. Randomly select one from multiple programming modes as the target programming mode.

[0098] 4. Determine the programming mode based on the data write situation in multiple storage planes. For example, if four out of six storage planes have a large amount of data written, and two storage planes have a small amount of data written, then program the two storage planes with the smaller amount of data, using the SP programming mode as the target programming mode; or program the two storage planes, using the DP programming mode as the target programming mode.

[0099] It is worth noting that the above-described method for determining the target programming pattern is merely an illustrative example, and the embodiments of this application do not limit it.

[0100] When the target programming mode is SP programming mode, firstly, determine the memory surface that needs to be programmed from the 6 memory surfaces. This can be any one of the 6 memory surfaces randomly determined, or a memory surface determined according to a preset determination rule. Apply a programming pulse voltage to the selected memory cell in the memory block that needs to be programmed in the memory surface to program the memory cell. When applying the programming pulse voltage, apply a voltage to the word line corresponding to the memory cell.

[0101] When the target programming mode is DP programming mode, firstly, two memory surfaces out of the six memory surfaces that need to be programmed are determined. Programming pulse voltages are then applied to selected memory cells in the memory blocks that need to be programmed in the two memory surfaces to program the memory cells. Optionally, programming pulse voltages can be applied to selected memory cells in the memory blocks that need to be programmed in both memory surfaces simultaneously.

[0102] When the target programming mode is QP programming mode, firstly, four memory surfaces out of the six memory surfaces that need to be programmed are determined. Programming pulse voltages are then applied to selected memory cells within the memory blocks that need to be programmed in the four memory surfaces, thereby programming the memory cells. Optionally, programming pulse voltages can be applied to selected memory cells within the memory blocks that need to be programmed in the four memory surfaces simultaneously.

[0103] Step 302: In response to the target programming mode being a non-full-fledged programming mode, apply additional load to the storage surface where programming is performed under the target programming mode.

[0104] The additional load is used to control the programming load balance between the target programming mode and the full programming mode.

[0105] Since the workload of AP programming mode is higher than that of any of the SP, DP, and QP programming modes, the workload of SP, DP, and QP programming modes is brought closer to that of AP programming mode, thereby reducing the difference in programming efficiency between the various programming modes.

[0106] The methods for applying additional load include at least one of the following:

[0107] 1. Connect the storage surface where programming is performed in the target programming mode to the specified load element, so that the specified load element provides additional load to the programming stage in the target programming mode;

[0108] 2. Perform the programming phase in the full programming mode on the memory, that is, perform the programming phase on all storage surfaces in the memory. In this phase, the storage surfaces that are programmed in the target programming mode are effectively programmed, while the other storage surfaces are invalidally programmed.

[0109] It is worth noting that the above-described methods of applying load are merely illustrative examples, and the embodiments of this application do not limit them.

[0110] In summary, the method provided in this embodiment reduces the programming efficiency differences between the programming stages in the target programming mode and the full programming mode by applying additional load to the target programming stage. This includes reducing differences in programming duration and margin. On one hand, when the programming efficiency differences between the various programming modes are small, each programming mode can share some parameters related to programming efficiency, such as the programming pulse width, thereby reducing the need for parameter debugging and the number of tests. On the other hand, since each programming mode can share some parameters related to programming efficiency, the space occupied by parameter storage is reduced.

[0111] The two methods of applying load described above will be explained in the following examples.

[0112] 1. Connect a specified load element to increase the load.

[0113] Figure 4 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application, the method being applied to a memory including multiple storage surfaces, such as... Figure 4 As shown above, Figure 3 Step 302 shown can also be implemented as step 3021:

[0114] Step 3021: In response to the target programming mode being a non-full-process programming mode, connect the storage surface for programming in the target programming mode to the specified load element.

[0115] The specified load element is used to provide additional load to the memory surface where programming is performed in the target programming mode. This additional load is used to control the programming load balance between the target programming mode and the full programming mode. Load balancing refers to situations where the difference between the programming load in the full programming mode and the programming load in the target programming mode is small or even negligible.

[0116] In some embodiments, the parameters of a specified load element connected to the memory surface for programming in the target programming mode are determined through testing, such as resistance and capacitance values. Illustratively, after connecting a candidate load element to the memory surface for programming in the target programming mode, programming is performed, and first programming data is obtained, such as programming duration data, programming rate data, pulse width data, verification duration data, and the final programming voltage data. Then, programming is performed on the memory in full programming mode, and second programming data is obtained. The target programming mode and full programming mode are used for the same test programming task. The first and second programming data are compared, and the parameters of the candidate load element are adaptively adjusted based on the comparison result until the difference between the first and second programming data is less than a difference threshold, thereby obtaining the specified load element.

[0117] Optionally, the specified load element includes at least one of a capacitor element and a resistor element. That is, the memory surface for programming in the target programming mode is connected to the specified capacitor element; and / or, the memory surface for programming in the target programming mode is connected to the specified resistor element.

[0118] In some embodiments, before the voltage is introduced into the selected word line, the voltage is first passed through a designated load element and output from the designated load element before being input into the selected word line as a programming pulse; or, after the voltage is introduced into the selected word line as a programming pulse, the output voltage is introduced into the designated load element; or, the voltage is loaded through the designated load element both before and after it is introduced into the selected word line.

[0119] Optionally, the storage surface and the specified load element can be connected in series or in parallel.

[0120] It is worth noting that the above-mentioned connection method between the storage surface and the specified load element is only an illustrative example, and the connection method of the specified load element is not limited in the embodiments of this application.

[0121] In some embodiments, because it is necessary to specify the load element to simulate the additional load of the full programming mode compared to the target programming mode, the element parameters of the specified load element need to be determined through testing in some embodiments. Taking the connection of the specified load element in SP programming mode as an example, optionally, candidate load elements are first connected in SP programming mode, and after connecting the candidate load elements, the SP programming process of SP programming mode is executed to obtain the first programming data of the programming process, and the programming process of AP programming mode is executed to obtain the second programming data of AP programming process. The first programming data and the second programming data are compared. If the first programming data and the second programming data do not meet the difference requirements, the candidate load element connected in SP programming mode is replaced, or the load capacity of the candidate load element is increased or decreased based on the originally connected candidate load element, until the first programming data generated by the candidate load element connected in SP programming mode meets the difference requirements with the second programming data generated in AP programming mode, such as: the difference rate is less than the difference threshold, and the candidate load element is determined as the specified load element.

[0122] It is worth noting that the aforementioned first or second programming data includes: programming duration data, programming rate data, pulse width data, verification duration data, and final programming voltage data, etc., and the embodiments of this application do not limit this.

[0123] In some embodiments, designated load elements connected in different programming modes can be reused. Illustratively, load element 1, load element 2, and load element 3 are connected in SP programming mode; load element 1 and load element 2 are connected in DP programming mode; and load element 1 is connected in QP programming mode.

[0124] When multiplexing specified load elements connected in different programming modes, the load parameters of a specified load element are determined by first testing the programming mode with fewer connected specified load elements. For example, the load parameters of load element 1 connected in QP programming mode are determined first. That is, after connecting candidate load elements in QP programming mode, the programming data generated after connecting candidate load elements is compared with the programming data in AP programming mode, thereby adjusting the candidate load elements connected in QP programming mode until load element 1 is determined. After determining load element 1 connected in QP programming mode, the load parameters of the load element in DP programming mode are determined. Here, load element 1 is controlled to be connected to the storage surface in DP programming mode, and the load parameters of load element 2 are determined while keeping the load parameters of load element 1 unchanged. After determining load element 1 and load element 2 connected in QP and DP programming modes, load element 3 connected in SP programming mode is determined. Here, load element 1 and load element 2 can both be connected to the storage surface where programming is performed in SP programming mode, or either one can be connected to the storage surface where programming is performed in SP programming mode. With the load parameters of load element 1 and load element 2 remaining unchanged, the load parameters of load element 3 are determined through testing. Therefore, in QP programming mode, after connecting load element 1, the difference rate of programming data between QP programming mode and AP programming mode is less than the difference threshold; in DP programming mode, after connecting load element 1 and load element 2, the difference rate of programming data between DP programming mode and AP programming mode is less than the difference threshold; in SP programming mode, after connecting load element 1, load element 2, and load element 3, the difference rate of programming data between SP programming mode and AP programming mode is less than the difference threshold.

[0125] Optionally, when connecting a specified load element to a storage surface that is programmed in the target programming mode, the specified load element is connected to the storage surface that is programmed in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection manner in which the connectivity state between the specified load element and the storage surface changes as required.

[0126] In some embodiments, during the testing of the memory, the memory surface being programmed in the target programming mode is connected to a specified load element based on the active connection method, and the programming process is executed to generate first programming test data; the memory surface being programmed in the target programming mode is disconnected from the specified load element based on the active connection method, and the programming process is executed to generate second programming test data; based on the data comparison relationship between the first programming test data and the second programming test data, the connection state of the specified load element with the memory surface being programmed in the target programming mode is determined.

[0127] Optionally, in response to the data performance corresponding to the first programming test data being better than the data performance corresponding to the second programming test data, it is determined that the specified load element is connected to the memory surface for programming in the target programming mode; in response to the data performance corresponding to the second programming test data being better than the data performance corresponding to the first programming test data, it is determined that the specified load element is disconnected from the memory surface for programming in the target programming mode. For example, if the programming time in the first programming test data is shorter than the programming time in the second programming test data, then the data performance corresponding to the first programming test data is better than the data performance corresponding to the second programming test data, and it is determined that the specified load element is connected to the memory surface for programming in the target programming mode.

[0128] In other words, it provides an option to connect to an additional load, so that during the testing process, the target programming modes with and without the additional load can be compared. For example, the SP programming mode with and without the additional load can be compared to avoid the SP programming mode with the additional load being significantly weaker in programming performance compared to the SP programming mode without the additional load.

[0129] In some embodiments, a circuit switch is set for a specified load element in the target programming mode. When the specified load element needs to be connected, the circuit switch is turned on, so that the storage surface for programming in the target programming mode is connected to the specified load element. When the specified load element does not need to be connected, the circuit switch is turned off, so that the storage surface for programming in the target programming mode performs programming operations in a circuit without additional load.

[0130] In some embodiments, the circuit switch of the specified load element is only used during memory development and testing. After the connection method of the specified load element for the memory surface is determined, the circuit switch remains on or off during subsequent applications.

[0131] In summary, the method provided in this embodiment reduces the difference in programming efficiency between the target programming mode and the full programming mode by applying additional load to the target programming process. This includes reducing differences in programming time and margin. On one hand, when the differences in programming efficiency between the various programming modes are small, each mode can share some parameters related to programming efficiency, thereby reducing the need for parameter debugging and the number of tests. On the other hand, since each programming mode can share some parameters related to programming efficiency, the space occupied by parameter storage is reduced.

[0132] The method provided in this embodiment provides an additional load during the programming process of the target programming mode by connecting a specified load element, such as a capacitor or a resistor. This reduces the difference in programming data between the target programming mode and the full programming mode, and the load addition method is simple and improves the load addition efficiency.

[0133] Second, implement a unified full-programming mode and invalidate programming on some storage planes.

[0134] Figure 5 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application, the method being applied to a memory including multiple storage surfaces, such as... Figure 5 As shown above, Figure 3 Step 302 shown can also be implemented as step 3022:

[0135] Step 3022: Perform the programming phase in the full programming mode, wherein invalid programming of the deselected storage blocks is performed on the other storage surfaces among the n storage surfaces, and valid programming of the selected storage blocks is performed on the storage surfaces that are programmed in the target programming mode.

[0136] Other storage surfaces refer to storage surfaces in the memory other than those used for programming in the target programming mode.

[0137] The memory comprises n storage surfaces, where n ≥ 2 and n is an integer. The target programming mode refers to a mode that programs a subset of the n storage surfaces.

[0138] To illustrate, let's take a memory with 6 storage surfaces as an example. The target programming mode can be any one of SP programming mode, DP programming mode, or QP programming mode.

[0139] That is, the memory is programmed in the full programming mode. In the target programming mode, the memory surface is programmed to effectively program the selected memory block, and the other memory surfaces in the n memory surfaces are programmed to invalidate the deselected memory block. The deselected memory block is the memory block selected for invalid programming in the n memory surfaces. The deselected memory block can be any memory block in the n memory surfaces, or it can be the memory block with the smallest data storage volume in the n memory surfaces. This embodiment does not limit this.

[0140] During the memory programming phase, programming is performed in a unified manner according to the full programming model, but the effective programming part and the ineffective programming part are adaptively selected according to the actual target programming model.

[0141] In illustrative terms, the AP programming mode is used to perform the programming phase in SP, DP, and QP programming modes. Taking SP programming mode as an example, the memory includes 6 memory surfaces. In SP programming mode, memory surface 1 is selected for programming operations. Then, AP programming mode is used to perform programming operations on the 6 memory surfaces. Specifically, valid programming is performed on the selected memory blocks in memory surface 1, and invalid programming is performed on the unselected memory blocks in the other memory surfaces.

[0142] Taking DP programming mode as an example, the memory includes 6 storage surfaces. In DP programming mode, storage surfaces 1 and 2 are selected to perform programming operations. In AP programming mode, programming operations are performed on the 6 storage surfaces in the memory. Specifically, valid programming is performed on the selected storage blocks in storage surfaces 1 and 2, and invalid programming is performed on the unselected storage blocks in the other storage surfaces.

[0143] Taking QP programming mode as an example, the memory includes 6 storage surfaces. In QP programming mode, storage surfaces 1, 2, 3 and 4 are selected to perform programming operations. In AP programming mode, programming operations are performed on the 6 storage surfaces in the memory. Specifically, valid programming is performed on the selected storage blocks in storage surfaces 1, 2, 3 and 4, and invalid programming is performed on the unselected storage blocks in the other storage surfaces.

[0144] Optionally, effective programming refers to writing programming data into the memory cells of the memory block according to the normal programming method. Taking data writing with a floating-gate field-effect transistor as an example, when writing data into the memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor so that electrons in the channel of the floating-gate field-effect transistor tunnel to the floating gate. Ineffective programming is mainly achieved by adjusting the voltage difference between the channel and the floating gate. By increasing the voltage applied to the floating gate, the voltage difference generated between the channel and the floating gate is reduced, so that electrons in the channel cannot tunnel to the memory cell, and thus the effective programming stage cannot be performed. In the embodiments of this application, for deselected memory blocks in other memory planes, when performing invalid programming on the memory cells in the deselected memory block, the voltage applied to the floating gate is first increased, such as increasing the floating gate voltage to 20 volts, so that a large voltage difference cannot be generated between the channel and the floating gate, that is, electrons in the channel cannot smoothly tunnel to the floating gate, thus completing the invalid programming of the deselected memory block, but allowing the voltage to pass through the memory plane where the deselected memory block is located.

[0145] In some embodiments, when programming using the ISPP programming method, after applying a programming pulse voltage to a selected memory cell in a selected memory block during each pulse cycle, a programming verification is required to determine whether the selected memory cell has reached the programming threshold voltage. However, in this embodiment, a programming verification voltage is applied to the selected memory block. This verification voltage is used to verify the programming stage of the selected memory block, thereby determining whether the selected memory block has reached the programming threshold voltage. The programming verification stage is omitted for deselected memory blocks during the programming process. That is, only selected memory blocks undergo verification after the programming pulse stage; deselected memory blocks do not undergo any verification process.

[0146] Optionally, during the programming process of the full programming mode in this embodiment, only the selected storage blocks are actually programmed, erased, or read.

[0147] Optionally, the deselected storage block participation is used only to provide additional load to the programming process of the target programming pattern during the programming process.

[0148] Optionally, whether the selected storage blocks participate in the programming process is optional. That is, if additional load is required, the programming process in AP programming mode is executed uniformly, and invalid programming is performed on the selected storage blocks; if no additional load is required, the programming process in target programming mode is executed directly.

[0149] When a programming pulse voltage is applied, the programming pulse voltage passes through each memory surface. In AP programming mode, each memory surface includes a selected memory block, and the selected memory cell in the selected memory block performs the programming process according to the programming pulse voltage. In other programming modes, some memory surfaces include a selected memory block, and the selected memory cell in the selected memory block performs the programming process according to the programming pulse voltage. Other memory surfaces do not include a selected memory block. That is, the memory blocks in other memory surfaces are deselected memory blocks, and the deselected memory blocks are invalidated by the programming pulse voltage.

[0150] In some embodiments, a circuit switch is provided for each storage surface. When an additional load is required, the circuit switch is turned on to enable the programming process in the full programming mode to be executed in the target programming mode, and the programming pulse voltage is applied to each storage surface. When no additional load is required, the circuit switch is turned off, so that the storage surface that is being programmed in the target programming mode performs the programming operation in a circuit without an additional load.

[0151] In some embodiments, after determining whether invalid programming using a full programming mode was employed during the programming process, the circuit switches of the storage surface are turned on or off in subsequent applications based on increased load requirements.

[0152] In summary, the method provided in this embodiment reduces the difference in programming efficiency between the target programming mode and the full programming mode by applying additional load to the target programming process. This includes reducing differences in programming time and margin. On one hand, when the differences in programming efficiency between the various programming modes are small, each mode can share some parameters related to programming efficiency, thereby reducing the need for parameter debugging and the number of tests. On the other hand, since each programming mode can share some parameters related to programming efficiency, the space occupied by parameter storage is reduced.

[0153] The method provided in this embodiment adopts a programming scheme of execution programming mode for target programming mode. The programming pulse voltage passes through each storage surface, but only the selected storage blocks in the storage surface of execution programming mode are validly programmed, while the unselected storage blocks in other storage surfaces are invalidally programmed. However, since there is a programming pulse voltage passing through, that is, a similar voltage trend exists in target programming mode as in full programming mode, thereby reducing the difference rate between programming data in target programming mode and execution programming mode.

[0154] In this application embodiment, the reduction of the difference between the target programming mode and the full programming mode is achieved by adjusting the load. In the above embodiment, the load is increased by connecting additional load elements and by performing invalid programming in the full programming mode. This application embodiment does not limit other load addition methods.

[0155] like Figure 6 and Figure 7 As shown, the programming differences between the target programming model and the full programming model are due to load imbalance.

[0156] First, such as Figure 6 As shown in the figure, graph 600 illustrates a comparison of programming voltages between SP programming mode and AP programming mode. In the initial programming pulse phase, the voltage of the selected word line in SP programming mode is first coupled in the second programming pulse phase, and then the voltage drops to the target voltage level, which is lower than the voltage of the selected word line in AP programming mode.

[0157] Regardless of the programming mode, the voltage regulator's ability to pull down the voltage is consistent. In SP programming mode, the word line load is less than that in AP programming mode. For the initial programming pulse phase, the memory string driver has a larger current capacity. Therefore, in SP programming mode, the word line voltage is more easily pulled down by the voltage regulator.

[0158] Secondly, as Figure 7As shown in the figure, graph 700 illustrates a comparison of programming voltages between SP programming mode and AP programming mode. In the third programming pulse phase, the voltage difference of the selected word line between SP programming mode and AP programming mode is about 0.4V, which may affect the effective pulse ratio.

[0159] The method provided in this application embodiment has small / minor differences in programming data between different programming modes. Since the differences in programming data between different programming modes are small, some programming data-related parameters can be shared, thus reducing the time spent on parameter adjustment and optimization, as well as the number of learning loops. In addition, it saves the space occupied by parameter storage.

[0160] Figure 8 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 8 As shown, the memory includes multiple storage surfaces 8010, wherein each storage surface includes peripheral circuitry 800 and a storage cell array 810;

[0161] The peripheral circuit 800 is used to write data to the memory cell array 810 and to read data from the memory cell array 810.

[0162] The peripheral circuitry 800 includes: a voltage generator 802, a page buffer / sensor amplifier 804, a column decoder / bit line (BL) driver 806, a row decoder / word line (WL) driver 808, a peripheral logic unit 812, a register 814, input / output circuitry 816, and a data bus 818. It should be understood that in some examples, it may also include... Figure 8 Additional peripheral circuitry not shown.

[0163] Page buffer / sensor amplifier 804 can be configured to read data from memory cell array 810 and program (write) data to memory cell array 810 according to control signals from peripheral logic unit 812. In one example, page buffer / sensor amplifier 804 can store a page of programming data (write data) to be programmed into a page of memory cell array 810. In another example, page buffer / sensor amplifier 804 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 804 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0164] The column decoder / bit line driver 806 can be configured to be controlled by the peripheral logic unit 812 and to select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 802.

[0165] The line decoder / word line driver 808 can be configured to be controlled by the peripheral logic unit 812 and to select / deselect blocks of the memory cell array 810 and select / deselect word lines of the blocks. The line decoder / word line driver 808 can also be configured to use word line voltages (V) generated from the voltage generator 802. WL The line decoder / word line driver 808 drives the word lines. In some embodiments, the line decoder / word line driver 808 can also select / deselect and drive the source select gate line and the drain select gate line. Illustratively, the line decoder / word line driver 808 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0166] Voltage generator 802 can be configured to be controlled by peripheral logic unit 812 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 810.

[0167] The peripheral logic unit 812 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit.

[0168] Register 814 can be coupled to peripheral logic unit 812 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 816 can be coupled to peripheral logic unit 812 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to peripheral logic unit 812, as well as to buffer status information received from peripheral logic unit 812 and relay it to the host. Input / output circuitry 816 can also be coupled to column decoder / bitline driver 806 via data bus 818 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 810.

[0169] It should be emphasized that the peripheral circuit 800 is configured to perform the memory programming method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0170] Figure 9 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 9 As shown, the storage system 900 includes: one or more memories 910, and,

[0171] A memory controller 920 is coupled to the memory 910 and configured to control the memory 910.

[0172] The storage system 900 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0173] Optionally, the storage system 900 may include a host and a storage subsystem, the storage subsystem having one or more memories 910 and a memory controller 920. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 910. Alternatively, the host may be configured to receive data from the memory 910. The memory 910 includes n storage surfaces, where n ≥ 2 and n is an integer, to implement different programming modes.

[0174] According to some implementations, the memory controller 920 is also coupled to a host. The memory controller 920 can manage data stored in the memory 910 and communicate with the host.

[0175] In some implementations, the memory controller 920 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0176] In some implementations, the memory controller 920 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0177] The memory controller 920 can be configured to control the operation of the memory 910, such as read, erase, and program operations. The memory controller 920 can also be configured to manage various functions relating to data stored or to be stored in the memory 910, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 920 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 910.

[0178] The memory controller 920 can also perform any other suitable functions, such as formatting the memory 910. The memory controller 920 can communicate with external devices according to a specific communication protocol.

[0179] The memory controller 920 and one or more memories 910 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 900 can be implemented and packaged into different types of end electronic products.

[0180] Schematic illustration: The memory controller 920 and a single memory 910 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0181] Schematic, the memory controller 920 and multiple memories 910 can be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0182] It is understood that the memory controller 920 can perform memory programming methods as provided in any embodiment of the present disclosure.

[0183] In an optional embodiment, the storage system further includes a designated load element for connecting to the storage surface where programming is performed in the target programming mode, providing additional load to the storage surface where programming is performed in the target programming mode, which is a non-full-scale programming mode. The additional load is used to control the programming load in the target programming mode to balance the programming load with that in the full-scale programming mode.

[0184] In an optional embodiment, the storage system includes:

[0185] One or more memories, each memory comprising n storage surfaces, where n ≥ 2 and n is an integer, and,

[0186] A memory controller coupled to and configured to control the memory, wherein the memory controller controls the memory to perform a full programming phase when programming is performed in a target programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed in the target programming mode, wherein the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode.

[0187] This application provides a control circuit that includes programmable logic circuitry and / or program instructions. The control circuit can be used to implement the memory programming method provided in the foregoing embodiments of this application.

[0188] Indicative, such as Figure 9 The memory 910 shown includes: a control circuit and n storage surfaces, where n ≥ 2 and n is an integer. Each storage surface includes a storage block, and each storage block includes a storage cell.

[0189] The control circuit is configured to determine the target programming mode corresponding to the programming task from a variety of programming modes, including a full programming mode and a non-full programming mode. The full programming mode refers to the mode of programming the n memory surfaces in the programming task, and the non-full programming mode refers to the mode of programming a portion of the n memory surfaces in the programming task.

[0190] The control circuit is configured to apply an additional load to the memory surface where programming is performed in the target programming mode in response to the target programming mode belonging to the non-full-scale programming mode. The additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

[0191] In an optional embodiment, the control circuit is configured to connect the storage surface for programming in the target programming mode to the designated load element.

[0192] In an optional embodiment, the control circuit is configured to connect the memory surface for programming in the target programming mode to a designated capacitor element; or,

[0193] The control circuit is configured to connect the storage surface for programming in the target programming mode to a designated resistive element.

[0194] In an optional embodiment, the control circuit is configured to connect the designated load element to the storage surface that performs programming in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection state between the designated load element and the storage surface that changes as needed.

[0195] In an optional embodiment, the control circuit is configured to, during the testing of the memory, connect the memory surface to be programmed in the target programming mode to the designated load element based on the active connection method, and execute the programming process to generate first programming test data;

[0196] The control circuit is configured to disconnect the storage surface that performs programming in the target programming mode from the designated load element based on the active connection method, and execute the programming process to generate second programming test data;

[0197] The control circuit is configured to determine the connection state of the specified load element with the storage surface for programming in the target programming mode based on the data comparison relationship between the first programming test data and the second programming test data.

[0198] In an optional embodiment, the control circuit is configured to determine that the specified load element is connected to the storage surface for programming in the target programming mode in response to the data performance corresponding to the first programming test data being better than the data performance corresponding to the second programming test data.

[0199] The control circuit is configured to determine, in response to the data performance corresponding to the second programming test data being better than the data performance corresponding to the first programming test data, that the designated load element is disconnected from the storage surface where programming is performed in the target programming mode.

[0200] In an optional embodiment, the control circuit is configured to perform a programming phase of the full programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among the n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed under the target programming mode, wherein the other memory surfaces are memory surfaces other than those that are programmed under the target programming mode.

[0201] In an optional embodiment, the control circuit is configured to apply a programming verification voltage to the selected memory block, the programming verification voltage being used to verify the programming stage of the selected memory block; wherein the programming verification stage is omitted during the programming process of the deselected memory block.

[0202] In an optional embodiment, the memory comprises a six-sided memory;

[0203] The non-comprehensive programming mode includes at least one of the following: single-sided programming mode, double-sided programming mode, and four-sided programming mode.

[0204] In summary, the memory provided in this embodiment reduces the difference in programming efficiency between the target programming mode and the full programming mode by applying an additional load to the target programming process. This includes reducing differences in programming time and read window margin. On one hand, when the differences in programming efficiency between the various programming modes are small, each programming mode can share some parameters related to programming efficiency, such as the programming pulse width, thereby reducing the need for parameter debugging and the number of tests. On the other hand, since each programming mode can share some parameters related to programming efficiency, the space occupied by parameter storage is reduced.

[0205] This application provides a computer-readable storage medium storing instructions that, when executed on a control circuit, implement the memory programming method provided in the foregoing embodiments of this application.

[0206] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0207] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0208] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for programming a memory, characterized in that, The memory includes n storage surfaces, where n ≥ 2 and n is an integer. The method includes: The target programming mode corresponding to the programming task is determined from multiple programming modes, including a full programming mode and a non-full programming mode. The full programming mode refers to the mode of programming the n storage surfaces in the programming task, and the non-full programming mode refers to the mode of programming a portion of the n storage surfaces in the programming task. In response to the target programming mode belonging to the non-full-scale programming mode, an additional load is applied to the storage surface where programming is performed in the target programming mode. This additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

2. The method according to claim 1, characterized in that, Applying additional load to the storage surface where programming is performed in the target programming mode includes: The storage surface that performs programming in the target programming mode is connected to a designated load element, which is used to provide the additional load to the storage surface that performs programming in the target programming mode.

3. The method according to claim 2, characterized in that, The step of connecting the storage surface for programming in the target programming mode to the specified load element includes: Connect the storage surface for programming in the target programming mode to the specified capacitor element; or, Connect the storage surface that performs programming in the target programming mode to the specified resistive element.

4. The method according to claim 2, characterized in that, The method further includes: The specified load element is connected to the storage surface that performs programming in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection state between the specified load element and the storage surface that changes according to the requirements of the programming task.

5. The method according to claim 4, characterized in that, The method further includes: During the testing of the memory, the memory surface for programming in the target programming mode is connected to the designated load element based on the active connection method, and the programming process is executed to generate the first programming test data; Based on the active connection method, the storage surface for programming in the target programming mode is disconnected from the designated load element, and the programming process is executed to generate second programming test data; Based on the data comparison relationship between the first programming test data and the second programming test data, the connection status of the specified load element with the storage surface for programming in the target programming mode is determined.

6. The method according to claim 5, characterized in that, The step of determining the connection status of the specified load element with the storage surface executing the programming in the target programming mode based on the data comparison relationship between the first programming test data and the second programming test data includes: In response to the fact that the data performance corresponding to the first programming test data is better than the data performance corresponding to the second programming test data, it is determined that the specified load element is connected to the storage surface for programming in the target programming mode; In response to the fact that the data performance corresponding to the second programming test data is better than the data performance corresponding to the first programming test data, it is determined that the specified load element is disconnected from the storage surface where programming is performed in the target programming mode.

7. The method according to claim 1, characterized in that, Applying additional load to the storage surface where programming is performed in the target programming mode includes: The programming phase of the full programming mode is executed, wherein invalid programming of the deselected memory blocks is performed on the other memory surfaces among the n memory surfaces, and the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode; Perform effective programming on the selected memory block for the memory surface that is being programmed under the target programming mode.

8. The method according to claim 7, characterized in that, The method further includes: During the verification phase, a programming verification voltage is applied to the selected memory block, which is used to verify the programming phase of the selected memory block; wherein, the verification phase is omitted during the programming process of the deselected memory block.

9. The method according to any one of claims 1 to 8, characterized in that, The memory includes a six-sided memory; The non-comprehensive programming mode includes at least one of the following: single-sided programming mode, double-sided programming mode, and four-sided programming mode.

10. A memory, characterized in that, The memory includes: a control circuit and n storage surfaces, where n ≥ 2 and n is an integer, and each storage surface includes a storage block; The control circuit is configured to determine the target programming mode corresponding to the programming task from a variety of programming modes, including a full programming mode and a non-full programming mode. The full programming mode refers to the mode of programming the n memory surfaces in the programming task, and the non-full programming mode refers to the mode of programming a portion of the n memory surfaces in the programming task. The control circuit is configured to apply an additional load to the memory surface where programming is performed in the target programming mode in response to the target programming mode belonging to the non-full-scale programming mode. The additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode.

11. The memory according to claim 10, characterized in that, The control circuit is configured to connect the storage surface that performs programming in the target programming mode to a designated load element.

12. The memory according to claim 11, characterized in that, The control circuit is configured to connect the storage surface for programming in the target programming mode to a designated capacitor element; or... The control circuit is configured to connect the storage surface for programming in the target programming mode to a designated resistive element.

13. The memory according to claim 11, characterized in that, The control circuit is configured to connect the specified load element to the storage surface that performs programming in the target programming mode in an active connection manner, wherein the active connection manner refers to the connection state between the specified load element and the storage surface that changes according to requirements.

14. The memory according to claim 13, characterized in that, The control circuit is configured to, during the testing of the memory, connect the memory surface to be programmed in the target programming mode to the designated load element based on the active connection method, and execute the programming process to generate first programming test data; The control circuit is configured to disconnect the storage surface that performs programming in the target programming mode from the designated load element based on the active connection method, and execute the programming process to generate second programming test data; The control circuit is configured to determine the connection state of the specified load element with the storage surface for programming in the target programming mode based on the data comparison relationship between the first programming test data and the second programming test data.

15. The memory according to claim 14, characterized in that, The control circuit is configured to determine that the specified load element is connected to the storage surface for programming in the target programming mode in response to the data performance corresponding to the first programming test data being better than the data performance corresponding to the second programming test data. The control circuit is configured to determine, in response to the data performance corresponding to the second programming test data being better than the data performance corresponding to the first programming test data, that the designated load element is disconnected from the storage surface where programming is performed in the target programming mode.

16. The memory according to claim 10, characterized in that, The control circuit is configured to execute the programming phase of the full programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among the n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed in the target programming mode, wherein the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode.

17. The memory according to claim 16, characterized in that, The control circuit is configured to apply a programming verification voltage to the selected memory block, the programming verification voltage being used to verify the programming process of the selected memory block; wherein, the programming verification stage is omitted during the programming process of the deselected memory block.

18. The memory according to any one of claims 10 to 17, characterized in that, The memory includes a six-sided memory; The non-comprehensive programming mode includes at least one of the following: single-sided programming mode, double-sided programming mode, and four-sided programming mode.

19. A storage system, characterized in that, The storage system includes: One or more memories, the memories comprising n memory surfaces, where n ≥ 2 and n is an integer, and, A load element is specified for connection to the storage surface where programming is performed in the target programming mode, and provides additional load to the storage surface where programming is performed in the target programming mode. The target programming mode is a non-full-scale programming mode, and the additional load is used to control the programming load in the target programming mode to balance the programming load in the full-scale programming mode. A memory controller coupled to the memory and configured to control the memory.

20. A storage system, characterized in that, The storage system includes: One or more memories, the memories comprising n memory surfaces, where n ≥ 2 and n is an integer, and, A memory controller coupled to and configured to control the memory, wherein the memory controller is configured to control the memory to perform a full programming phase when programming is performed in a target programming mode, wherein invalid programming of deselected memory blocks is performed on other memory surfaces among n memory surfaces, and valid programming of selected memory blocks is performed on the memory surfaces that are programmed in the target programming mode, wherein the other memory surfaces are memory surfaces other than the memory surfaces that are programmed in the target programming mode.

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