Test circuit and method for memory

Abstract

The present disclosure provides a test circuit and method for memory. The test circuit comprises: a first data line read-write detection circuit, configured to read first read-out data in a first line, obtain first write-in data written into the first line, and detect the first read-out data according to the first write-in data to obtain a first detection result of the first read-out data; a first data line failure bit counting circuit, configured to obtain a first bit counting result of the first read-out data in which detection fails; a second data line read-write detection circuit, configured to read second read-out data in a second line, obtain second write-in data written into the second line, and detect the second read-out data according to the second write-in data to obtain a second detection result of the second read-out data; a second data line failure bit counting circuit, configured to obtain a second bit counting result of the second read-out data in which detection fails; and a test result output circuit, configured to output a target test signal according to the first bit counting result and the second bit counting result.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit testing technology, and more specifically, to a test circuit and method for memory. Background Technology

[0002] In related technologies, testing equipment can be used to test for single-bit errors (SBITs) in memory. For example, a high-level output (H) indicates the presence of an SBIT. However, the SBIT obtained during testing is highly likely not a true SBIT; it could indicate a problem with multiple memory cells being tested simultaneously, rather than just one of them. This leads to a problem: test engineers need to provide a large number of SBIT memory cell addresses to the Engineering Failure Analysis (EFA), who then uses a Final Test (FT) machine to verify each SBIT individually. This results in high testing time costs and low accuracy and efficiency. Summary of the Invention

[0003] The purpose of this disclosure is to provide a test circuit and method for memory, which can at least reduce the testing time cost of memory and improve testing efficiency and accuracy to a certain extent.

[0004] This disclosure provides a test circuit for a memory, the memory including a storage array. The test circuit includes: a first data row read / write detection circuit, configured to read first read data from a first row in the storage array and acquire first write data written to the first row, and detect the first read data based on the first write data to obtain a first detection result of the first read data; a first data row failure bit counting circuit, connected to the first data row read / write detection circuit, configured to obtain a first bit count result of failed detection in the first read data based on the first detection result; a second data row read / write detection circuit, configured to read second read data from a second row in the storage array and acquire second write data written to the second row, and detect the second read data based on the second write data to obtain a second detection result of the second read data; a second data row failure bit counting circuit, connected to the second data row read / write detection circuit, configured to obtain a second bit count result of failed detection in the second read data based on the second detection result; and a test result output circuit, connected to the first data row failure bit counting circuit and the second data row failure bit counting circuit, configured to output a target test signal based on the first bit count result and the second bit count result.

[0005] This disclosure provides a testing method for a memory, the memory including a storage array. The method includes: reading first read data from a first row in the storage array and acquiring first write data written to the first row, and detecting the first read data based on the first write data to obtain a first detection result of the first read data; obtaining a first bit count result of failed detection in the first read data based on the first detection result; reading second read data from a second row in the storage array and acquiring second write data written to the second row, and detecting the second read data based on the second write data to obtain a second detection result of the second read data; obtaining a second bit count result of failed detection in the second read data based on the second detection result; and outputting a target test signal based on the first bit count result and the second bit count result.

[0006] This disclosure provides a test circuit and method for a memory in some embodiments. The test circuit includes a first data row read / write detection circuit, a first data row failure bit counting circuit, a second data row read / write detection circuit, a second data row failure bit counting circuit, and a test result output circuit. The first data row read / write detection circuit reads first read data from a first row in the memory array and acquires first write data written to the first row, and detects the first read data based on the first write data to obtain a first detection result for the first read data. The first data row failure bit counting circuit obtains a first bit count result for failed detections in the first read data based on the first detection result. The second data row... The read / write detection circuit reads the second read data from the second row of the storage array and obtains the second write data written to the second row. Based on the second write data, it detects the second read data to obtain a second detection result for the second read data. The second data row failure bit counting circuit obtains a second bit count result for the failed detection in the second read data based on the second detection result. The test result output circuit outputs a target test signal based on the first bit count result and the second bit count result. This allows for row-by-row detection of the first bit count result and the second bit count effect in the storage array, thereby improving the accuracy of the output target test signal, thus increasing test efficiency and reducing test time. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a test circuit for a memory according to an exemplary embodiment of this disclosure.

[0008] Figure 2 This is a schematic diagram of a test circuit for a memory according to another exemplary embodiment of this disclosure.

[0009] Figure 3 This is a schematic diagram of a test circuit for a memory in yet another exemplary embodiment of this disclosure.

[0010] Figure 4 This is a schematic diagram of the data in the first to fourth rows of the storage array in an exemplary embodiment of this disclosure.

[0011] Figure 5 This is a schematic diagram of a test circuit for a memory according to yet another exemplary embodiment of this disclosure.

[0012] Figure 6 This is a schematic diagram of a test circuit for a memory in test mode according to another exemplary embodiment of this disclosure.

[0013] Figure 7 This is a schematic diagram of a test circuit for a memory in an address compression read / write mode, as described in yet another exemplary embodiment of this disclosure.

[0014] Figure 8 This is a schematic diagram of a test circuit for a memory in test mode according to another exemplary embodiment of this disclosure.

[0015] Figure 9 This is a schematic diagram of a test circuit for a memory in an address compression read / write mode, as described in yet another exemplary embodiment of this disclosure.

[0016] Figure 10 This is a flowchart of a testing method for a memory according to an exemplary embodiment of this disclosure. Detailed Implementation

[0017] The accompanying drawings are merely illustrative of this disclosure; the same reference numerals denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0018] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of a test circuit for a memory according to an exemplary embodiment of this disclosure.

[0020] like Figure 1As shown, this embodiment of the disclosure provides a test circuit 200 for a memory 100, which may include a memory array 110. The test circuit 200 may include: a first data row read / write detection circuit 210, a first data row failure bit counting circuit 220, a second data row read / write detection circuit 230, a second data row failure bit counting circuit 240, and a test result output circuit 250.

[0021] The memory 110 in this embodiment can be any storage device. In the following embodiments, DRAM (Dynamic Random Access Memory) is used as an example, but this disclosure is not limited thereto.

[0022] The first data row read / write detection circuit 210 can be used to read the first read data (e.g., DQ0, but this disclosure is not limited thereto) in the first row of the storage array 110 and to obtain the first write data (e.g., D0, but this disclosure is not limited thereto) written to the first row, and to detect the first read data based on the first write data to obtain the first detection result DT0 of the first read data.

[0023] In this embodiment of the disclosure, the storage array 110 may include multiple rows (more than or equal to 2 rows), and each row may include multiple storage cells. The first row may be any one or more rows in the storage array 110.

[0024] In this embodiment of the disclosure, "written data" refers to data written to the storage cells in the storage array. Simultaneously with the writing process, the data can be stored in latching units. When reading data from a storage cell, the written data and the read data can be compared to determine which storage cell(s) have inconsistent read data. If the read data is inconsistent with the written data, the storage cell is considered to have failed the detection; otherwise, if they are consistent, the storage cell is considered to have passed the detection. The first written data refers to data written to the storage cells in the first row, and the second written data refers to data written to the storage cells in the second row.

[0025] The first data line failure bit counting circuit 220 can be connected to the first data line read / write detection circuit 210, and can be used to obtain the first bit count result DC0 of the first read data DQ0 that failed detection based on the first detection result DT0.

[0026] The second data row read / write detection circuit 230 can be used to read the second read data (e.g., DQ1, but this disclosure is not limited thereto) in the second row of the storage array 110 and to obtain the second write data (e.g., D1, but this disclosure is not limited thereto) written in the second row, and to detect the second read data according to the second write data D1 to obtain the second detection result DT1 of the second read data.

[0027] In this embodiment of the disclosure, the second row can be any one or more rows in the storage array 110, and the first row and the second row are different rows.

[0028] The second data line failure bit counting circuit 240 can be connected to the second data line read / write detection circuit 230, and can be used to obtain the second bit count result DC1 of the failed detection in the second read data according to the second detection result DT1.

[0029] The test result output circuit 250 can be connected to the first data line failure bit counting circuit 220 and the second data line failure bit counting circuit 240, and can be used to output the target test signal Tout based on the first bit counting result DC0 and the second bit counting result DC1.

[0030] It is understood that although the embodiments of this disclosure use the first bit count result DC0 to accumulate the number of storage units that failed to be detected in the first read data and the second bit count result DC1 to accumulate the number of storage units that failed to be detected in the second read data, this disclosure is not limited to this. Those skilled in the art can also calculate the number of storage units that failed to be detected by accumulating the number of storage units that passed to be detected in the first read data and the number of storage units that passed to be detected in the second read data, based on the inventive concept of this disclosure. This calculation also falls within the protection scope of this disclosure.

[0031] The present disclosure provides a test circuit for a memory, which includes a first data row read / write detection circuit, a first data row failure bit counting circuit, a second data row read / write detection circuit, a second data row failure bit counting circuit, and a test result output circuit. The first data row read / write detection circuit reads first read data from a first row in the memory array and acquires first write data written to the first row, and detects the first read data based on the first write data to obtain a first detection result for the first read data. The first data row failure bit counting circuit obtains a first bit count result for failed read data based on the first detection result. The second data row read / write detection circuit... The read / write detection circuit reads the second read data from the second row of the storage array and obtains the second write data written to the second row. Based on the second write data, it detects the second read data to obtain the second detection result of the second read data. The second data row failure bit counting circuit obtains the second bit count result of the failed detection in the second read data based on the second detection result. The test result output circuit outputs the target test signal based on the first bit count result and the second bit count result. This allows for row-by-row detection of the first bit count result and the second bit count effect in the storage array, thereby improving the accuracy of the output target test signal, thus increasing test efficiency and reducing test time.

[0032] In an exemplary embodiment, the first row may include m columns, where m can be a positive integer greater than or equal to 1. The first read data DQ0 may include m bits of first read sub-data from the m columns in the first row. The first write data D0 may include m bits of first write sub-data from the m columns in the first row; the first detection result DT0 may include m bits of first detection result.

[0033] In an exemplary embodiment, the first data row read / write detection circuit can also be used to compare the i-th bit of the first read sub-data and the i-th bit of the first write sub-data. When the i-th bit of the first read sub-data is the same as the i-th bit of the first write sub-data, the i-th bit of the first detection result in the first row is obtained as if the i-th bit of the first detection passed (Fail); when the i-th bit of the first read sub-data is different from the i-th bit of the first write sub-data, the i-th bit of the first detection result in the first row is obtained as if the i-th bit of the first detection failed (Pass). Here, i can be a positive integer greater than or equal to 1 and less than or equal to m.

[0034] In an exemplary embodiment, the second row may include m columns, where m can be a positive integer greater than or equal to 1. The second read data DQ1 may include m bits of second read sub-data from the m columns in the second row. The second write data D1 may include m bits of second write sub-data from the m columns in the second row; the second detection result DT1 may include m bits of second detection result.

[0035] In an exemplary embodiment, the second data row read / write detection circuit can also be used to compare the i-th bit of the second read sub-data and the i-th bit of the second write sub-data. When the i-th bit of the second read sub-data is the same as the i-th bit of the second write sub-data, the i-th bit of the second detection result in the second row is obtained as if the i-th bit of the second detection passed (Fail); when the i-th bit of the second read sub-data is different from the i-th bit of the second write sub-data, the i-th bit of the second detection result in the second row is obtained as if the i-th bit of the second detection failed (Pass). Here, i can be a positive integer greater than or equal to 1 and less than or equal to m.

[0036] In an exemplary embodiment, the first data row read / write detection circuit may include m first XOR gates, each of which may include a first input, a second input, and an output. The first input of the i-th first XOR gate may receive the i-th bit of first read sub-data, and the second input may receive the i-th bit of first write sub-data. The i-th first XOR gate is used to generate the i-th bit of first detection result based on the i-th bit of first read sub-data and the i-th bit of first write sub-data, and the output may be used to output the i-th bit of first detection result.

[0037] In an exemplary embodiment, the second data row read / write detection circuit may include m second XOR gates, each of which may include a first input, a second input, and an output. The first input of the i-th second XOR gate may receive the i-th bit of second read sub-data, and the second input may receive the i-th bit of second write sub-data. The i-th second XOR gate may be used to generate the i-th bit of second detection result based on the i-th bit of second read sub-data and the i-th bit of second write sub-data, and the output may be used to output the i-th bit of second detection result.

[0038] In an exemplary embodiment, the first data row failure bit counting circuit may include m input terminals and an output terminal; the i-th input terminal may receive the i-th bit first detection result; the first data row failure bit counting circuit may be used to obtain the first bit count result in the m-bit first readout sub-data where the first detection result is a detection failure based on the m-bit first detection result; the output terminal may be used to output the first bit count result.

[0039] In an exemplary embodiment, if m = 2 k If k can be a positive integer greater than or equal to 1, then the first data row failure bit counting circuit may include a first k-bit adder. The first k-bit adder may include m input terminals and an output terminal. The i-th input terminal can receive the i-th bit of the first detection result. The first k-bit adder can be used to obtain the first bit count result in the m-bit first read sub-data where the first detection result is a failure, based on the m-bit first detection result. The output terminal can be used to output the first bit count result.

[0040] In an exemplary embodiment, the second data row failure bit counting circuit may include m input terminals and an output terminal; the i-th input terminal may receive the i-th bit second detection result; the second data row failure bit counting circuit may be used to obtain the second bit count result in which the second detection result in the m-bit second readout sub-data is a detection failure based on the m-bit second detection result; the output terminal may be used to output the second bit count result.

[0041] In an exemplary embodiment, if m = 2 k If k can be a positive integer greater than or equal to 1, then the second data row failure bit counting circuit may include a second k-bit adder. The second k-bit adder may include m input terminals and an output terminal. The i-th input terminal can receive the i-th bit of the second detection result. The second k-bit adder can be used to obtain the second bit count result of the second detection failure in the m-bit second readout sub-data based on the m-bit second detection result. The output terminal can be used to output the second bit count result.

[0042] In an exemplary embodiment, the test result output circuit may include an OR gate, which may include a first input terminal and an output terminal. The first input terminal of the OR gate may be connected to a first data row failure bit counting circuit, and the output terminal may be used to output a target test signal.

[0043] In an exemplary embodiment, the first data row failure bit counting circuit can also be used to output a first output signal in a first level state when the first bit count result is 1; and to output a first output signal in a second level state when the first bit count result is not 1; the first input terminal of the OR gate can receive the first output signal and can be used to obtain a target test signal for test failure when the first output signal is in the first level state.

[0044] In an exemplary embodiment, the test circuit may further include: a third data row read / write detection circuit, which can be used to read third read data from the third row in the storage array and acquire third write data written to the third row, and detect the third read data based on the third write data to obtain a third detection result of the third read data; and a third data row failure bit counting circuit, which can be connected to the third data row read / write detection circuit and can be used to obtain a third bit count result of failed detection in the third read data based on the third detection result. The test result output circuit can be connected to the third data row failure bit counting circuit and can be used to output a target test signal based on the first bit count result, the second bit count result, and the third bit count result.

[0045] In an exemplary embodiment, the third row may include m columns, where m can be a positive integer greater than or equal to 1. The third read data DQ2 may include m bits of third read sub-data from the m columns in the third row. The third write data D2 may include m bits of third write sub-data from the m columns in the third row; the third detection result DT2 may include m bits of third detection result.

[0046] In an exemplary embodiment, the third data row read / write detection circuit can also be used to compare the i-th bit of the third read sub-data and the i-th bit of the third write sub-data. When the i-th bit of the third read sub-data is the same as the i-th bit of the third write sub-data, the i-th bit of the third detection result in the third row is obtained as if the i-th bit of the detection passed (Fail); when the i-th bit of the third read sub-data is different from the i-th bit of the third write sub-data, the i-th bit of the third detection result in the third row is obtained as if the i-th bit of the detection failed (Pass). Here, i can be a positive integer greater than or equal to 1 and less than or equal to m.

[0047] In an exemplary embodiment, the third data row read / write detection circuit may include m third XOR gates, each of which may include a first input, a second input, and an output. The first input of the i-th third XOR gate may receive the i-th bit of third read sub-data, and the second input may receive the i-th bit of third write sub-data. The i-th third XOR gate is used to generate the i-th bit of third detection result based on the i-th bit of third read sub-data and the i-th bit of third write sub-data, and the output may be used to output the i-th bit of third detection result.

[0048] In an exemplary embodiment, the third data row failure bit counting circuit may include m input terminals and an output terminal; the i-th input terminal may receive the i-th bit third detection result; the third data row failure bit counting circuit may be used to obtain the third bit count result of the third detection result being a detection failure in the m-bit third readout sub-data based on the m-bit third detection result; the output terminal may be used to output the third bit count result.

[0049] In an exemplary embodiment, if m = 2 k If k can be a positive integer greater than or equal to 1, then the third data row failure bit counting circuit may include a third k-bit adder. The third k-bit adder may include m input terminals and output terminals. The i-th input terminal can receive the i-th bit of the third detection result. The third k-bit adder can be used to obtain the third bit count result of the m-bit third readout sub-data where the third detection result is a failure, based on the m-bit third detection result. The output terminal can be used to output the third bit count result.

[0050] In an exemplary embodiment, the test circuit may further include: a fourth data row read / write detection circuit, which can be used to read the fourth read data in the fourth row of the storage array and obtain the fourth write data written to the fourth row, and detect the fourth read data based on the fourth write data to obtain the fourth detection result of the fourth read data; and a fourth data row failure bit counting circuit, which can be connected to the fourth data row read / write detection circuit and can be used to obtain the fourth bit count result of the failed detection in the fourth read data based on the fourth detection result. The test result output circuit can be connected to the fourth data row failure bit counting circuit and can be used to output a target test signal based on the first bit count result, the second bit count result, the third bit count result, and the fourth bit count result.

[0051] In an exemplary embodiment, the fourth row may include m columns, where m can be a positive integer greater than or equal to 1. The fourth read data DQ3 may include m bits of fourth read sub-data from the m columns in the fourth row. The fourth write data D3 may include m bits of third write sub-data from the m columns in the fourth row; the fourth detection result DT3 may include m bits of fourth detection result.

[0052] In an exemplary embodiment, the fourth data row read / write detection circuit can also be used to compare the i-th bit of the fourth read sub-data and the i-th bit of the fourth write sub-data. When the i-th bit of the fourth read sub-data is the same as the i-th bit of the fourth write sub-data, the i-th bit of the fourth detection result in the fourth row is obtained as if the i-th bit of the detection passed (Fail); when the i-th bit of the fourth read sub-data is different from the i-th bit of the fourth write sub-data, the i-th bit of the fourth detection result in the fourth row is obtained as if the i-th bit of the detection failed (Pass). Here, i can be a positive integer greater than or equal to 1 and less than or equal to m.

[0053] In an exemplary embodiment, the fourth data row read / write detection circuit may include m fourth XOR gates, each of which may include a first input, a second input, and an output. The first input of the i-th fourth XOR gate may receive the i-th bit of fourth read sub-data, and the second input may receive the i-th bit of fourth write sub-data. The i-th fourth XOR gate may be used to generate the i-th bit of fourth detection result based on the i-th bit of fourth read sub-data and the i-th bit of fourth write sub-data, and the output may be used to output the i-th bit of fourth detection result.

[0054] In an exemplary embodiment, the fourth data row failure bit counting circuit may include m input terminals and an output terminal; the i-th input terminal may receive the i-th bit fourth detection result; the fourth data row failure bit counting circuit may be used to obtain the fourth bit count result of the fourth detection result being a detection failure in the m-bit fourth readout sub-data based on the m-bit fourth detection result; the output terminal may be used to output the fourth bit count result.

[0055] In an exemplary embodiment, if m = 2 k If k can be a positive integer greater than or equal to 1, then the fourth data row failure bit counting circuit may include a fourth k-bit adder. The fourth k-bit adder may include m input terminals and output terminals. The i-th input terminal can receive the i-th bit of the fourth detection result. The fourth k-bit adder can be used to obtain the fourth bit count result of the fourth detection failure in the m-bit fourth readout sub-data based on the m-bit fourth detection result. The output terminal can be used to output the fourth bit count result.

[0056] The following is combined Figure 2 An example of a test circuit for a memory provided in an embodiment of this disclosure will be given. Figure 2 In this embodiment, it is assumed that m = 8, and the test circuit simultaneously reads the first read data of the first row, the second read data of the second row, the third read data of the third row, and the fourth read data of the fourth row in the storage array. However, this disclosure is not limited to this, as long as m is a positive integer greater than or equal to 1, and the test circuit simultaneously reads data from at least two rows in the storage array.

[0057] like Figure 2 As shown, the test circuit 300 for the memory may include a first data row read / write detection circuit, a second data row read / write detection circuit, a third data row read / write detection circuit, and a fourth data row read / write detection circuit 310, as well as a first data row failure bit counting circuit (i.e., Figure 2 The DQ0 failure bit count circuit 320 and the second data line failure bit count circuit (i.e., the DQ1 failure bit count circuit) are mentioned. Figure 2 (not shown in the image), the third data line failure bit counter circuit (i.e., the DQ2 failure bit counter circuit), Figure 2 (not shown in the image) and the fourth data line failure bit counter circuit (i.e. Figure 2 The circuit includes the DQ3 failure bit counter circuit 350 and the test result output circuit 360.

[0058] Figure 2 In this embodiment, the first row may include 8 columns. The first read data DQ0 may include 8 bits of first read sub-data from the 8 columns in the first row. For example, the first to 8 bits of the first read sub-data from the 1st column in the first row are respectively columns Y0 to Y7 of the first read data DQ0. The first write data D0 may include 8 bits of first write sub-data from the 8 columns in the first row. For example, the first to 8 bits of the first write sub-data from the 1st column in the first row are respectively columns Y0 to Y7 of the first write data D0. The first detection result DT0 may include 8 bits of first detection result, for example... Figure 2 The first detection results shown are Y0DQ0, Y1DQ0, Y2DQ0, Y3DQ0, Y4DQ0, Y5DQ0, Y6DQ0, and Y7DQ0, representing bits 1 to 8.

[0059] Figure 2 In this embodiment, the first data row read / write detection circuit may include: eight first XOR gates, for example... Figure 2 XOR1 and XOR5 in Figure 2 (not shown in the image), XOR9 ( Figure 2 (not shown in the image), XOR13 ( Figure 2 (not shown in the image), XOR17 ( Figure 2 (not shown in the image), XOR21 ​​( Figure 2 (not shown in the image), XOR25 ( Figure 2 (not shown in the image) and XOR29, each first XOR gate may include a first input, a second input, and an output.

[0060] Specifically, the first input and second input of the first XOR gate XOR1 can receive the first bit of first read sub-data (i.e., column Y0 in DQ0) and the first bit of first write sub-data (i.e., column Y0 in D0) respectively. The first XOR gate XOR1 can be used to generate the first bit of first detection result Y0DQ0 based on the first bit of first read sub-data (i.e., column Y0 in DQ0) and the first bit of first write sub-data (i.e., column Y0 in D0), that is, when column Y0 in DQ0 is XORed with column Y0DQ0, the first detection result Y0DQ0 is generated. When the Y0 column in D0 is the same, Y0DQ0 is "0" (that is, the first bit of the first detection result Y0DQ0 in the first row is obtained if the first bit of the first detection is passed). When the Y0 column in DQ0 is different from the Y0 column in D0, Y0DQ0 is "1" (that is, the first bit of the first detection result Y0DQ0 in the first row is obtained if the first bit of the first detection is failed). The output of the first XOR gate XOR1 can be used to output the first bit of the first detection result Y0DQ0. The first and second inputs of the second first XOR gate XOR5 can receive the Y1 column in DQ0 and the Y1 column in D0, respectively. The second first XOR gate XOR5 can be used to generate the second bit of the first detection result Y1DQ0 based on the Y1 column in DQ0 and the Y1 column in D0. That is, when the Y1 column in DQ0 is the same as the Y1 column in D0, Y1DQ0 is "0" and when the Y1 column in DQ0 is different from the Y1 column in D0, Y1DQ0 is "1". The first and second inputs of the third first XOR gate XOR9 can receive the Y2 column in DQ0 and the Y2 column in D0, respectively. The third first XOR gate XOR9 can be used to generate the third bit first detection result Y2DQ0 based on the Y2 column in DQ0 and the Y2 column in D0. That is, when the Y2 column in DQ0 is the same as the Y2 column in D0, Y2DQ0 is "0" and when the Y2 column in DQ0 is different from the Y2 column in D0, Y2DQ0 is "1". The first and second inputs of the fourth first XOR gate XOR13 can receive the Y3 column in DQ0 and the Y3 column in D0, respectively. The fourth first XOR gate XOR13 can be used to generate the fourth bit first detection result Y3DQ0 based on the Y3 column in DQ0 and the Y3 column in D0. That is, when the Y3 column in DQ0 is the same as the Y3 column in D0, Y3DQ0 is "0" and when the Y3 column in DQ0 is different from the Y3 column in D0, Y3DQ0 is "1". The first and second inputs of the fifth first XOR gate XOR17 can receive the Y4 column in DQ0 and the Y4 column in D0, respectively. The fifth first XOR gate XOR17 can be used to generate the fifth bit first detection result Y4DQ0 based on the Y4 column in DQ0 and the Y4 column in D0. That is, when the Y4 column in DQ0 is the same as the Y4 column in D0, Y4DQ0 is "0" and when the Y4 column in DQ0 is different from the Y4 column in D0, Y4DQ0 is "1".The first and second inputs of the sixth first XOR gate XOR21 ​​can receive the Y5 column in DQ0 and the Y5 column in D0, respectively. The sixth first XOR gate XOR21 ​​can be used to generate the sixth bit first detection result Y5DQ0 based on the Y5 column in DQ0 and the Y5 column in D0. That is, when the Y5 column in DQ0 is the same as the Y5 column in D0, Y5DQ0 is "0" and when the Y5 column in DQ0 is different from the Y5 column in D0, Y5DQ0 is "1". The first and second inputs of the seventh first XOR gate XOR25 can receive the Y6 column in DQ0 and the Y6 column in D0, respectively. The seventh first XOR gate XOR25 can be used to generate the seventh bit first detection result Y6DQ0 based on the Y6 column in DQ0 and the Y6 column in D0. That is, when the Y6 column in DQ0 is the same as the Y6 column in D0, Y6DQ0 is "0" and when the Y6 column in DQ0 is different from the Y6 column in D0, Y6DQ0 is "1". The first and second inputs of the 8th first XOR gate XOR29 can receive the Y7 column in DQ0 and the Y7 column in D0, respectively. The 8th first XOR gate XOR29 can be used to generate the 8th bit first detection result Y7DQ0 based on the Y7 column in DQ0 and the Y7 column in D0. That is, when the Y7 column in DQ0 is the same as the Y7 column in D0, Y7DQ0 is "0" and when the Y7 column in DQ0 is different from the Y7 column in D0, Y7DQ0 is "1".

[0061] Figure 2In this embodiment, the DQ0 failure bit counting circuit 320 may include eight input terminals and one output terminal; the first input terminal of the DQ0 failure bit counting circuit 320 may be connected to the output terminal of the first first XOR gate XOR1, and the first input terminal of the DQ0 failure bit counting circuit 320 may receive the first bit of the first detection result Y0DQ0; the second input terminal of the DQ0 failure bit counting circuit 320 may be connected to the output terminal of the second first XOR gate XOR5, and the first input terminal of the DQ0 failure bit counting circuit 320 may receive the first bit of the first detection result Y0DQ0; Two input terminals can receive the second bit of the first detection result Y1DQ0; the third input terminal of the DQ0 failure bit counter circuit 320 can be connected to the output terminal of the third first XOR gate XOR9, and the third input terminal of the DQ0 failure bit counter circuit 320 can receive the third bit of the first detection result Y2DQ0; the fourth input terminal of the DQ0 failure bit counter circuit 320 can be connected to the output terminal of the fourth first XOR gate XOR13, and the fourth input terminal of the DQ0 failure bit counter circuit 320 can receive... The 4th bit of the first detection result is Y3DQ0; the 5th input of the DQ0 failure bit counter circuit 320 can be connected to the output of the 5th first XOR gate XOR17, and the 5th input of the DQ0 failure bit counter circuit 320 can receive the 5th bit of the first detection result Y4DQ0; the 6th input of the DQ0 failure bit counter circuit 320 can be connected to the output of the 6th first XOR gate XOR21, and the 6th input of the DQ0 failure bit counter circuit 320 can receive the 6th bit of the first detection result Y4DQ0. The result is Y5DQ0; the 7th input of the DQ0 failure bit counter circuit 320 can be connected to the output of the 7th first XOR gate XOR25, and the 7th input of the DQ0 failure bit counter circuit 320 can receive the 7th bit of the first detection result Y6DQ0; the 8th input of the DQ0 failure bit counter circuit 320 can be connected to the output of the 8th first XOR gate XOR29, and the 8th input of the DQ0 failure bit counter circuit 320 can receive the 1st bit of the first detection result Y7DQ0.

[0062] The DQ0 failure bit counting circuit 320 can be used to obtain the first bit count result (i.e., the number of "1" results in Y1DQ0, Y2DQ0, Y3DQ0, Y4DQ0, Y5DQ0, Y6DQ0, and Y7DQ0) of the first 8 bits of first read sub-data (i.e., columns Y0-Y7 in DQ0) where the first detection result is a failure, based on the 8-bit first detection result (i.e., Y1DQ0, Y2DQ0, Y3DQ0, Y4DQ0, Y5DQ0, Y6DQ0, and Y7DQ0). The output of the DQ0 failure bit counting circuit 320 can be used to output the first bit count result DC0.

[0063] Figure 2 In the example, 8 = 2 3Therefore, the DQ0 failure bit counting circuit 320 may include a first 3-bit adder. The first 3-bit adder may include 8 input terminals and an output terminal. The i-th input terminal can receive the i-th bit of the first detection result. The first 3-bit adder can be used to obtain the first bit count result DC0 of the first readout sub-data (i.e., columns Y0-Y7 in DQ0) where the first detection result is a failure, based on the 8-bit first detection results (i.e., Y1DQ0, Y2DQ0, Y3DQ0, Y4DQ0, Y5DQ0, Y6DQ0, and Y7DQ0). The output terminal can be used to output the first bit count result DC0.

[0064] Figure 2 In the embodiment, when the test result output circuit 360 includes an OR gate, the DQ0 failure bit counting circuit 320 can also be used to output a first output signal in a first level state (e.g., high level) when the first bit count result DC0 is 1 (i.e., a single bit error (SBIT) is detected from the 8 columns Y0 to Y7 of DQ0); and to output a first output signal in a second level state (e.g., low level) when the first bit count result is not 1 (i.e., a single bit error (SBIT) is not detected from the 8 columns Y0 to Y7 of DQ0). The first input terminal of the OR gate can receive the first output signal and can be used to obtain the target test signal of test failure when the first output signal is in the first level state.

[0065] Continue to refer to Figure 2 The second to fourth rows, the second to fourth read data DQ1-DQ3, the second to fourth write data D1-D3, the second to fourth detection results DT1-DT3, the second to fourth data row read / write detection circuit, the DQ1 to DQ3 failure bit counting circuit, and the second to fourth bit counting results DC1-DC3 can be referred to the first row, the first read data DQ0, the first write data D0, the first detection result DT0, the first data row read / write detection circuit, the DQ0 failure bit counting circuit, and the first bit counting result DC0, respectively.

[0066] Based on the above information, Figure 2 In this embodiment, when the test result output circuit 360 includes an OR gate, if at least one of the first, second, third, and fourth output signals from the DQ0, DQ1, DQ2, and DQ3 failure bit counter circuits is "1", then the Tout output by the test result output circuit 360 is Fail. If all of the first, second, third, and fourth output signals are "0", then the Tout output by the test result output circuit 360 is Pass.

[0067] The test circuit for memory provided in this embodiment can simultaneously test 32 bits of data (columns Y0 to Y7 in DQ0 to DQ3) using four failure bit counter circuits (i.e., failure bit counter circuits DQ0, DQ1, DQ2, and DQ3) to detect the SBIT in 8 bits of DQ0, 8 bits of DQ1, 8 bits of DQ2, and 8 bits of DQ3. A high-level Fail signal is sent only when at least one true SBIT exists in these four DQs, thereby improving the authenticity of the SBIT.

[0068] In an exemplary embodiment, the test result output circuit may include a NAND gate, which may include a first input terminal and an output terminal. The first input terminal of the NAND gate may be connected to a first data row failure bit counting circuit, and the output terminal may be used to output a target test signal.

[0069] In an exemplary embodiment, the first data row failure bit counting circuit can also be used to output a first output signal in a second level state when the first bit count result is 1; and to output a first output signal in a first level state when the first bit count result is not 1; the first input terminal of the NAND gate receives the first output signal and can be used to obtain a target test signal indicating test failure when the first output signal is in a second level state.

[0070] Figure 3 The test circuit 400 for memory provided in the embodiment may include a first data row read / write detection circuit, a second data row read / write detection circuit, a third data row read / write detection circuit, and a fourth data row read / write detection circuit 310, as well as a first data row failure bit counting circuit (i.e., Figure 3 The DQ0 failure bit count circuit 420 and the second data line failure bit count circuit (i.e., the DQ1 failure bit count circuit) are mentioned. Figure 3 (not shown in the image), the third data line failure bit counter circuit (i.e., the DQ2 failure bit counter circuit), Figure 3 (not shown in the image) and the fourth data line failure bit counter circuit (i.e. Figure 3 The circuit includes the DQ3 failure bit counter circuit 450 and the test result output circuit 460.

[0071] like Figure 3As shown, the test result output circuit 460 may include a NAND gate, which may include a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first, second, third, and fourth input terminals of the NAND gate are respectively connected to the output terminals of the DQ0 failure bit count circuit 420, the DQ1 failure bit count circuit, the DQ2 failure bit count circuit, and the DQ3 failure bit count circuit 450, so as to receive the first output signal, the second output signal, the third output signal, and the fourth output signal respectively output by the output terminals of the DQ0 failure bit count circuit 420, the DQ1 failure bit count circuit, the DQ2 failure bit count circuit, and the DQ3 failure bit count circuit 450.

[0072] Figure 3 In the embodiment, when the test result output circuit 460 includes a NAND gate, the DQ0 failure bit counting circuit 420 can also be used to output a first output signal in a second level state (e.g., low level, represented by "0") when the first bit count result is 1; and output a first output signal in a first level state (e.g., high level, represented by "1") when the first bit count result is not 1; the DQ1 failure bit counting circuit can also be used to output a second output signal in a second level state when the second bit count result is 1; and output a second output signal in a first level state when the first bit count result is not 1; the DQ2 failure bit counting circuit can also be used to output a third output signal in a second level state when the third bit count result is 1; and output a third output signal in a first level state when the third bit count result is not 1; the DQ3 failure bit counting circuit can also be used to output a fourth output signal in a second level state when the fourth bit count result is 1; and output a fourth output signal in a first level state when the fourth bit count result is not 1.

[0073] Figure 3In this embodiment, when the test result output circuit 460 includes a NAND gate, if at least one of the first, second, third, and fourth output signals from the DQ0 failure bit counting circuit 420, DQ1 failure bit counting circuit, DQ2 failure bit counting circuit, and DQ3 failure bit counting circuit 450 is "0", then the Tout output by the test result output circuit 460 is Fail (a high level can represent Fail, but this disclosure is not limited to this; a low level can also represent Fail in other embodiments). When all four output signals are "1", the Tout output by the test result output circuit 460 is Pass (a low level can represent Fail, but this disclosure is not limited to this; a high level can also represent Fail in other embodiments).

[0074] Figure 3 Other aspects of the embodiments can be found above. Figure 2 Example.

[0075] The test circuit for memory provided in this embodiment can use either an OR gate or a NAND gate to output the test result. When using a NAND gate, the high and low levels of the output signals of each failure bit counting circuit can be adaptively changed, thereby improving the flexibility of circuit design.

[0076] In an exemplary embodiment, the first write data, the second write data, the third write data, and the fourth write data in the same column of the first to fourth rows can be the same.

[0077] For example, such as Figure 4 As shown, columns Y7 of DQ0 to DQ3 are all written with "0", Y6 with "0", Y5 with "1", Y4 with "1", Y3 with "0", Y2 with "1", Y1 with "0", and Y0 with "0". Each column of DQ0 to DQ3 is called a burst. This embodiment uses a burst length of 8 bits as an example, but this disclosure is not limited to this. In other embodiments, a suitable burst length, such as 16 bits, can be selected according to actual needs.

[0078] It should be noted that in the above example, each fail counter has 8 bits for the corresponding DQ, but this disclosure is not limited to this. In other embodiments, for each burst DQ (taking DQ0 as an example), when performing the DQ0 fail counter, two or more bits can be selected as counting units (for example, the DQ0 fail counter can only receive two bits from columns Y0 and Y1 in DQ0). Only when there is an SBIT in these selected counting units, that is, when the DQ0 fail counter counts as 1, will a high level be output to the next test result output circuit. At this time, the fail is a true SBIT for DQ0.

[0079] It is understood that the above example illustrates one fail counter corresponding to one DQ, but this disclosure is not limited to this. In other embodiments, one fail counter can correspond to multiple DQs. For example, the DQ0 fail counter detects the true SBIT in DQ0 and DQ1, the DQ1 fail counter detects the true SBIT in DQ2 and DQ3, or even the DQ0 fail counter detects the true SBIT of some bits in DQ0 and DQ1, and the DQ1 fail counter detects the true SBIT of some bits in DQ0 and DQ1.

[0080] The test circuit for memory provided in this disclosure ensures that the data written to the same position in different DQs is the same, so that the data read out later can be compared with the data written later, thereby simplifying the test process and improving test efficiency.

[0081] In an exemplary embodiment, the test circuit may further include: an address compression detection circuit, which can be connected to the first data row read / write detection circuit and the second data row read / write detection circuit. The address compression detection circuit can be used to generate and output a target test signal to the test machine based on the first detection result and the second detection result when the test circuit is in address compression read / write mode; and to turn off the address compression detection circuit when the test circuit is in test mode, so that the test result output circuit outputs the target test signal to the test machine based on the first bit count result and the second bit count result.

[0082] like Figure 5 As shown, Figure 5 The test circuit 400 provided in the embodiment and Figure 2The difference in the test circuit 200 provided in the embodiment is that it may also include an address compression detection circuit 500. The address compression detection circuit 500 may include a first input terminal, a second input terminal, and an output terminal. The first input terminal of the address compression detection circuit 500 may be connected to the output terminal of the first data row read / write detection circuit 210 to receive the first detection result DT0; the second input terminal of the address compression detection circuit 500 may be connected to the output terminal of the second data row read / write detection circuit 230 to receive the second detection result DT1; and the output terminal of the address compression detection circuit 500 may be connected to the output terminal of the test circuit 400.

[0083] The address compression detection circuit 500 can be used to generate and output a target test signal Tout to the test machine based on the first detection result DT0 and the second detection result DT1 when the test circuit 400 is in address compression read / write mode (which can be represented as Para Mode); and to turn off the address compression detection circuit 500 when the test circuit 400 is in test mode (which can be represented as Test Mode), so that the test result output circuit 250 outputs the target test signal Tout to the test machine based on the first bit count result DC0 and the second bit count result DC1.

[0084] Figure 6 In the embodiment, when in Test Mode, the connection between the address compression detection circuit 610 and the first data line read / write detection circuit, the second data line read / write detection circuit, the third data line read / write detection circuit and the fourth data line read / write detection circuit 310 is turned off, and Tout is output through the OR gate included in the test result output circuit 360.

[0085] Figure 7In the embodiment, when in Para Mode, the test result output circuit 360 is turned off, or the connection between the DQ0 failure bit counting circuit 320 to the DQ3 failure bit counting circuit 350 and the test result output circuit 360 can also be turned off, or the connection between the first data line read / write detection circuit, the second data line read / write detection circuit, the third data line read / write detection circuit, and the fourth data line read / write detection circuit 310 and the DQ0 failure bit counting circuit 320 to the DQ3 failure bit counting circuit 350 can also be turned off. When the test result output circuit 360 includes an OR gate, the address compression detection circuit 610 can also include an OR gate. The OR gate in the address compression detection circuit 610 can include 32 input terminals and one output terminal. The 32 input terminals are respectively connected to the output terminals of XOR1 to XOR32 to receive Y0DQ0 to Y7DQ3. When at least one "1" exists among the 32 inputs Y0DQ0 to Y7DQ3, the output terminal of the OR gate in the address compression detection circuit 610 outputs a high level to represent the target test signal Tout (Fail, i.e., indicating that there is a single-bit error (SBIT) in columns Y0 to Y7 of the read 32 bits DQ0 to DQ3). When all 32 inputs Y0DQ0 to Y7DQ3 are "0", the output terminal of the OR gate in the address compression detection circuit 610 outputs a low level to represent the target test signal Tout (Pass, i.e., indicating that there is no single-bit error (SBIT) in columns Y0 to Y7 of the read 32 bits DQ0 to DQ3).

[0086] Figure 8 In the embodiment, when in Test Mode, the connection between the address compression detection circuit 610 and the first data line read / write detection circuit, the second data line read / write detection circuit, the third data line read / write detection circuit and the fourth data line read / write detection circuit 310 is turned off, and the NAND gate included in the test result output circuit 460 outputs Tout.

[0087] Figure 9In the embodiment, when in Para Mode, the test result output circuit 460 is turned off, or the connection between the DQ0 failure bit counting circuit 420 to the DQ3 failure bit counting circuit 450 and the test result output circuit 460 can also be turned off, or the connection between the first data line read / write detection circuit, the second data line read / write detection circuit, the third data line read / write detection circuit, and the fourth data line read / write detection circuit 310 and the DQ0 failure bit counting circuit 420 to the DQ3 failure bit counting circuit 450 can also be turned off. When the test result output circuit 460 includes a NAND gate, the address compression detection circuit 610 may include an OR gate. The OR gate in the address compression detection circuit 610 may include 32 inputs and one output. The 32 inputs are respectively connected to the outputs of XOR1 to XOR32 to receive Y0DQ0 to Y7DQ3. When at least one "1" exists among the 32 inputs Y0DQ0 to Y7DQ3, the output of the OR gate in the address compression detection circuit 610 outputs a high level to represent the target test signal Tout (Fail, i.e., indicating a single-bit error (SBIT) in columns Y0 to Y7 of the read 32 bits DQ0 to DQ3). When all 32 inputs Y0DQ0 to Y7DQ3 are "0", the output of the OR gate in the address compression detection circuit 610 outputs a low level to represent the target test signal Tout (Pass, i.e., indicating no single-bit error (SBIT) in columns Y0 to Y7 of the read 32 bits DQ0 to DQ3).

[0088] In an exemplary embodiment, the first row may be in the first subarray of the storage array, the second row may be in the second subarray of the storage array, the third row may be in the third subarray of the storage array, and the fourth row may be in the fourth subarray of the storage array.

[0089] Taking T2048 (a Para Mode) as an example, DRAM will only output a Fail signal to the tester when at least one of the four subarrays is a real SBIT, thus increasing the probability that a real SBIT exists in the compressed 32 bits.

[0090] The memory test circuit provided in this disclosure includes both Para Mode and Test Mode. In Test Mode, a fail counter circuit is added. When Test Mode is enabled, the data path of the address compression detection circuit no longer outputs a signal, and each fail counter circuit is enabled. Each fail counter circuit can be implemented using a 3-bit adder (including the first to fourth 3-bit adders mentioned above). When each fail counter circuit counts to 1, it outputs a high level (OR gate) or a low level (NAND gate) to the next-level test result output circuit; otherwise, it outputs a low level or a high level. This ensures that the tester receives a high level only when at least one of the four subarrays is a true SBIT, increasing the probability of obtaining a true SBIT. In Para Mode, 32 bits can be compressed simultaneously for testing, thereby improving test efficiency and reducing test costs.

[0091] Figure 10 This is a flowchart of a testing method for a memory according to an exemplary embodiment of this disclosure.

[0092] like Figure 10 As shown in the embodiments of this disclosure, a testing method for a memory is provided. The memory may include a storage array, and the method may include:

[0093] In step S1010, the first read data in the first row of the storage array is read and the first write data in the first row is obtained. The first read data is detected based on the first write data to obtain the first detection result of the first read data.

[0094] In step S1020, the count result of the first bit that failed to be detected in the first readout data is obtained based on the first detection result.

[0095] In step S1030, the second read data in the second row of the storage array is read and the second write data in the second row is obtained. The second read data is detected based on the second write data to obtain the second detection result of the second read data.

[0096] In step S1040, the count result of the second bit that failed to be detected in the second readout data is obtained based on the second detection result.

[0097] In step S1050, the target test signal is output based on the first bit count result and the second bit count result.

[0098] Figure 10 Other aspects of the embodiments can be found in the description of the embodiments above.

[0099] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A test circuit for a memory, characterized in that, The memory includes a storage array, and the test circuit includes: The first data row read / write detection circuit is used to read the first read data in the first row of the storage array and obtain the first write data written to the first row, and detect the first read data according to the first write data to obtain the first detection result of the first read data. The first data line failure bit counting circuit is connected to the first data line read / write detection circuit and is used to obtain the first bit count result of the first failed detection in the first read data according to the first detection result. The second data row read / write detection circuit is used to read the second read data in the second row of the storage array and obtain the second write data written to the second row, and detect the second read data according to the second write data to obtain the second detection result of the second read data; The second data line failure bit counting circuit is connected to the second data line read / write detection circuit and is used to obtain the second bit count result of the failed detection in the second read data according to the second detection result. The test result output circuit is connected to the first data line failure bit counting circuit and the second data line failure bit counting circuit, and is used to output the target test signal according to the first bit counting result and the second bit counting result. Also includes: The address compression detection circuit is connected to the first data line read / write detection circuit and the second data line read / write detection circuit. The address compression detection circuit is used to generate and output the target test signal to the test machine based on the first detection result and the second detection result when the test circuit is in the address compression read / write mode. When the test circuit is in test mode, the address compression detection circuit is turned off so that the test result output circuit outputs the target test signal to the test machine based on the first bit count result and the second bit count result.

2. The test circuit as described in claim 1, characterized in that, The first row includes m columns, where m is a positive integer greater than or equal to 1, and the first read data includes m bits of first read sub-data in the m columns of the first row; The first written data includes m bits of first written sub-data written in m columns of the first row; the first detection result includes m bits of first detection result; The first data row read / write detection circuit is also used to compare the first read sub-data of the i-th bit and the first write sub-data of the i-th bit. When the first read sub-data of the i-th bit is the same as the first write sub-data of the i-th bit, the first detection result of the i-th bit in the first row is obtained; when the first read sub-data of the i-th bit is different from the first write sub-data of the i-th bit, the first detection result of the i-th bit in the first row is obtained. i is a positive integer greater than or equal to 1 and less than or equal to m.

3. The test circuit as described in claim 2, characterized in that, The first data row read / write detection circuit includes: There are m first XOR gates, each of which includes a first input terminal, a second input terminal, and an output terminal; The first input of the i-th first XOR gate receives the i-th bit of the first read sub-data, the second input receives the i-th bit of the first write sub-data, the i-th first XOR gate is used to generate the i-th bit of the first detection result based on the i-th bit of the first read sub-data and the i-th bit of the first write sub-data, and the output is used to output the i-th bit of the first detection result.

4. The test circuit as described in claim 2, characterized in that, The first data line failure bit counting circuit includes m input terminals and output terminals; The i-th input receives the first detection result of the i-th bit; The first data line failure bit counting circuit is used to obtain the first bit count result in which the first detection result is a failure in the first m-bit first read sub-data based on the first m-bit first detection result; The output terminal is used to output the first bit count result.

5. The test circuit as described in claim 4, characterized in that, If m = 2k, and k is a positive integer greater than or equal to 1, then the first data row failure bit counting circuit includes a first k-bit adder; The first k-bit adder includes m input terminals and output terminals. The i-th input terminal receives the i-th bit of the first detection result. The first k-bit adder is used to obtain the first bit count result in the m-bit first readout sub-data where the first detection result is a detection failure based on the m-bit first detection result. The output terminal is used to output the first bit count result.

6. The test circuit as described in claim 1, characterized in that, The test result output circuit includes: An OR gate includes a first input terminal and an output terminal. The first input terminal of the OR gate is connected to the first data row failure bit counting circuit, and the output terminal is used to output the target test signal.

7. The test circuit as described in claim 6, characterized in that, The first data line failure bit counting circuit is also used to output a first output signal in a first level state when the first bit count result is 1; and to output a first output signal in a second level state when the first bit count result is not 1. The first input terminal of the OR gate receives the first output signal and is used to obtain the target test signal indicating a test failure when the first output signal is in the first level state.

8. The test circuit as described in claim 1, characterized in that, The test result output circuit includes: The NAND gate includes a first input terminal and an output terminal. The first input terminal of the NAND gate is connected to the first data row failure bit counting circuit, and the output terminal is used to output the target test signal.

9. The test circuit as described in claim 8, characterized in that, The first data line failure bit counting circuit is also used to output a first output signal in a second level state when the first bit count result is 1; and to output a first output signal in a first level state when the first bit count result is not 1. The first input terminal of the NAND gate receives the first output signal and is used to obtain the target test signal indicating a test failure when the first output signal is in the second level state.

10. The test circuit as described in claim 1, characterized in that, Also includes: The third data row read / write detection circuit is used to read the third read data in the third row of the storage array and obtain the third write data written in the third row, and detect the third read data according to the third write data to obtain the third detection result of the third read data. The third data line failure bit counting circuit is connected to the third data line read / write detection circuit and is used to obtain the third bit count result of the failed detection in the third read data based on the third detection result. The test result output circuit is connected to the third data line failure bit counting circuit and is used to output the target test signal based on the first bit counting result, the second bit counting result and the third bit counting result.

11. The test circuit as described in claim 10, characterized in that, Also includes: The fourth data row read / write detection circuit is used to read the fourth read data in the fourth row of the storage array and obtain the fourth write data written in the fourth row, and detect the fourth read data according to the fourth write data to obtain the fourth detection result of the fourth read data. The fourth data line failure bit counting circuit is connected to the fourth data line read / write detection circuit and is used to obtain the fourth bit count result of the failed detection in the fourth read data based on the fourth detection result. The test result output circuit is connected to the fourth data line failure bit counting circuit and is used to output the target test signal based on the first bit counting result, the second bit counting result, the third bit counting result, and the fourth bit counting result.

12. The test circuit as described in claim 11, characterized in that, The first row is located in the first subarray of the storage array, the second row is located in the second subarray of the storage array, the third row is located in the third subarray of the storage array, and the fourth row is located in the fourth subarray of the storage array.

13. The test circuit as described in claim 11, characterized in that, The first written data, the second written data, the third written data, and the fourth written data in the same column of the first row to the fourth row are the same.

14. A testing method for memory, characterized in that, The memory includes a storage array, and the method includes: Read the first read data from the first row in the storage array and obtain the first write data written to the first row, and detect the first read data based on the first write data to obtain the first detection result of the first read data; Based on the first detection result, obtain the first bit count result of the failed detection in the first read data; Read the second read data from the second row in the storage array and obtain the second write data written to the second row, and detect the second read data based on the second write data to obtain the second detection result of the second read data; Based on the second detection result, obtain the count result of the second bit that failed to be detected in the second readout data; Output the target test signal based on the first bit count result and the second bit count result; Also includes: When in address compression read / write mode, the target test signal is generated and output to the test machine based on the first detection result and the second detection result; When in test mode, the target test signal is output to the test machine based on the first bit count result and the second bit count result.

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