Test interface circuit

Abstract

The application provides a test interface circuit comprising N switches and N first resistors, wherein N is a positive integer. A first end of each of the N switches is coupled to each of N test connection terminals, and a second end of each of the N switches receives a reference voltage. Each of the N first resistors is coupled in series between each of the N test connection terminals and the reference voltage to each of the N switches. Wherein each of the N switches is controlled by each of N control signals to turn on or turn off.

Description

Technical Field

[0001] The present invention generally relates to a test interface circuit, and more specifically to a test interface circuit capable of adjusting the impedance between the tester and the device under test. Background Technology

[0002] In Double-Data-Rate Three-Synchronous Dynamic Random Access Memory (DDR3 SDRAM) products, the impedance matching requirements for the pins under test differ from other memory products. Therefore, during testing, conventional techniques require a specific design to provide an external circuit board to adjust the impedance of the DDR3 SDRAM pins. In other words, testing DDR3 SDRAM products incurs additional costs. Summary of the Invention

[0003] The present invention provides a test interface circuit for adjusting the impedance between each of the test channels of the tester and each of the pins of the device under test.

[0004] The test interface circuit includes N switches and N first resistors, where N is a positive integer. The first terminal of each of the N switches is coupled to each of the N test connection terminals, and the second terminal of each of the N switches receives a reference voltage. Each of the N first resistors is connected in series with each of the N test connection terminals and the reference voltage, and then coupled to each of the N switches. Each of the N switches is controlled by each of the N control signals to turn on or off.

[0005] In summary, the test interface circuit is positioned between the tester and the device under test (DUT) and is used to adjust the impedance between the tester's test channels and the pins of the DUT. By turning each switch on or off, the impedance between each test channel of the tester and each pin of the DUT can be adjusted, ensuring impedance matching requirements for each pin of the DUT. This allows for precise testing of the DUT.

[0006] To make the above content easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0008] Figure 1 A schematic diagram of a test interface circuit according to an embodiment of the present disclosure is shown;

[0009] Figure 2 A schematic diagram of a test interface circuit according to another embodiment of the present disclosure is shown;

[0010] Figure 3 A control signal generator for a test interface circuit according to an embodiment of the present disclosure is shown.

[0011] Explanation of icon numbers

[0012] 100, 200: Test interface circuit

[0013] 101: Tester

[0014] 102: Device under test

[0015] 300: Control signal generator

[0016] C21, C22, C23: Capacitors

[0017] CE1, CE2~CEN: Connection terminals

[0018] CH1~CHN: Test channels

[0019] CTS: Control Signal

[0020] GND: Reference ground voltage

[0021] IS: Input signal

[0022] JP: Jumper component

[0023] M1, M2, T1: Transistors

[0024] PIN1~PINN: Pins

[0025] R11, R12~R1N, R31, R32, R33, R34: Resistors

[0026] RT1~RTN: Terminating resistors

[0027] SW1, SW2~SWN: Switches

[0028] VPP: Operating voltage

[0029] VR, VR1~VRN: Reference voltage Detailed Implementation

[0030] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, examples of which are illustrated. The same reference numerals are used as far as possible in the drawings and description to refer to the same or similar parts.

[0031] Reference Figure 1 , Figure 1 A schematic diagram of a test interface circuit according to an embodiment of the present disclosure is shown. The test interface circuit 100 is coupled between a tester 101 and a device under test (DUT) 102. The test interface circuit 100 includes N resistors R11 to R1N and N switches SW1 to SWN. The N resistors R11 to R1N correspond to the N switches SW1 to SWN respectively. In this embodiment, resistor R11 and switch SW1 are connected in series between connection terminal CE1 and reference voltage VR1, and resistor R1N and switch SWN are connected in series between connection terminal CEN and reference voltage VRN. Connection terminal CE1 is used to connect the test channel CH1 of the tester 101 to pin PIN1 of the DUT 102, and connection terminal CEN is used to connect the test channel CHN of the tester 101 to pin PINN of the DUT 102. In this embodiment, the test interface circuit 100 may be disposed on a probe card, and the DUT 102 may be a chip.

[0032] In tester 101, test channel CH1 has a terminating resistor RT1, and test channel CHN has a terminating resistor RTN. The resistance of each of the terminating resistors RT1 to RTN can be 50 ohms. Each of the switches SW1 to SWN can be turned on or off to adjust the impedance between each of the pins PIN1 to PINN and each of the test channels CH1 to CHN. Taking switch SW1 and resistor R11 as an example: If switch SW1 is off, the impedance between pin PIN1 and test channel CH1 is dominated by terminating resistor RT1 and is substantially equal to 50 ohms. On the other hand, if switch SW1 is on, resistor R11 can be connected in parallel to terminating resistor RT1. If the resistance of resistor R11 is substantially equal to 50 ohms, the impedance between pin PIN1 and test channel CH1 can be adjusted to substantially equal to 25 ohms.

[0033] In other words, the impedance between each of the pins PIN1 to PINN and each of the test channels CH1 to CHN can be adjusted to meet the specifications of the device under test 102 by turning each of the switches SW1 to SWN on or off. For example, if the device under test 102 is a double data rate triple synchronous dynamic random access memory (DDR3 SDRAM), then each of the switches SW1 to SWN can be turned on to adjust the corresponding impedance to 25 ohms.

[0034] In this embodiment, the resistance of each of resistors R11 to R1N can be set to 50 ohms. Specifically, the resistance of each of resistors R11 to R1N may not be precisely equal to 50 ohms. In some embodiments, the resistance of each of resistors R11 to R1N may be substantially equal to 50 ohms with some manufacturing tolerances.

[0035] On the other hand, the reference voltages VR1 to VRN may have the same value. In this embodiment, each of the reference voltages VR1 to VRN may be equal to half the operating voltage of the device under test 102. In this embodiment, the reference voltages VR1 to VRN may be generated by a plurality of separate voltage sources. In some embodiments, the reference voltages VR1 to VRN may be generated by a single voltage source.

[0036] It should be noted that the number of switches SW1 to SWN and resistors R11 to R1N can be determined based on the number of pins of the device under test 102. If the device under test 102 has only one pin to be tested, then only one switch and its corresponding resistor are needed in the test interface circuit 100. If the device under test 102 has N pins to be tested, then both the number of switches SW1 to SWN and the number of resistors R11 to R1N in the test interface circuit 100 are N, where N is an integer greater than 1.

[0037] Reference Figure 2 , Figure 2 A schematic diagram of a test interface circuit according to another embodiment of the present disclosure is shown. The test interface circuit 200 includes resistors R1 and R2, switches SW1 and SW2, and capacitors C21 to C23. A first end of resistor R1 is coupled to a connection terminal CE1, and a second end of resistor R1 is coupled to a first end of switch SW1, the second end of which receives a reference voltage VR. A second end of resistor R2 is coupled to a connection terminal CE2, and a second end of switch SW2 is coupled to a first end of switch SW2, the second end of which also receives the reference voltage VR. Connection terminal CE1 is used to connect one test channel of the tester to a pin of the device under test, and connection terminal CE1 is used to connect another test channel of the tester to another pin of the device under test. In this embodiment, the resistance of each of resistors R11 and R12 may be substantially equal to 50 ohms.

[0038] Switch SW11 is a transistor switch formed by transistor M1. Switch SW12 is also a transistor switch formed by transistor M2. In this embodiment, transistors M1 and M2 can be P-type transistors. The first terminal of transistor M1 is coupled to the second terminal of resistor R11, the second terminal of transistor M1 receives a reference voltage VR, and the control terminal of transistor M1 receives a control signal CTS. The first terminal of transistor M2 is coupled to the second terminal of resistor R12, the second terminal of transistor M2 receives the reference voltage VR, and the control terminal of transistor M2 receives the control signal CTS. On the other hand, capacitor C23 is coupled between the control terminal of transistor M1 and the reference ground voltage GND. Capacitors C21 and C22 are connected in parallel and coupled between the second terminal of transistor M1 and the reference ground voltage GND. Capacitors C21 to C23 are all voltage-regulating capacitors.

[0039] In this embodiment, transistors M1 and M2 are controlled by the same control signal CTS. When the control signal CTS is at a low voltage value, transistors M1 and M2 can be turned on, and resistors R11 and R12 can be connected in parallel to the terminating resistors of the corresponding test channels. This allows adjustment of the impedance between each of the test channels of the tester and each pin of the device under test. Conversely, when the control signal CTS is at a high voltage value, transistors M1 and M2 can be turned off, and resistors R11 and R12 can be isolated from the test channels of the tester. The impedance between each of the test channels of the tester and each pin of the device under test can be equal to the resistance of each of the terminating resistors of the test channel.

[0040] In this embodiment, the reference voltage VR can be provided by the same voltage source. The resistance of each of resistors R11 and R12 can be substantially equal to 25 ohms.

[0041] In some embodiments, switches SW1 and SW2 may be implemented by N-type transistors. If switches SW1 and SW2 are implemented by N-type transistors, then switches SW1 and SW2 can be turned on if the control signal CTS is at a high voltage value, and switches SW1 and SW2 can be turned off if the control signal CTS is at a low voltage value. Of course, switches SW1 and SW2 may be implemented by any other electronic components (e.g., transmission gates) known to those skilled in the art.

[0042] The test interface circuit 200 can be mounted on a probe card. When performing a test operation on the device under test (DUT), the probe card can connect the DUT to the tester by probing multiple pins on the DUT. Furthermore, the tester can provide test modes to the DUT through the probe card, or measure test results from the DUT through the probe card.

[0043] In this embodiment, switches SW1 and SW2 can be controlled to adjust the impedance between the tester and the device under test (DUT). This satisfies the impedance matching requirements between the test channel of the tester and the pins of the DUT, allowing the tester to perform fast and accurate testing on the DUT.

[0044] Reference Figure 3 , Figure 3 A control signal generator for a test interface circuit according to an embodiment of the present disclosure is shown. The control signal generator 300 can be disposed on a probe card and can be coupled to, for example, Figure 2 The switches SW1 and SW2 are shown. The control signal generator 300 is used to generate a control signal CTS to control, for example... Figure 2 The switches SW1 and SW2 shown are used for control.

[0045] The control signal generator 300 includes resistors R31, R32, R33, and R34, and transistor T1. Resistors R31 and R32 are both pull-up resistors. The first terminal of resistor R31 receives the operating voltage VPP, and the second terminal of resistor R31 is coupled to the control terminal of transistor T1 through resistor R34. The first terminal of resistor R32 receives the operating voltage VPP, and the second terminal of resistor R32 is coupled to the first terminal of transistor T1. The second terminal of transistor T1 receives the reference ground voltage GND and is coupled to the control terminal of transistor T1 through resistor R33. That is, resistor R33 is coupled between the second terminal and the control terminal of transistor T1. Additionally, resistor R34 is coupled between the second terminal of resistor R31 and the control terminal of transistor T1. The control terminal of transistor T1 receives the input signal IS through resistor R34.

[0046] In this embodiment, the input signal IS can be provided by a tester. If the input signal IS is at a logic high level, transistor T1 can be turned on, and a control signal CTS equal to the reference ground voltage (with a low voltage value) can be generated by the control signal generator 300. On the other hand, if the input signal IS is at a logic low level, transistor T1 can be turned off, and a control signal CTS equal to the operating voltage (with a high voltage value) can be generated by the control signal generator 300. That is, the control signal generator 300 can generate the control signal CTS by inverting the input signal IS.

[0047] In this embodiment, transistor T1 can be a bipolar junction transistor (BJT). More specifically, transistor T1 can be an NPN type BJT, which can invert and amplify the input signal IS to generate a control signal CTS.

[0048] It should be noted that in this embodiment, a jumper element JP may be provided between one end of resistor R34 and the reference ground voltage GND. The jumper element JP provides a short-circuit path between resistor R34 and the reference ground voltage GND. If the jumper element JP is short-circuited, the voltage at the control terminal of transistor T1 can be forced to the reference ground voltage, regardless of the voltage value of the input signal IS. In this way, transistor T1 can be forcibly turned off. During normal operation, the jumper element JP remains open.

[0049] In one embodiment, the number of control signal generators 300 in the test interface circuit may be one. In this case, all switches in the test interface circuit can be controlled by the same control signal CTS. In another embodiment, the number of control signal generators 300 in the test interface circuit may be greater than one and may also be equal to the number of switches in the test interface circuit. In this case, each switch can be individually controlled by each of the control signal generators 300.

[0050] In summary, the test interface circuit of this disclosure provides at least one switch that determines whether to connect a resistor to the test channel of the tester. The test interface circuit is mounted on a probe card. This allows for adjustment of the impedance between the test channel and the pins of the device under test (DUT) to meet specifications and correspondingly improve test quality. Furthermore, since the test interface circuit is mounted on the probe card, the cost of testing the DUT can be saved.

[0051] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A test interface circuit, comprising: N switches, wherein the first terminal of each of the N switches is coupled to each of the N test connection terminals, the second terminal of each of the N switches receives a reference voltage, and N is a positive integer; N first resistors, wherein each of the N first resistors is coupled in series with each of the N test connections and the reference voltage to each of the N switches. Each of the N switches is controlled by each of the N control signals to be turned on or off; and N control signal generators are respectively coupled to the N switches to provide the N control signals. Each of the N control signal generators includes: The second resistor has a first terminal that receives the operating voltage; A third resistor has a first terminal that receives the operating voltage; A transistor having a first terminal coupled to a second terminal of a second resistor, a control terminal coupled to a second terminal of a third resistor, and a second terminal coupled to a reference ground terminal, wherein the control terminal of the transistor receives an input signal; and A fourth resistor is coupled between the control terminal and the second terminal of the transistor.

2. The test interface circuit according to claim 1, wherein each of the N test connection terminals is used to connect the pins of the device under test to the test channel of the tester.

3. The test interface circuit according to claim 2, wherein the reference voltage is half of the operating voltage of the device under test.

4. The test interface circuit of claim 2, wherein each of the N first resistors is configured to adjust the impedance between the pin of the device under test and the test channel of the tester.

5. The test interface circuit according to claim 1, wherein each of the N switches is a transistor switch.

6. The test interface circuit according to claim 1, wherein the resistance of each of the N first resistors is substantially equal to 50 ohms.

7. The test interface circuit according to claim 1, wherein each of the N control signal generators further comprises The fifth resistor is coupled to the path through which the transistor receives the input signal.

8. The test interface circuit according to claim 1, wherein the input signal is generated by the tester.

9. The test interface circuit according to claim 1, further comprising: At least one first capacitor is coupled between the second terminal of the N switches and the reference ground terminal.

10. The test interface circuit according to claim 9, further comprising: N second capacitors are respectively coupled between the N control terminals of the N switches and the reference ground terminal.

11. The test interface circuit according to claim 1, wherein the test interface circuit is disposed on the probe card.

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