A test circuit and method for DDR5

Abstract

The embodiment of the present application provides a test circuit and method for DDR5, the circuit comprises: a plurality of test points are connected with a test substrate through a adapter plate; the test substrate comprises a first switch module, a second switch module, a third switch module, a fourth switch module, an acquisition module, a first output module, a second output module and a control chip; each test point is connected with the first end of a first relay switch and the first end of a second relay switch respectively; the first relay switch is arranged in parallel between a device under test and a first switch, and the second relay switch is arranged in parallel between the device under test and a second switch; the second end of the first relay switch is connected with the first end of the first switch; the second end of the second relay switch is connected with the first end of the third switch; and the control chip is connected with the second output module, the first output module and the acquisition module. The present application can effectively improve the test efficiency.

Description

Technical Field

[0001] This invention relates to the field of DDR5 testing technology, and more particularly to a testing circuit and method for DDR5. Background Technology

[0002] DDR5 is the fifth generation of Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR5 SDRAM. Compared to DDR4, its biggest improvement is a significant speed increase.

[0003] With the increasing demand in the server and PC markets, the demand for DDR memory is also rising. To ensure product quality, most manufacturers conduct circuit testing on DDR memory after production. Current circuit testing methods are typically based on behavioral or logic testing of FPGAs or CPUs, making it impossible to pinpoint specific components. Furthermore, existing circuit testing methods are only suitable for testing DDR4 memory. With the advent of DDR5 memory, there is currently no relevant testing equipment or system to test DDR5 memory and confirm its proper functioning, resulting in significant potential quality risks for DDR products.

[0004] Therefore, existing circuit testing methods suffer from low testing efficiency. Summary of the Invention

[0005] This invention provides a test circuit and method for DDR5, aiming to solve the problem of low testing efficiency in existing circuit testing methods.

[0006] In a first aspect, embodiments of the present invention provide a test circuit for DDR5, comprising: a device under test (DUT), an adapter board, and a test substrate, wherein the DUT includes multiple test points, and the multiple test points are connected to the test substrate via the adapter board;

[0007] The test substrate includes a first switch module, a second switch module, a third switch module, a fourth switch module, a data acquisition module, a first output module, a second output module, and a control chip;

[0008] The end of each test point that is not connected to the device under test is connected to the first terminal of the first relay switch and the first terminal of the second relay switch, respectively.

[0009] The first relay switches are all connected in parallel between the device under test and the first switch module, and the second relay switches are all connected in parallel between the device under test and the second switch module;

[0010] The first switch module includes a first switch and a second switch;

[0011] The second switch module includes a third switch and a fourth switch;

[0012] The third switch module includes a fifth switch and a sixth switch;

[0013] The fourth switch module includes a seventh switch and an eighth switch;

[0014] The second terminals of the first relay switch are all connected to the first terminals of the first switch;

[0015] The second terminal of the second relay switch is connected to the first terminal of the third switch;

[0016] The first terminal of the control chip is connected to the second output module, the second terminal of the control chip is connected to the first output module, and the third terminal of the control chip is connected to the acquisition module.

[0017] Secondly, embodiments of the present invention provide a precise testing method for DDR5, applied to a control chip in the DDR5 testing circuit described in the first aspect above. The control chip is communicatively connected to both the acquisition module and the smart terminal, and includes:

[0018] According to the preset open and short circuit test strategy, open and short circuit tests are performed on each test point in sequence to obtain the open and short circuit test results corresponding to each test point, and the open and short circuit test results corresponding to each test point are sent to the smart terminal.

[0019] According to the preset high leakage voltage test strategy, the high leakage voltage test is performed on each test point in sequence to obtain the high leakage voltage test result corresponding to each test point, and the high leakage voltage test result corresponding to each test point is sent to the smart terminal.

[0020] According to the preset low leakage voltage test strategy, the low leakage voltage test is performed on each test point in sequence to obtain the low leakage voltage test result corresponding to each test point, and the low leakage voltage test result corresponding to each test point is sent to the smart terminal.

[0021] This invention provides a test circuit and method for DDR5. The circuit includes a device under test (DUT), an adapter board, and a test substrate. The DUT includes multiple test points, which are connected to the test substrate via the adapter board. The test substrate includes a first switch module, a second switch module, a third switch module, a fourth switch module, a data acquisition module, a first output module, a second output module, and a control chip. The end of each test point not connected to the DUT is connected to the first terminal of a first relay switch and the first terminal of a second relay switch, respectively. The first relay switches are all connected in parallel between the DUT and the first switch modules. Relay switches are connected in parallel between the device under test (DUT) and the second switch module. The first switch module includes a first switch and a second switch. The second switch module includes a third switch and a fourth switch. The third switch module includes a fifth switch and a sixth switch. The fourth switch module includes a seventh switch and an eighth switch. The second terminals of the first relay switches are all connected to the first terminals of the first switches. The second terminals of the second relay switches are all connected to the first terminals of the third switches. The first terminal of the control chip is connected to the second output module, the second terminal of the control chip is connected to the first output module, and the third terminal of the control chip is connected to the acquisition module. This invention enables precise testing of the DUT based on the test circuit, effectively improving testing efficiency and the accuracy of test results. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A first circuit diagram of a test circuit for DDR5 provided in an embodiment of the present invention;

[0024] Figure 2 A second circuit diagram of a test circuit for DDR5 provided in an embodiment of the present invention;

[0025] Figure 3 A third circuit diagram of a test circuit for DDR5 provided in an embodiment of the present invention;

[0026] Figure 4 This is a flowchart illustrating a precise testing method for DDR5 provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0031] Please see Figure 1 , Figure 1This is a first circuit diagram of a test circuit for DDR5 provided in an embodiment of the present invention. The embodiment of the present invention provides a test circuit 10 for DDR5, comprising: a device under test (DUT) 11, an adapter board 12, and a test substrate. The DUT 11 includes multiple test points, which are connected to the test substrate via the adapter board 12. The test substrate includes a first switch module K1, a second switch module K2, a third switch module K3, a fourth switch module K4, a data acquisition module 13, a first output module 14, a second output module 15, and a control chip 16. The end of each test point not connected to the DUT 11 is connected to the first terminal of a first relay switch and the first terminal of a second relay switch, respectively. The first relay switches are all connected in parallel between the DUT 11 and the first switch module K1. Two relay switches are connected in parallel between the device under test 11 and the second switch module K2; the first switch module K1 includes a first switch and a second switch; the second switch module K2 includes a third switch and a fourth switch; the third switch module K3 includes a fifth switch and a sixth switch; the fourth switch module K4 includes a seventh switch and an eighth switch; the second terminal of each of the first relay switches is connected to the first terminal of the first switch; the second terminal of each of the second relay switches is connected to the first terminal of the third switch; the first terminal of the control chip 16 is connected to the second output module 15, the second terminal of the control chip 16 is connected to the first output module 14, and the third terminal of the control chip 16 is connected to the acquisition module 13.

[0032] In this embodiment, the device under test 11 can be a DDR5 memory chip, namely, fifth-generation DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory); the device under test 11 includes 140 test points (the number of test points is not limited), namely TP1, TP2...TP140, and the multiple test points are connected to the test substrate through the adapter plate 12; TP1, TP2...TP140 are all connected to the test substrate through the adapter plate 12; the test substrate includes a first switch module K1, a second switch module K2, a third switch module K3, a fourth switch module K4, an acquisition module 13, a first output module 14, a second output module 15, and a control chip 16; based on the test circuit 10, the device under test 11 can be subjected to open / short circuit tests, high leakage voltage tests, or low leakage voltage tests to ensure the quality of the device under test 11. Each test point, except for the device under test (DUT) 11, is connected to the first terminal of the first relay switch and the first terminal of the second relay switch, respectively. For example, TP1 is connected to the first terminal of KA1 and the first terminal of KB1, respectively. The number of test points is equal to the number of first relay switches and the number of second relay switches. Accurate testing of the DUT can be achieved by controlling the first switch module K1, the second switch module K2, the third switch module K3, the fourth switch module K4, the first relay switch, and the second relay switch. The first terminal of the control chip 16 is connected to the second output module 15, the second terminal of the control chip 16 is connected to the first output module 14, and the third terminal of the control chip 16 is connected to the acquisition module 13. The first output module 14 and the second output module 15 supply power to the test circuit 10, and the control chip 16 can control the voltage / current output by the first output module 14 and the second output module 15.

[0033] In one embodiment, see Figure 1The second ends of the first relay switches are all connected to the first ends of the first switches; the second ends of the first switches are sequentially connected to the second contact of the first switch module K1, the fourth contact of the first switch module K1, and the second end of the second switch; the first end of the second switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the output end of the first output module 14 through the first contact of the third switch module K3; the second ends of the second relay switches are all connected to the first ends of the third switches; the second ends of the third switches are sequentially connected to the first contact of the second switch module K2, the third contact of the second switch module K2, and the second end of the fourth switch; the first end of the fourth switch is connected to the first end of the sixth switch, and the sixth switch... The second terminal of the switch is connected to the input terminal of the first output module 14 through the third contact of the third switch module K3; the second terminals of each of the first relay switches are connected in sequence, and their connection points serve as the first terminals of the relays; the second terminals of each of the second relay switches are connected in sequence, and their connection points serve as the second terminals of the relays; the first terminal of the acquisition module 13 is connected to the second terminal of the seventh switch, and the second terminal of the acquisition module 13 is connected to the second terminal of the eighth switch; the first terminal of the seventh switch is connected in sequence to the first contact of the fourth switch module K4 and the first terminal of the relay, and the first terminal of the eighth switch is connected in sequence to the third contact of the fourth switch module K4 and the second terminal of the relay; the second terminal of the control chip 16 is connected to the first output module 14.

[0034] In this embodiment, open-circuit and short-circuit tests can be performed sequentially at each test point by controlling the on / off state of the first relay switch and the second relay. For example... Figure 1As shown, the device under test 11 includes 140 test points (TP1, TP2...TP140). Test point TP1 is used as the target test point, and an open-circuit test is performed on the target test point. At this time, KA1 and KB2 to KB140 are in the closed state, and KB1 and KA2 to KA140 are in the open state. That is, except for PT1, all other test points (PT2 to PT140) are short-circuited. The current output by the first output module 14 passes through K1, K3, and KA1 to TP1 in sequence, and then returns to the input terminal of the first output module 14 after passing through TP2 to TP140. The acquisition module 13 acquires the voltage V1 across TP1 and TP2 to TP140, and sends the voltage V1 to the control chip 16. The control chip 16 obtains the open / short circuit test result regarding whether TP1 was successfully tested based on the voltage V1, and uploads the open / short circuit test result to the smart terminal 17. The smart terminal 17 establishes a communication connection with the control chip 16. Then, it determines whether there are any test points that have not undergone open / short circuit testing. If there are test points that have not undergone open / short circuit testing, the next test point is obtained as the target test point, and the process returns to perform the open / short circuit test on the target test point. If there are no test points that have not undergone open / short circuit testing, the smart terminal 17 integrates the open / short circuit test results to obtain a first test result. It then judges the first test result according to a preset first constraint condition to obtain a first result indicating whether the device under test (DUT) has passed the open / short circuit test. The first constraint condition can be set according to requirements. Specifically, it judges whether the pass rate of the first test result is 100%. If the pass rate of the first test result is 100%, then the device under test has passed the open / short circuit test. This embodiment of the invention can control the on / off state of the first relay switch and the second relay to sequentially perform open / short circuit tests on each test point, achieving precise positioning of the test points, effectively improving testing efficiency and the accuracy of test results, and ensuring the reliability of the DUT.

[0035] In one embodiment, see Figure 2The second terminals of the first relay switches are all connected to the first terminals of the first switches; the second terminals of the first switches are sequentially connected to the first contact of the first switch module K1, the test resistor Rs, the third contact of the first switch module K1, and the second terminal of the second switch; the first terminal of the second switch is connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is connected to the output terminal of the second output module 15 through the second contact of the third switch module K3; the second terminals of the second relay switches are all connected to the first terminals of the third switches; the second terminals of the third switches are sequentially connected to the first contact of the second switch module K2, the third contact of the second switch module K2, the test resistor Rs, the third contact of the second switch module K3, and the second terminal of the second relay switch. The contacts are connected to the second terminal of the fourth switch; the first terminal of the fourth switch is connected to the first terminal of the sixth switch, and the second terminal of the sixth switch is connected to the input terminal of the second output module 15 through the fourth contact of the third switch module K3; the first terminal of the acquisition module 13 is connected to the second terminal of the seventh switch, and the second terminal of the acquisition module 13 is connected to the second terminal of the eighth switch; the first terminal of the seventh switch is sequentially connected to the second contact of the fourth switch module K4, the test resistor Rs, the fourth contact of the fourth switch module K4, and the first terminal of the eighth switch; the first terminal of the control chip 16 is connected to the second output module 15.

[0036] In this embodiment, leakage voltage high tests can be performed sequentially at each test point by controlling the on / off state of the first relay switch and the second relay. For example... Figure 2As shown, the device under test 11 includes 140 test points (TP1, TP2...TP140). Test point TP1 is used as the target test point, and a high leakage voltage test is performed on the target test point. At this time, KA1 and KB2 to KB140 are in the closed state, and KB1 and KA2 to KA140 are in the open state. That is, except for PT1, all other test points (PT2 to PT140) are short-circuited. The second output module 15 is connected in series with the test resistor Rs through the first switch module K1. The current output by the second output module 15 flows through the test resistor Rs to TP1, and then returns to the input terminal of the second output module 15 after passing through TP2 to TP140. The acquisition module 13 acquires the voltage V2 across the test resistor Rs and sends the voltage V2 to the control chip 16. The control chip 16 obtains the leakage voltage high test result regarding whether TP1 was successfully tested according to the formula (I = V / Rs) and the voltage V2, and uploads the leakage voltage high test result to the smart terminal 17. Specifically, the leakage current I2 of test point TP1 is obtained according to the formula (I = V / Rs) and the voltage V2; it is determined whether the leakage current I2 is within the preset second current range. If the leakage current I2 is within the preset second current range, the leakage voltage high test result of test point TP1 is obtained; it is determined whether there is a test point that has not undergone leakage voltage high test; if there is a test point that has not undergone leakage voltage high test, the next test point is obtained as the target test point and the process of performing leakage voltage high test on the target test point is returned. If there are no test points where high leakage voltage testing has not been performed, the intelligent terminal 17 integrates all the high leakage voltage test results to obtain a second test result. It then judges the second test result according to a preset second constraint to determine whether the device under test (DUT) has passed the high leakage voltage test. The second constraint can be set according to requirements; specifically, it judges whether the pass rate of the second test result is greater than 70%. If the pass rate of the second test result is greater than 70%, then the device under test has passed the high leakage voltage test. This embodiment of the invention can control the on / off state of the first relay switch and the second relay to sequentially perform high leakage voltage testing on each test point, achieving precise positioning of the test points, effectively improving testing efficiency and the accuracy of test results, and ensuring the reliability of the DUT.

[0037] In one embodiment, see Figure 3The second terminals of the first relay switches are all connected to the first terminals of the first switches; the second terminals of the first switches are sequentially connected to the first contact of the first switch module K1, the test resistor Rs, the third contact of the first switch module K1, and the second terminal of the second switch; the first terminal of the second switch is connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is connected to the output terminal of the second output module 15 through the second contact of the third switch module K3; the second terminals of the second relay switches are all connected to the first terminals of the third switch; the second terminals of the third switch are sequentially connected to the second contact of the second switch module K2, the test resistor Rs, the second switch module K1, and the second terminal of the second switch module K1. The fourth contact of the 2 is connected to the second end of the fourth switch; the first end of the fourth switch is connected to the first end of the sixth switch, and the second end of the sixth switch is connected to the input end of the second output module 15 through the fourth contact of the third switch module K3; the first end of the acquisition module 13 is connected to the second end of the seventh switch, and the second end of the acquisition module 13 is connected to the second end of the eighth switch; the first end of the seventh switch is sequentially connected to the second contact of the fourth switch module K4, the test resistor Rs, the fourth contact of the fourth switch module K4, and the first end of the eighth switch; the first end of the control chip 16 is connected to the second output module 15.

[0038] In this embodiment, the leakage voltage low test can be performed sequentially at each test point by controlling the on / off state of the first relay switch and the second relay. For example... Figure 3As shown, the device under test 11 includes 140 test points (TP1, TP2...TP140). Test point TP1 is used as the target test point, and a low leakage voltage test is performed on the target test point. At this time, KB1, KA2~KA140 are in the closed state, and KA1, KB2~KB140 are in the open state. That is, except for PT1, the other test points (PT2~PT140) are short-circuited. Test point TP1 is connected in series with the test resistor Rs through the second switch module K2. The current output by the second output module 15 flows through TP2~TP140 and then to the test resistor Rs, and finally to the input terminal of the second output module 15. The acquisition module 13 acquires the voltage V3 across the test resistor Rs and sends the voltage V3 to the control chip 16. The control chip 16 obtains the leakage voltage low test result regarding whether TP1 was successfully tested according to the formula (I = V / Rs) and the voltage V3, and uploads the leakage voltage low test result to the smart terminal 17. Specifically, the leakage current I3 of test point TP1 is obtained according to the formula (I = V / Rs) and the voltage V3; it is determined whether the leakage current I3 is within the preset third current range. If the leakage current I3 is within the preset third current range, the leakage voltage low test result of test point TP1 is obtained; it is determined whether there is a test point that has not undergone leakage voltage low test; if there is a test point that has not undergone leakage voltage low test, the next test point is obtained as the target test point and the process of performing leakage voltage low test on the target test point is returned. If there are no test points where the low leakage voltage test has not been performed, the smart terminal 17 integrates all the low leakage voltage test results to obtain a third test result. It then judges the third test result according to a preset third constraint condition to determine whether the device under test (DUT) has passed the low leakage voltage test. The third constraint condition can be set according to requirements; specifically, it judges whether the pass rate of the third test result is greater than 70%. If the pass rate of the third test result is greater than 70%, then the device under test has passed the low leakage voltage test. This embodiment of the invention can control the on / off state of the first relay switch and the second relay to sequentially perform low leakage voltage tests on each test point, achieving precise positioning of the test points, effectively improving test efficiency and the accuracy of test results, and ensuring the reliability of the DUT.

[0039] See Figure 4 , Figure 4 This is a flowchart illustrating a precise testing method for DDR5 according to an embodiment of the present invention. The present invention provides a precise testing method for DDR5, applied to the control chip in the aforementioned DDR5 testing circuit. The precise testing method for DDR5 provided by the present invention includes steps S11 to S13.

[0040] S11. Perform open and short circuit tests on each test point in sequence according to the preset open and short circuit test strategy, obtain the open and short circuit test results corresponding to each test point, and send the open and short circuit test results corresponding to each test point to the smart terminal.

[0041] In this embodiment, based on the test circuit (see details...), Figure 1 The invention sequentially performs open-short circuit tests on each test point according to a preset open-short circuit test strategy, obtains open-short circuit test results corresponding to each test point, and sends the open-short circuit test results corresponding to each test point to the smart terminal, so that the smart terminal integrates the open-short circuit test results to obtain a first result of whether the device under test passes the open-short circuit test; the embodiment of the invention can sequentially perform open-short circuit tests on each test point, realize the precise positioning of the test points, effectively improve test efficiency and the accuracy of test results, and ensure the reliability of the device under test.

[0042] S12. Perform high leakage voltage tests on each test point sequentially according to the preset high leakage voltage test strategy, obtain the high leakage voltage test results corresponding to each test point, and send the high leakage voltage test results corresponding to each test point to the smart terminal.

[0043] In this embodiment, based on the test circuit (see details...), Figure 2 The present invention sequentially performs high leakage voltage tests on each test point according to a preset high leakage voltage test strategy, obtains high leakage voltage test results corresponding to each test point, and sends the high leakage voltage test results corresponding to each test point to the smart terminal, so that the smart terminal integrates the high leakage voltage test results to obtain a second result of whether the device under test passes the high leakage voltage test; the present invention can sequentially perform high leakage voltage tests on each test point, realize the precise positioning of the test points, effectively improve test efficiency and test result accuracy, and ensure the reliability of the device under test.

[0044] S13. Perform low leakage voltage tests on each test point sequentially according to the preset low leakage voltage test strategy, obtain the low leakage voltage test results corresponding to each test point, and send the low leakage voltage test results corresponding to each test point to the smart terminal.

[0045] In this embodiment, based on the test circuit (see details...), Figure 3The invention sequentially performs low leakage voltage tests on each test point according to a preset low leakage voltage test strategy, obtains low leakage voltage test results corresponding to each test point, and sends the low leakage voltage test results corresponding to each test point to the smart terminal, so that the smart terminal integrates the low leakage voltage test results to obtain a third result of whether the device under test passes the low leakage voltage test; the embodiment of the invention can sequentially perform low leakage voltage tests on each test point, realize precise positioning of test points, effectively improve test efficiency and accuracy of test results, and ensure the reliability of the device under test.

[0046] In one embodiment, see Figure 1 and Figure 4 Step S11 includes:

[0047] Obtain a test point as the target test point; perform open / short circuit testing on the target test point to obtain the target open / short circuit test result; determine whether the target open / short circuit test result is within the open / short circuit test range of the open / short circuit test strategy, and obtain the open / short circuit test result indicating whether the test was successful; determine whether there are any test points that have not undergone open / short circuit testing; if there are test points that have not undergone open / short circuit testing, obtain the next test point as the target test point and return to execute the step of performing open / short circuit testing on the target test point.

[0048] In this embodiment, a test point is acquired as a target test point; an open-short circuit test is performed on the target test point, the control chip acquires the voltage V1 acquired by the acquisition module, and obtains the target open-short circuit test result based on the acquired voltage V1; it is determined whether the target open-short circuit test result is within the open-short circuit test range in the open-short circuit test strategy, and the open-short circuit test result of whether the target test point was successfully tested is obtained; it is determined whether there are any test points that have not undergone open-short circuit testing; if there are any test points that have not undergone open-short circuit testing, the next test point is acquired as the target test point and the process returns to perform the open-short circuit test on the target test point.

[0049] In one embodiment, see Figure 2 and Figure 4 Step S12 includes:

[0050] A test point is selected as the target test point; a high leakage voltage test is performed on the target test point to obtain the target high leakage voltage test result; it is determined whether the target high leakage voltage test result is within the high leakage voltage test range in the high leakage voltage test strategy, and a high leakage voltage test result indicating whether the test was successful is obtained; it is determined whether there are any test points that have not undergone high leakage voltage testing; if there are test points that have not undergone high leakage voltage testing, the next test point is selected as the target test point and the process returns to perform the high leakage voltage test on the target test point.

[0051] In this embodiment, a test point is acquired as the target test point; a high leakage voltage test is performed on the target test point. The control chip acquires the voltage V2 acquired by the acquisition module, and obtains the leakage current I2 of the target test point according to the formula (I = V / Rs) and the acquired voltage V2, where Rs is a known resistance; the leakage current I2 of the target test point is used as the target high leakage voltage test result; it is determined whether the target high leakage voltage test result is within the high leakage voltage test range in the high leakage voltage test strategy, and the high leakage voltage test result of whether the target test point was successfully tested is obtained; it is determined whether there are any test points that have not undergone high leakage voltage testing; if there are any test points that have not undergone high leakage voltage testing, the next test point is acquired as the target test point and the process returns to execute the step of performing high leakage voltage testing on the target test point.

[0052] In one embodiment, see Figure 3 and Figure 4 Step S13 includes:

[0053] A test point is selected as the target test point; a low leakage voltage test is performed on the target test point to obtain the target low leakage voltage test result; it is determined whether the target low leakage voltage test result is within the low leakage voltage test range in the low leakage voltage test strategy, and a low leakage voltage test result indicating whether the test was successful is obtained; it is determined whether there are any test points that have not undergone low leakage voltage testing; if there are test points that have not undergone low leakage voltage testing, the next test point is selected as the target test point and the process returns to perform the low leakage voltage test on the target test point.

[0054] In this embodiment, a test point is acquired as a target test point; a low leakage voltage test is performed on the target test point. The control chip acquires the voltage V3 acquired by the acquisition module, and obtains the leakage current I3 of the target test point according to the formula (I = V / Rs) and the acquired voltage V3, where Rs is a known resistance; the leakage current I3 of the target test point is taken as the target low leakage voltage test result; it is determined whether the target low leakage voltage test result is within the low leakage voltage test range in the low leakage voltage test strategy, and the low leakage voltage test result of whether the target test point was successfully tested is obtained; it is determined whether there are test points that have not undergone low leakage voltage testing; if there are test points that have not undergone low leakage voltage testing, the next test point is acquired as the target test point and the process returns to perform the low leakage voltage test on the target test point.

[0055] In one embodiment, after step S13, the method further includes:

[0056] The intelligent terminal integrates the open-circuit and short-circuit test results to obtain a first test result; the intelligent terminal integrates the high leakage voltage test results to obtain a second test result; the intelligent terminal integrates the low leakage voltage test results to obtain a third test result; the intelligent terminal generates and stores a test report based on the first test result, the second test result, and the third test result.

[0057] In this embodiment, the intelligent terminal integrates the open / short circuit test results to obtain a first test result; the intelligent terminal integrates the high leakage voltage test results to obtain a second test result; the intelligent terminal integrates the low leakage voltage test results to obtain a third test result; the intelligent terminal generates and stores a test report based on the first test result, the second test result, and the third test result. Staff can quickly locate and view faulty test points based on the test report, effectively improving testing efficiency.

[0058] In one embodiment, prior to step S13, the method further includes:

[0059] Determine whether the first test result meets the preset first restriction condition to obtain a first result of whether the test passed; determine whether the second test result meets the preset second restriction condition to obtain a second result of whether the test passed; determine whether the third test result meets the preset third restriction condition to obtain a third result of whether the test passed.

[0060] In this embodiment, the first limiting condition can be set according to requirements; specifically, it is determined whether the test pass rate of the first test result is 100% to obtain the first result that the device under test has passed the open / short circuit test; the second limiting condition can be set according to requirements; specifically, it is determined whether the test pass rate of the second test result is greater than 70% to obtain the second result that the device under test has passed the high leakage voltage test; the third limiting condition can be set according to requirements; specifically, it is determined whether the test pass rate of the third test result is greater than 70% to obtain the third result that the device under test has passed the low leakage voltage test.

[0061] This invention provides a test circuit and method for DDR5. The circuit includes a device under test (DUT), an adapter board, and a test substrate. The DUT includes multiple test points, which are connected to the test substrate via the adapter board. The test substrate includes a first switch module, a second switch module, a third switch module, a fourth switch module, a data acquisition module, a first output module, a second output module, and a control chip. The end of each test point not connected to the DUT is connected to the first terminal of a first relay switch and the first terminal of a second relay switch, respectively. The first relay switches are all connected in parallel between the DUT and the first switch modules. Relay switches are connected in parallel between the device under test (DUT) and the second switch module. The first switch module includes a first switch and a second switch. The second switch module includes a third switch and a fourth switch. The third switch module includes a fifth switch and a sixth switch. The fourth switch module includes a seventh switch and an eighth switch. The second terminals of the first relay switches are all connected to the first terminals of the first switches. The second terminals of the second relay switches are all connected to the first terminals of the third switches. The first terminal of the control chip is connected to the second output module, the second terminal of the control chip is connected to the first output module, and the third terminal of the control chip is connected to the acquisition module. This invention enables precise testing of the DUT based on the test circuit, effectively improving testing efficiency and the accuracy of test results.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A test circuit for DDR5, characterized in that, include: The device under test (DUT), an adapter board, and a test substrate are provided. The DUT includes multiple test points, which are connected to the test substrate via the adapter board. The test substrate includes a first switch module, a second switch module, a third switch module, a fourth switch module, a data acquisition module, a first output module, a second output module, and a control chip; The end of each test point that is not connected to the device under test is connected to the first terminal of the first relay switch and the first terminal of the second relay switch, respectively. The first relay switches are all connected in parallel between the device under test and the first switch module, and the second relay switches are all connected in parallel between the device under test and the second switch module; The first switch module includes a first switch and a second switch; The second switch module includes a third switch and a fourth switch; The third switch module includes a fifth switch and a sixth switch; The fourth switch module includes a seventh switch and an eighth switch; The second terminals of the first relay switch are all connected to the first terminals of the first switch; The second terminal of the second relay switch is connected to the first terminal of the third switch; The first terminal of the control chip is connected to the second output module, the second terminal of the control chip is connected to the first output module, and the third terminal of the control chip is connected to the acquisition module.

2. The test circuit for DDR5 according to claim 1, characterized in that, The second terminals of the first relay switch are all connected to the first terminals of the first switch; The second end of the first switch is sequentially connected to the second contact of the first switch module, the fourth contact of the first switch module, and the second end of the second switch; The first end of the second switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the output end of the first output module through the first contact of the third switch module; The second terminal of the second relay switch is connected to the first terminal of the third switch; The second end of the third switch is connected in sequence to the first contact of the second switch module, the third contact of the second switch module, and the second end of the fourth switch; The first end of the fourth switch is connected to the first end of the sixth switch, and the second end of the sixth switch is connected to the input end of the first output module through the third contact of the third switch module. The second terminals of each of the first relay switches are connected in sequence, and their connection points serve as the first terminals of the relays. The second terminals of each of the second relay switches are connected in sequence, and their connection points serve as the second terminals of the relays. The first end of the acquisition module is connected to the second end of the seventh switch, and the second end of the acquisition module is connected to the second end of the eighth switch; The first end of the seventh switch is connected in sequence to the first contact of the fourth switch module and the first end of the relay, and the first end of the eighth switch is connected in sequence to the third contact of the fourth switch module and the second end of the relay. The second end of the control chip is connected to the first output module.

3. The test circuit for DDR5 according to claim 1, characterized in that, The second terminals of the first relay switch are all connected to the first terminals of the first switch; The second end of the first switch is connected in sequence to the first contact of the first switch module, the test resistor, the third contact of the first switch module, and the second end of the second switch; The first end of the second switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the output end of the second output module through the second contact of the third switch module; The second terminal of the second relay switch is connected to the first terminal of the third switch; The second end of the third switch is connected in sequence to the first contact of the second switch module, the third contact of the second switch module, and the second end of the fourth switch; The first end of the fourth switch is connected to the first end of the sixth switch, and the second end of the sixth switch is connected to the input end of the second output module through the fourth contact of the third switch module. The first end of the acquisition module is connected to the second end of the seventh switch, and the second end of the acquisition module is connected to the second end of the eighth switch; The first end of the seventh switch is sequentially connected to the second contact of the fourth switch module, the test resistor, the fourth contact of the fourth switch module, and the first end of the eighth switch; The first end of the control chip is connected to the second output module.

4. The test circuit for DDR5 according to claim 1, characterized in that, The second terminals of the first relay switch are all connected to the first terminals of the first switch; The second end of the first switch is connected in sequence to the first contact of the first switch module, the test resistor, the third contact of the first switch module, and the second end of the second switch; The first end of the second switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the output end of the second output module through the second contact of the third switch module; The second terminal of the second relay switch is connected to the first terminal of the third switch; The second end of the third switch is sequentially connected to the second contact of the second switch module, the test resistor, the fourth contact of the second switch module, and the second end of the fourth switch. The first end of the fourth switch is connected to the first end of the sixth switch, and the second end of the sixth switch is connected to the input end of the second output module through the fourth contact of the third switch module. The first end of the acquisition module is connected to the second end of the seventh switch, and the second end of the acquisition module is connected to the second end of the eighth switch; The first end of the seventh switch is sequentially connected to the second contact of the fourth switch module, the test resistor, the fourth contact of the fourth switch module, and the first end of the eighth switch; The first end of the control chip is connected to the second output module.

5. A precise testing method for DDR5, applied to a control chip in the DDR5 testing circuit according to any one of claims 1-4, wherein the control chip is communicatively connected to the acquisition module and the smart terminal respectively, characterized in that... The method includes: According to the preset open and short circuit test strategy, open and short circuit tests are performed on each test point in sequence to obtain the open and short circuit test results corresponding to each test point, and the open and short circuit test results corresponding to each test point are sent to the smart terminal. According to the preset high leakage voltage test strategy, the high leakage voltage test is performed on each test point in sequence to obtain the high leakage voltage test result corresponding to each test point, and the high leakage voltage test result corresponding to each test point is sent to the smart terminal. According to the preset low leakage voltage test strategy, the low leakage voltage test is performed on each test point in sequence to obtain the low leakage voltage test result corresponding to each test point, and the low leakage voltage test result corresponding to each test point is sent to the smart terminal.

6. The accurate testing method for DDR5 according to claim 5, characterized in that, The step of sequentially performing open-short circuit tests on each test point according to a preset open-short circuit test strategy to obtain open-short circuit test results corresponding to each test point includes: Obtain a test point as the target test point; Perform open-short circuit tests on the target test points to obtain the target open-short circuit test results; Determine whether the target open / short circuit test result is within the open / short circuit test range of the open / short circuit test strategy, and obtain the open / short circuit test result indicating whether the test was successful. Determine if there are any test points where open / short circuit testing was not performed; If there are test points that have not undergone open / short circuit testing, then obtain the next test point as the target test point and return to execute the step of performing open / short circuit testing on the target test point.

7. The accurate testing method for DDR5 according to claim 5, characterized in that, The step of sequentially performing high leakage voltage tests on each test point according to a preset high leakage voltage test strategy to obtain high leakage voltage test results corresponding to each test point includes: Obtain a test point as the target test point; A high leakage voltage test is performed on the target test point to obtain the target high leakage voltage test result; Determine whether the target high leakage voltage test result is within the high leakage voltage test range in the high leakage voltage test strategy, and obtain the high leakage voltage test result indicating whether the test was successful. Determine if there are any test points where high leakage voltage testing was not performed; If there are test points that have not undergone high leakage voltage testing, then obtain the next test point as the target test point and return to execute the step of performing high leakage voltage testing on the target test point.

8. The precise testing method for DDR5 according to claim 5, characterized in that, The step of sequentially performing low leakage voltage tests on each test point according to a preset low leakage voltage test strategy to obtain low leakage voltage test results corresponding to each test point includes: Obtain a test point as the target test point; A low leakage voltage test is performed on the target test point to obtain the target low leakage voltage test result; Determine whether the target low leakage voltage test result is within the low leakage voltage test range in the low leakage voltage test strategy, and obtain the low leakage voltage test result indicating whether the test was successful. Determine if there are any test points where low leakage voltage testing was not performed; If there are test points that have not undergone low leakage voltage testing, then obtain the next test point as the target test point and return to execute the step of performing low leakage voltage testing on the target test point.

9. The accurate testing method for DDR5 according to claim 5, characterized in that, After sending the low leakage voltage test results corresponding to each of the test points to the smart terminal, the method further includes: The smart terminal integrates the open and short circuit test results to obtain a first test result; The intelligent terminal integrates the high leakage voltage test results to obtain a second test result; The intelligent terminal integrates the low leakage voltage test results to obtain a third test result; The smart terminal generates and stores a test report based on the first test result, the second test result, and the third test result.

10. The precise testing method for DDR5 according to claim 9, characterized in that, Before the smart terminal generates and stores a test report based on the first test result, the second test result, and the third test result, it also includes: Determine whether the first test result meets the preset first restriction condition to obtain a first result indicating whether the test passed. Determine whether the second test result meets the preset second constraint condition to obtain a second result indicating whether the test passed. Determine whether the third test result meets the preset third restriction condition to obtain a third result indicating whether the test passed.

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