Method of manufacturing a semiconductor device

Abstract

The present application relates to a manufacturing method of a semiconductor device. The present application aims to provide a semiconductor device with high reliability and mobility. The semiconductor device includes: forming a first metal oxide film containing aluminum as a main component over a substrate; forming an amorphous oxide semiconductor film over the first metal oxide film under conditions where the oxygen partial pressure is higher than or equal to 3 % and lower than or equal to 5 %; processing the oxide semiconductor film into a patterned oxide semiconductor layer; crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer; processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask; forming a gate insulating film over the oxide semiconductor layer; and forming a gate electrode over the gate insulating film, wherein the oxide semiconductor film has a film thickness greater than 10 nm and less than or equal to 30 nm.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel and a method for manufacturing a semiconductor device. Background Technology

[0002] In recent years, the development of semiconductor devices using oxide semiconductors for the channel has been continuously advancing, replacing amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon (for example, Patent Documents 1-6). Semiconductor devices using oxide semiconductors for the channel, like those using amorphous silicon for the channel, can be fabricated with simple structures and low-temperature processes. It is known that semiconductor devices using oxide semiconductors for the channel have higher mobility than those using amorphous silicon for the channel.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] However, the field-effect mobility of conventional thin-film transistors containing oxide semiconductor layers is not very high, even when using crystalline oxide semiconductor layers. Therefore, it is desirable to improve the crystal structure of the oxide semiconductor layer used in thin-film transistors to increase the field-effect mobility of the thin-film transistors.

[0013] It is known that by relatively increasing the proportion of indium in the oxide semiconductor layer, semiconductor devices with high mobility can be obtained, but oxygen defects are easily formed in the oxide semiconductor layer. If a large number of oxygen defects exist in the channel formed in the oxide semiconductor layer, it will cause variations in the electrical characteristics of the semiconductor device.

[0014] One objective of one embodiment of the present invention is to provide a semiconductor device with high reliability and mobility.

[0015] Methods for solving problems

[0016] An embodiment of the present invention relates to a semiconductor device comprising: forming a first metal oxide film with aluminum as the main component on a substrate; forming an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%; processing the oxide semiconductor film into a patterned oxide semiconductor layer; crystallizing the oxide semiconductor layer by subjecting the patterned oxide semiconductor layer to a first heat treatment; processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask; forming a gate insulating film on the oxide semiconductor layer; and forming a gate electrode on the gate insulating film, wherein the thickness of the oxide semiconductor film is greater than 10 nm and less than 30 nm. Attached Figure Description

[0017] [ Figure 1 This is a cross-sectional view illustrating a schematic representation of a semiconductor device according to an embodiment of the present invention.

[0018] [ Figure 2 [A top view showing an outline of a semiconductor device according to an embodiment of the present invention.]

[0019] [ Figure 3 This is a sequence diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0020] [ Figure 4 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0021] [ Figure 5 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0022] [ Figure 6 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] [ Figure 7 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] [ Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] [ Figure 9 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] [ Figure 10 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] [ Figure 11 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] [ Figure 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] [ Figure 13 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] [ Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] [ Figure 15 This is a sequence diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] [ Figure 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0033] [ Figure 17 [A top view showing an outline of a display device according to an embodiment of the present invention.]

[0034] [ Figure 18 [A block diagram illustrating the circuit configuration of a display device according to an embodiment of the present invention.]

[0035] [ Figure 19 This is a circuit diagram illustrating the pixel circuit of a display device according to an embodiment of the present invention.

[0036] [ Figure 20 [A cross-sectional view showing an outline of a display device according to an embodiment of the present invention.]

[0037] [ Figure 21 This is a top view of the pixel electrode and common electrode of a display device according to an embodiment of the present invention.

[0038] [ Figure 22 This is a circuit diagram illustrating the pixel circuit of a display device according to an embodiment of the present invention.

[0039] [ Figure 23 [A cross-sectional view showing an outline of a display device according to an embodiment of the present invention.]

[0040] [ Figure 24 This is a photograph of the surface of a semiconductor device taken using an optical microscope.

[0041] [ Figure 25 [Id-Vg characteristics] are the electrical characteristics of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 10 nm.

[0042] [ Figure 26 [Id-Vg characteristics] are the electrical characteristics of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 20 nm.

[0043] [ Figure 27 [Id-Vg characteristics] are the electrical characteristics of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 30 nm.

[0044] [ Figure 28 [ ] represents the intrinsic mobility relative to various film formation conditions of the oxide semiconductor film.

[0045] [ Figure 29 ] represents the variation of the threshold voltage ΔVth relative to various film formation conditions of the oxide semiconductor film.

[0046] Explanation of reference numerals in the attached figures

[0047] 10: Semiconductor device; 11: Driving transistor; 12: Selecting transistor; 20: Display device; 22: Liquid crystal area; 24: Sealing area; 26: Terminal area; 100: Substrate; 105: Gate electrode; 110: Gate insulating film; 120: Gate insulating film; 130: Metal oxide film; 132: Metal oxide layer; 140: Oxide semiconductor film; 142: Oxide semiconductor layer; 143: Resist mask; 144: Oxide semiconductor layer; 144CH: Channel region; 144D: Drain region; 144S: Source region; 150: Gate insulating film; 160: Gate electrode; 164: Oxide semiconductor layer; 170: Insulating film; 171: Opening; 173: Opening; 180: Insulating film; 190: Metal oxide film 200: Drain electrode; 201: Source electrode; 203: Drain electrode; 210: Holding capacitor; 211: Signal line; 212: Gate line; 213: Anode power line; 214: Cathode power line; 300: Array substrate; 301: Pixel circuit; 302: Source driving circuit; 303: Gate driving circuit; 304: Source wiring; 306: Terminal portion; 307: Connection wiring; 310: Sealing portion; 311: Liquid crystal element; 320: Opposing substrate; 330: Flexible printed circuit board; 340: Chip; 350: Holding capacitor; 360: Insulating film; 362: Insulating film; 363: Opening; 370: Common electrode; 380: Insulating film; 381: Opening; 390: Pixel electrode; 392: Emitting layer; 394: Common electrode Detailed Implementation

[0048] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Configurations that can be readily conceived by those skilled in the art through appropriate modifications to the configuration of the embodiments while maintaining the spirit of the invention are of course included within the scope of the present invention. In addition, for the purpose of making the description clearer, there are cases where the width, film thickness, or shape of various parts in the drawings are schematically represented compared to the actual embodiment. However, the shapes illustrated are merely examples and do not limit the interpretation of the present invention. In this specification and the various drawings, the same reference numerals are sometimes used for the same elements as those stated above with respect to the foregoing drawings, and detailed descriptions are appropriately omitted.

[0049] "Semiconductor device" refers to any device that can function by utilizing the properties of semiconductors. Transistors and semiconductor circuits are forms of semiconductor devices. The semiconductor devices in the embodiments shown below can be, for example, transistors used in integrated circuits (ICs) such as display devices and microprocessors (MPUs), or in memory circuits.

[0050] "Display device" refers to a structure that uses an electro-optic layer to display images. For example, the term "display device" sometimes also refers to a display panel that includes an electro-optic layer, or sometimes to a structure that mounts other optical components (e.g., polarizing components, backlights, touch panels, etc.) onto a display unit. As long as there is no technical inconsistency, the "electro-optic layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer. Therefore, regarding the embodiments described later, examples of display devices include a liquid crystal display device containing a liquid crystal layer and an organic EL display device containing an organic EL layer; however, the structure in this embodiment can be applied to display devices containing other electro-optic layers described above.

[0051] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for ease of explanation, the terms "up" or "below" are used, but for example, the vertical relationship between the substrate and the oxide semiconductor layer may be configured in the opposite direction to the illustration. In the following description, the description of "oxide semiconductor layer on substrate" is merely an explanation of the vertical relationship between the substrate and the oxide semiconductor layer as described above; other components may also be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure in which multiple layers are stacked. In the case of describing a pixel electrode above a transistor, it may also refer to the non-overlapping position of the transistor and the pixel electrode when viewed from above. On the other hand, in the case of describing a pixel electrode vertically above a transistor, it refers to the overlapping position of the transistor and the pixel electrode when viewed from above. It should be noted that "viewed from above" means viewed from a direction perpendicular to the surface of the substrate.

[0052] In this specification and other materials, the term "membrane" and the term "layer" may be used interchangeably, depending on the circumstances.

[0053] In this specification, unless otherwise specified, statements such as "α includes A, B, or C," "α includes any one of A, B, and C," or "α includes one of the groups selected from A, B, and C" do not preclude the possibility that α includes multiple combinations of A to C. Furthermore, these statements do not preclude the possibility that α includes other elements.

[0054] It should be noted that the following implementation methods can be combined with each other as long as there is no technical contradiction.

[0055] <First Embodiment>

[0056] use Figures 1 to 14 The semiconductor device 10 according to one embodiment of the present invention will be described.

[0057] [Semiconductor device 10 configuration]

[0058] use Figures 1-2 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 1 A cross-sectional view illustrating a schematic of a semiconductor device 10 according to an embodiment of the present invention. Figure 2 This is a top view illustrating an outline of a semiconductor device 10 according to an embodiment of the present invention. Additionally, Figure 2 The cross-section shown when cut with a single-dot dashed line corresponds to Figure 1 The sectional view shown.

[0059] like Figure 1 As shown, a semiconductor device 10 is disposed above a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating films 110 and 120, an oxide semiconductor layer 144, a gate insulating film 150, a gate electrode 160, insulating films 170 and 180, a source electrode 201, and a drain electrode 203. Without specifically distinguishing between the source electrode 201 and the drain electrode 203, they are sometimes referred to together as the source electrode and drain electrode 200. Additionally, the oxide semiconductor layer 144, the gate insulating film 150, and the gate electrode 160 are sometimes referred to as a transistor.

[0060] A gate electrode 105 is disposed on the substrate 100. A gate insulating film 110 and a gate insulating film 120 are disposed on the substrate 100 and the gate electrode 105, respectively. A metal oxide layer 132 is disposed on the gate insulating film 120. The metal oxide layer 132 is in contact with the gate insulating film 120. An oxide semiconductor layer 144 is disposed on the metal oxide layer 132. The oxide semiconductor layer 144 is in contact with the metal oxide layer 132. The surface of the oxide semiconductor layer 144 that is in contact with the metal oxide layer 132 is referred to as the lower surface. The ends of the metal oxide layer 132 and the ends of the oxide semiconductor layer 144 are substantially aligned.

[0061] The oxide semiconductor layer 144 is transparent. Furthermore, the oxide semiconductor layer 144 is divided into a source region 144S, a drain region 144D, and a channel region 144CH. The channel region 144CH is the region in the oxide semiconductor layer 144 that is vertically below the gate electrode 160. The source region 144S is the region in the oxide semiconductor layer 144 that does not overlap with the gate electrode 160, and is closer to the source electrode 201 than the channel region 144CH. The drain region 144D is the region in the oxide semiconductor layer 144 that does not overlap with the gate electrode 160, and is closer to the drain electrode 203 than the channel region 144CH.

[0062] The oxide semiconductor layer 144 has a polycrystalline structure comprising multiple grains. Details are described below. The oxide semiconductor layer 144 with a polycrystalline structure can be formed using Poly-OS (Poly-crystalline Oxide Semiconductor) technology. The structure of the oxide semiconductor layer 144 will be described below; sometimes, the oxide semiconductor with a polycrystalline structure is referred to as Poly-OS.

[0063] The grain size of the grains contained in the Poly-OS, as observed from the upper surface (or the thickness direction of the oxide semiconductor layer 144) or a cross-section of the oxide semiconductor layer 144, is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The grain size can be obtained, for example, by cross-sectional SEM observation, cross-sectional TEM observation, or electron backscatter diffraction (EBSD) method.

[0064] The oxide semiconductor layer 144 has a film thickness greater than 10 nm and less than 30 nm. As mentioned above, the crystal grain size of the grains contained in Poly-OS is greater than 0.1 μm, therefore the oxide semiconductor layer 144 contains a region with only one grain in the film thickness direction.

[0065] As will be explained in detail later, the oxide semiconductor layer 144 contains two or more metals containing indium, and the proportion of indium in the two or more metals is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides are used. Elements other than those mentioned above can be used as the oxide semiconductor layer 144. In this embodiment, an IGO-based oxide semiconductor is preferably used as the oxide semiconductor layer 144. An IGO-based oxide semiconductor refers to an oxide semiconductor containing indium, gallium, and oxygen.

[0066] Furthermore, the source region 144S and drain region 144D contain impurity elements. Additionally, by adding impurity elements, the resistivity of the source region 144S and drain region 144D in the oxide semiconductor layer 144 can be significantly reduced compared to the channel region 144CH. That is, the source region 144S and drain region 144D possess the physical properties of conductors.

[0067] Regarding the concentration of impurity elements contained in the source region 144S and the drain region 144D, when measured using SIMS analysis (secondary ion mass spectrometry), a concentration of 1 × 10⁻⁶ is preferred. 18 cm-3 Above 1×10 21 cm -3 Below. Here, impurity elements refer to argon (Ar), phosphorus (P), or boron (B). Additionally, the source region 144S and drain region 144D contain 1 × 10⁻⁶ elements. 18 cm -3 Above 1×10 21 cm -3 When the following impurity elements are present, it is presumed that the impurity elements were intentionally added using ion implantation or doping methods. However, in the source region 144S and the drain region 144D, impurity elements may also be added in quantities less than 1 × 10⁻⁶. 18 cm -3 The concentration includes impurity elements other than argon (Ar), phosphorus (P), or boron (B).

[0068] Gate electrode 160 is opposite to oxide semiconductor layer 144. Gate insulating film 150 is disposed between oxide semiconductor layer 144 and gate electrode 160. Gate insulating film 150 is in contact with oxide semiconductor layer 144. The surface of main surface of oxide semiconductor layer 144 that is in contact with gate insulating film 150 is called upper surface. The surface between upper surface and lower surface is called side surface. Insulating films 170 and 180 are disposed on gate insulating film 150 and gate electrode 160. Openings 171 and 173 are provided in insulating films 170 and 180, reaching oxide semiconductor layer 144. Source electrode 201 is disposed inside opening 171. Source electrode 201 is in contact with oxide semiconductor layer 144 at the bottom of opening 171. Drain electrode 203 is disposed inside opening 173. Drain electrode 203 is in contact with oxide semiconductor layer 144 at the bottom of opening 173.

[0069] The gate electrode 160 functions as the top gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 144. The gate insulating film 150 functions as a gate insulating film for the top gate and has the function of releasing oxygen through heat treatment during the manufacturing process. The insulating films 170 and 180 have the function of insulating the gate electrode 160 from the source electrode and drain electrode 200 and reducing the parasitic capacitance between them. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. Wherein, when the gate electrode 105 is used only as a light-shielding film, a specific voltage may not be supplied to the gate electrode 105, but a floating potential may be used. That is, the gate electrode 105 may also be simply referred to as a "light-shielding film".

[0070] like Figure 2 As shown, from a top view, the top view pattern of the metal oxide layer 132 is substantially the same as that of the oxide semiconductor layer 144. (Refer to...) Figure 1 and Figure 2At this time, the lower surface of the oxide semiconductor layer 144 is covered by the metal oxide layer 132. In particular, in the semiconductor device 10 according to this embodiment, the entire lower surface of the oxide semiconductor layer 144 is covered by the metal oxide layer 132. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is the direction that connects the source electrode 201 and the drain electrode 203, and is the direction that represents the channel length L of the semiconductor device 10. Specifically, the length of the region (channel region 144CH) where the oxide semiconductor layer 144 and the gate electrode 160 overlap in the D1 direction is the channel length L, and the width of the channel region 144CH in the D2 direction is the channel width W.

[0071] This embodiment illustrates a configuration where the entire lower surface of the oxide semiconductor layer 144 is covered by the metal oxide layer 132, but is not limited to this configuration. For example, a portion of the lower surface of the oxide semiconductor layer 144 may not be in contact with the metal oxide layer 132. For instance, the entire lower surface of the oxide semiconductor layer 144 in the channel region 144CH may be covered by the metal oxide layer 132, while all or part of the lower surface of the oxide semiconductor layer 144 in the source region 144S and drain region 144D may not be covered by the metal oxide layer 132. That is, all or part of the lower surface of the oxide semiconductor layer 144 in the source region 144S and drain region 144D may not be in contact with the metal oxide layer 132. However, in the above configuration, a portion of the lower surface of the oxide semiconductor layer 144 in the channel region 144CH may not be covered by the metal oxide layer 132, while other portions of the lower surface are in contact with the metal oxide layer 132.

[0072] Figure 1 The illustration shows a configuration in which, from a top view, the source and drain electrodes 200 do not overlap with the gate electrodes 105 and 160, but the invention is not limited to this configuration. For example, from a top view, the source and drain electrodes 200 may overlap with at least one of the gate electrodes 105 and 160. The above configuration is merely one embodiment, and the invention is not limited to the above configuration.

[0073] This embodiment illustrates a configuration where a top-gate transistor with its gate electrode disposed on the oxide semiconductor layer 144 is used as the semiconductor device 10, but the invention is not limited to this configuration. For example, the semiconductor device 10 may be a bottom-gate transistor with its gate electrode disposed only below the oxide semiconductor layer 144, or a dual-gate transistor with its gate electrode disposed both above and below the oxide semiconductor layer 144. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0074] [Manufacturing method of semiconductor device 10]

[0075] use Figures 3 to 14 A method for manufacturing a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 3 This is a sequence diagram illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figures 4 to 14 A cross-sectional view illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention.

[0076] like Figure 3 and Figure 4 As shown, a gate electrode 105 is formed on the substrate 100 as a bottom gate, and gate insulating films 110 and 120 are formed on the gate electrode 105. Figure 3 Step S1001, “Bottom GI / GE (Bottom GI / GE) Formation”.

[0077] As substrate 100, rigid substrates with light transmittance such as glass substrates, quartz substrates, and sapphire substrates can be used. If substrate 100 needs to be flexible, substrates such as polyimide substrates, acrylic substrates, siloxane substrates, fluoropolymer substrates, or resin-containing substrates can be used. When using a resin-containing substrate as substrate 100, impurity elements can be introduced into the resin to improve its heat resistance. Especially when the semiconductor device 10 is a top-emitting display, since substrate 100 does not need to be transparent, impurities that reduce the transparency of substrate 100 can be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, substrates without light transmittance such as silicon substrates, silicon carbide substrates, compound semiconductor substrates, or conductive substrates such as stainless steel substrates can be used as substrate 100.

[0078] The gate electrode 105 is formed by processing a conductive film deposited by sputtering. Conventional metallic materials are used as the gate electrode 105. Examples of materials used for the gate electrode 105 include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds. These materials can be used as a single layer or in a stacked configuration as the gate electrode 105.

[0079] Gate insulating films 110 and 120 are formed using CVD (Chemical Vapor Deposition) or sputtering methods. Conventional insulating materials are used as gate insulating films 110 and 120. For example, silicon oxide (SiO2) is used as a gate insulating film 110 and 120. x ), silicon nitride (SiO) x N y), silicon nitride (SiN) x ), silicon nitride (SiN) x O y Inorganic insulating materials such as SiO2. x N y It is a silicon compound containing nitrogen (N) in a ratio less than that of oxygen (O) (x>y). SiN x O y It is a silicon compound containing oxygen in a ratio less than that of nitrogen (x>y).

[0080] As gate insulating films 110 and 120, it is preferable to form a nitrogen-containing insulating material and an oxygen-containing insulating material sequentially from the substrate 100. For example, by using a nitrogen-containing insulating material as the gate insulating film 110, it is possible to block impurities, for example, diffusing from the substrate 100 side toward the oxide semiconductor layer 144. Furthermore, by using an oxygen-containing insulating material as the gate insulating film 120, oxygen can be released through heat treatment. The heat treatment temperature for releasing oxygen from the oxygen-containing insulating material is, for example, 500°C or less, 450°C or less, or 400°C or less. That is, the oxygen-containing insulating material releases oxygen at the heat treatment temperature performed, for example, in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100. In this embodiment, silicon nitride is formed, for example, as the gate insulating film 110. Silicon oxide is formed, for example, as the gate insulating film 120.

[0081] like Figure 3 and Figure 5 As shown, a metal oxide film 130 is formed on the gate insulating film 120. Figure 3 The step S1002 shown is “MO film formation”. The metal oxide film 130 is formed by sputtering or atomic layer deposition (ALD).

[0082] As the metal oxide film 130, a metal oxide with aluminum as the main component is used. For example, aluminum oxide (Al₂O₃) is used as the metal oxide film 130. x ), aluminum nitride (AlO) x N y Aluminum nitride (AlNxOy), aluminum nitride (AlN) x Inorganic insulating layers such as aluminum oxide film and metal oxide film 130. A metal oxide film with aluminum as the main component refers to a metal oxide film in which the proportion of aluminum is 1% or more of the total metal oxide film 130. The proportion of aluminum in the metal oxide film 130 can be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide film 130. The above proportions can be either mass ratios or weight ratios.

[0083] The thickness of the metal oxide film 130 is, for example, 1 nm to 50 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide film 130. Aluminum oxide has high barrier properties to gases such as oxygen or hydrogen. In other words, barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen through the aluminum oxide. That is, it means that even if gases such as oxygen or hydrogen are present from the layer disposed below the aluminum oxide film, they will not move to the layer disposed above the aluminum oxide film. Or, it means that even if gases such as oxygen or hydrogen are present from the layer disposed above the aluminum oxide film, they will not move to the layer disposed below the aluminum oxide film. In this embodiment, the aluminum oxide used as the metal oxide film 130 blocks hydrogen and oxygen emitted from the gate insulating film 120, inhibiting the emitted hydrogen and oxygen from reaching the oxide semiconductor layer.

[0084] like Figure 3 and Figure 6 As shown, an oxide semiconductor film 140 is formed on top of a metal oxide film 130. Figure 3 The step S1003 “OS film formation” is shown. In this process, sometimes an oxide semiconductor film 140 is formed on the substrate 100.

[0085] The oxide semiconductor film 140 is formed using sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 140 is, for example, greater than 10 nm and less than 30 nm.

[0086] As the oxide semiconductor film 140, a metal oxide with semiconductor properties can be used. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor film 140. Furthermore, the ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanides are also used as the oxide semiconductor film 140. Preferably, it contains group 13 elements. However, elements other than those mentioned above can also be used as the oxide semiconductor film 140. In this embodiment, an IGO-based oxide semiconductor is preferred as the oxide semiconductor film 140.

[0087] When the oxide semiconductor film 140 is crystallized by OS annealing (described later), the oxide semiconductor film 140 after film formation and before OS annealing is preferably amorphous (in a state with low crystal content of the oxide semiconductor). That is, the film formation method of the oxide semiconductor film 140 is preferably such that the oxide semiconductor film 140 is as non-crystallized as possible immediately after film formation. For example, when the oxide semiconductor film 140 is formed by sputtering, the oxide semiconductor film 140 is formed while controlling the temperature of the object to be formed (the substrate 100 and the structure formed thereon).

[0088] When a film is formed on an object to be formed using sputtering, ions generated in the plasma and atoms bounced off the sputtering target collide with the object to be formed, causing the temperature of the object to rise during the film formation process. If the temperature of the object to be formed rises during the film formation process, microcrystals will be present in the oxide semiconductor film 140 immediately after film formation. If microcrystals are present in the oxide semiconductor film 140, the crystal grain size cannot be increased by subsequent OS annealing. In order to control the temperature of the object to be formed as described above, for example, film formation can be performed while cooling the object to be formed. For example, the object to be formed can be cooled from the side opposite to the surface to which the film is formed, such that the temperature of the surface to be formed (hereinafter referred to as the "film formation temperature") is 100°C or lower, 70°C or lower, 50°C or lower. In particular, the film formation temperature of the oxide semiconductor film 140 in this embodiment is preferably 50°C or lower. By cooling the substrate while forming the oxide semiconductor film 140, an oxide semiconductor film 140 with low crystal content can be obtained immediately after film formation. In this embodiment, the oxide semiconductor film 140 is formed at a film formation temperature of 50°C or lower, and OS annealing (described later) is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, the difference between the temperature at which the oxide semiconductor film 140 is formed and the temperature at which the oxide semiconductor film 140 is OS annealed is preferably 350°C or higher.

[0089] In the sputtering process, an amorphous oxide semiconductor film 140 is formed under conditions where the oxygen partial pressure is 10% or less. If the oxygen partial pressure is high, microcrystals will be present in the oxide semiconductor film 140 immediately after formation due to excess oxygen contained therein. Therefore, it is preferable to form the oxide semiconductor film 140 under conditions of low oxygen partial pressure. For example, the oxygen partial pressure is 3% to 5%, preferably 3% to 4%. It should be noted that when the oxide semiconductor film is formed under conditions of 2% oxygen partial pressure, the oxide semiconductor film does not crystallize even after subsequent OS annealing.

[0090] like Figure 3 and Figure 7As shown, the pattern forming the oxide semiconductor layer 142 ( Figure 3 (See step S1004, "OS pattern formation"). Although not shown, a photoresist mask 143 is formed on the oxide semiconductor film 140, and the oxide semiconductor film 140 is etched using the photoresist mask 143. The etching of the oxide semiconductor film 140 can be performed using either wet etching or dry etching. As wet etching, an acidic etchant can be used. Examples of etchants include oxalic acid, PAN, sulfuric acid, aqueous hydrogen peroxide solution, or hydrofluoric acid. This allows the formation of a patterned oxide semiconductor layer 142. The photoresist mask 143 is then removed.

[0091] The oxide semiconductor film 140 is preferably patterned before OS annealing. If the oxide semiconductor film 140 crystallizes through OS annealing, it tends to be difficult to etch. In addition, even if damage is caused in the patterned oxide semiconductor layer 142 due to etching, the damage to the oxide semiconductor layer 142 can be repaired by OS annealing, which is therefore preferred.

[0092] like Figure 3 and Figure 8 As shown, after the patterning of the oxide semiconductor layer 142 is formed, the oxide semiconductor layer 142 is subjected to heat treatment (OS annealing). Figure 3 The step S1005 shown is "OS annealing". In OS annealing, the oxide semiconductor layer 142 is held at a predetermined arrival temperature for a predetermined time. The predetermined arrival temperature is 300°C to 500°C, preferably 350°C to 450°C. Furthermore, the holding time at the arrival temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing OS annealing, the oxide semiconductor layer 142 is crystallized, forming an oxide semiconductor layer 144 with a polycrystalline structure.

[0093] In thin-film transistors (TFTs), reducing the thickness of the oxide semiconductor layer increases the number of charge carriers near the interface with the gate insulating film, reducing the influence of the back channel and thus tending to increase the field-effect mobility. Specifically, TFTs exhibit the following tendency: the smaller the thickness of the region of the oxide semiconductor layer that functions as the channel, the higher the field-effect mobility. Therefore, a smaller oxide semiconductor layer thickness is preferable. However, after depositing an oxide semiconductor layer with a thickness of less than 10 nm, even with heat treatment, the oxide semiconductor layer does not crystallize sufficiently. When the oxide semiconductor layer is not sufficiently crystallized, both the oxide semiconductor layer and the metal oxide film disappear during subsequent etching processes that use the oxide semiconductor layer as a mask to pattern the metal oxide film.

[0094] Furthermore, in thin-film transistors, the crystallinity of the oxide semiconductor layer 144 contributes to improved field-effect mobility. Therefore, the oxide semiconductor layer 144 preferably has a polycrystalline structure. However, if microcrystals are present during the deposition of the oxide semiconductor film 140, even subsequent heat treatment cannot increase the crystal grain size of the polycrystalline structure. Thus, it is difficult to simultaneously achieve both thin-film deposition and good crystallinity of the oxide semiconductor layer.

[0095] Furthermore, if a large number of oxygen vacancies and hydrogen exist near the interface with the metal oxide layer 132 in the oxide semiconductor layer 144, the interface energy level density increases. Since electrons are trapped at the interface energy level, this becomes a major cause of transistor degradation and decreased reliability of semiconductor devices during reliability testing.

[0096] According to a method for manufacturing a semiconductor device based on an embodiment of the present invention, when forming an oxide semiconductor film 140 using a sputtering method, the film is formed at a low oxygen partial pressure of 3% to 5%. By forming the oxide semiconductor film 140 under low oxygen partial pressure conditions, it is possible to suppress the excessive presence of oxygen in the oxide semiconductor film 140 and to suppress the presence of microcrystals in the oxide semiconductor film 140 immediately after film formation. As a result, during the heat treatment of the oxide semiconductor layer 142, the growth of crystals from microcrystals can be suppressed. Therefore, even when the oxide semiconductor film 140 is formed with a thin film thickness of greater than 10 nm and less than 30 nm, the crystal grain size of the polycrystalline structure of the oxide semiconductor layer 144 can be increased.

[0097] like Figure 3 and Figure 9 As shown, the metal oxide film 130 is patterned to form a metal oxide layer 132. Figure 4 (Step S1006, "MO pattern formation"). The oxide semiconductor layer 144, which is sufficiently crystallized by heat treatment, has etch resistance. Therefore, when the metal oxide film 130 is patterned using the crystallized oxide semiconductor layer 144 as a mask, the disappearance of the oxide semiconductor layer 144 can be suppressed. The metal oxide film 130 is etched using the oxide semiconductor layer 144, which is polycrystalline through the above process, as a mask. The etching of the metal oxide film 130 can be performed using wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. By etching the metal oxide film 130 using the oxide semiconductor layer 144 as a mask, the photolithography process can be omitted.

[0098] like Figure 3 and Figure 10 As shown, a gate insulating film 150 is formed on the oxide semiconductor layer 144. Figure 3 The step S1007 shown is "GI film formation".

[0099] The method for forming the gate insulating film 150 and the insulating material can be referred to the descriptions of the gate insulating films 110 and 120. In addition, the film thickness of the gate insulating film 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0100] As the gate insulating film 150, an oxygen-containing insulating material is preferably used. Furthermore, as the gate insulating film 150, an insulating film with few defects is preferably used. For example, when comparing the oxygen composition ratio in the gate insulating film 150 with the oxygen composition ratio in an insulating film with the same composition as the gate insulating film 150 (hereinafter referred to as "other insulating films"), the oxygen composition ratio in the gate insulating film 150 is closer to the stoichiometry for that insulating film compared to the oxygen composition ratio in the other insulating film. For example, silicon oxide (SiO₂) is used in both the gate insulating film 150 and the insulating film 180. x In the case of [missing information], the oxygen composition ratio in the silicon oxide used as the gate insulating film 150 is closer to the stoichiometry of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating film 180. For example, as the gate insulating film 150, a layer in which defects are not observed when evaluated using electron spin resonance (ESR) can be used.

[0101] To form an insulating film with few defects as the gate insulating film 150, the gate insulating film 150 can be formed at a film formation temperature of 350°C or higher. Furthermore, after forming the gate insulating film 150, an oxygen-diffusion process can be performed to introduce oxygen into a portion of the gate insulating film 150. In this embodiment, to form an insulating film with few defects as the gate insulating film 150, silicon oxide is formed at a film formation temperature of 350°C or higher.

[0102] With a gate insulating film 150 formed on the oxide semiconductor layer 144, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 144. Figure 3 The step S1008 shown is "oxidative annealing".

[0103] Oxygen released from the gate insulating film 120 by oxidation annealing is blocked by the metal oxide layer 132, thus preventing oxygen from being readily supplied to the lower surface of the oxide semiconductor layer 144. Oxygen released from the gate insulating film 120 diffuses from the region where the metal oxide layer 132 is not formed to the gate insulating film 150 disposed above the gate insulating film 120, and then reaches the oxide semiconductor layer 144 via the gate insulating film 150. As a result, oxygen released from the gate insulating film 120 is not readily supplied to the lower surface of the oxide semiconductor layer 144, but is mainly supplied to the side and upper surfaces of the oxide semiconductor layer 144. Furthermore, oxygen released from the gate insulating film 150 by oxidation annealing is supplied to the upper and side surfaces of the oxide semiconductor layer 144. During the aforementioned oxidation annealing, hydrogen is sometimes released from the gate insulating films 110 and 120, but this hydrogen is blocked by the metal oxide layer 132.

[0104] During the process from the deposition of the oxide semiconductor layer 144 to the deposition of the gate insulating film 150 on the oxide semiconductor layer 144, a large number of oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 144. Through the aforementioned oxidation annealing, the oxygen released from the gate insulating film 120 is supplied to the upper surface and side surfaces of the oxide semiconductor layer 144, and the oxygen defects are repaired.

[0105] Next, as Figure 3 and Figure 11 As shown, a gate electrode 160 is formed on the gate insulating film 150. Figure 3 The step S1009 shown is "Top GE (Top GE) Formation".

[0106] The gate electrode 160 is formed by processing a conductive film that has been formed by sputtering. Like the gate electrode 105, the gate electrode 160 is made of a conventional metallic material. For information on materials that can be used for the gate electrode 160, please refer to the description of the materials for the gate electrode 105. The aforementioned materials can be used as a single layer or in a stacked manner as the gate electrode 160.

[0107] Next, as Figure 3 and Figure 12 As shown, using the gate electrode 160 as a mask, impurities are added to the oxide semiconductor layer 144. Figure 3 The step S1010 shown is "SD low resistance". In this embodiment, the addition of impurities by ion implantation is described, but ion doping can also be used.

[0108] Specifically, impurity elements are added to the source region 144S and drain region 144D through the gate insulating film 150 via ion implantation. Examples of impurity elements include argon (Ar), phosphorus (P), or boron (B). Furthermore, when adding boron (B) using ion implantation, the accelerating energy is set to 20 keV or higher and 40 keV or lower, and the boron (B) implantation amount is 1 × 10⁻⁶. 14 cm -2 Above 1×10 16 cm -2 That's all.

[0109] It is possible to inject 1×10 into the source region 144S and the drain region 144D. 18 cm -3 Above 1×10 21 cm -3 Impurity elements are added at the following concentrations. In this case, oxygen defects are formed in the oxide semiconductors of the source region 144S and drain region 144D due to the addition of impurity elements. Hydrogen is easily captured by these oxygen defects. This reduces the resistivity of the source region 144S and drain region 144D, allowing them to function as conductors.

[0110] For example, when using an IGZO-based oxide semiconductor layer, the high resistance of the oxide semiconductor layer means that the resistance of the source and drain regions cannot be sufficiently reduced without increasing the film thickness. In contrast, with the oxide semiconductor layer 144 having a polycrystalline structure, by adding impurity elements to the source region 144S and the drain region 144D, the sheet resistance of the source region 144S and the drain region 144D can be reduced to 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less.

[0111] like Figure 3 and Figure 13 As shown, insulating films 170 and 180 are formed on the gate insulating film 150 and the gate electrode 160 as interlayer films. Figure 3 The step S1011 shown is "interlayer film formation".

[0112] The methods for forming insulating films 170 and 180 and the insulating materials can be found in the description of the materials for gate insulating films 110 and 120. The thickness of insulating film 170 is 50 nm to 500 nm. The thickness of insulating film 180 is 50 nm to 500 nm. In this embodiment, for example, silicon oxide is formed as insulating film 170, and silicon nitride is formed as insulating film 180.

[0113] like Figure 3 and Figure 14As shown, openings 171 and 173 are formed in the gate insulating film 150 and the insulating films 170 and 180. Figure 3 The “contact opening” in step S1012 is shown. Due to opening 171, the oxide semiconductor layer 144 of the source region 144S is exposed. Due to opening 173, the oxide semiconductor layer 144 of the drain region 144D is exposed.

[0114] Finally, source and drain electrodes 200 are formed on the oxide semiconductor layer 144 exposed by openings 171 and 173 and on the insulating film 180. Figure 3 The step S1013 shown is "SD formation", which enables the formation of Figure 1 The semiconductor device 10 shown.

[0115] The source electrode and drain electrode 200 are formed, for example, by processing a conductive film formed by sputtering. Like the gate electrode 105, conventional metallic materials are used for the source electrode and drain electrode 200. For details regarding materials that can be used for the source electrode and drain electrode 200, please refer to the description of the gate electrode 105. The aforementioned materials can be used as a single layer or in a stacked manner for the source electrode and drain electrode 200.

[0116] Through the above processes, it is possible to manufacture Figure 1 The semiconductor device 10 shown.

[0117] For the semiconductor device 10 manufactured by the above-described manufacturing method, a mobility of 30 cm⁻¹ can be obtained within the range where the channel length L of the channel region 144CH is 2 μm or more and 4 μm or less, and the channel width of the channel region 144CH is 2 μm or more and 25 μm or less. 2 / Vs and above, 35cm 2 / Vs or above, or 40cm 2 Electrical characteristics above / Vs. The mobility in this specification, etc., refers to the field-effect mobility in the saturation region of the semiconductor device 10, which is the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage supplied to the gate electrode (Vg) (Vg-Vth).

[0118] Here, reliability testing refers to, for example, NGBT (Negative Gate Bias-Temperature) stress testing with a negative gate voltage applied, or PGBT (Positive Gate Bias-Temperature) stress testing with a positive gate voltage applied. It should be noted that NGBT and PGBT stress tests are a type of accelerated testing that can evaluate transistor characteristic changes (over-year variations) caused by long-term use in a short period. In particular, the change in the transistor's threshold voltage before and after the BT stress test becomes an important indicator for investigating reliability. The smaller the change in threshold voltage before and after the BT stress test, the more reliable the transistor is considered to be.

[0119] Furthermore, by thinning the oxide semiconductor layer 144, the ΔL length can be reduced. In this embodiment, hydrogen is implanted into the oxide semiconductor layer 144 using the gate electrode 160 as a mask. At this time, in the oxide semiconductor layer 144, a region where hydrogen invades into the channel region 144CH is sometimes generated with reference to the end of the gate electrode 160. The ΔL length refers to the length in the channel length L direction of the region where hydrogen invades into the channel region 144CH. As in this embodiment, when the oxide semiconductor layer 144 is thin, during ion implantation, hydrogen passes through the oxide semiconductor layer 144 and is driven into the gate insulating film 120 side. As a result, hydrogen diffusion into the channel region 144CH is suppressed, and therefore it is believed that the ΔL length can be reduced.

[0120] <Second Embodiment>

[0121] In this embodiment, a manufacturing method different from that described in the first embodiment of the semiconductor device 10 will be described. It should be noted that the structure of the semiconductor device 10 in this embodiment is the same as that of the semiconductor device 10 described in the first embodiment in terms of appearance. In this embodiment, the description will focus on the differences from the first embodiment.

[0122] [Manufacturing method of semiconductor device 10]

[0123] use Figure 15 , Figure 16 A method for manufacturing a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 15 This is a sequence diagram illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figure 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Detailed descriptions of the same processes as in the first embodiment are omitted.

[0124] Figure 15This is a sequence diagram illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. (See diagram below.) Figure 15 As shown, the processes of steps S1001 to S1007 are similar to... Figure 3 The procedures for steps S1001 to S1007 shown are the same.

[0125] In this embodiment, such as Figure 15 and Figure 16 As shown, after step S1007, a metal oxide film 190 with aluminum as the main component is formed on the gate insulating film 150. Figure 15 Step S1014 “MO film formation” is shown.

[0126] The metal oxide film 190 is formed using a sputtering method. During the formation of the metal oxide film 190, oxygen is introduced into the gate insulating film 150. The metal oxide film 190, with aluminum as the main component, is the same inorganic insulating film as the metal oxide film 130 described in the first embodiment. The percentage of aluminum contained in the metal oxide film 190 can be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide film 190. The above percentages can be either a mass percentage or a weight percentage.

[0127] The thickness of the metal oxide film 190 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide film 190. Aluminum oxide has high gas barrier properties. In this embodiment, the aluminum oxide used as the metal oxide film 190 suppresses the diffusion of oxygen into the gate insulating film 150 during the formation of the metal oxide film 190.

[0128] For example, when a metal oxide film 190 is formed using sputtering, the process gas used in sputtering may remain in the metal oxide film 190. For example, if Ar is used as the sputtering process gas, Ar may sometimes remain in the metal oxide film 190. The residual Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide film 190.

[0129] Next, as Figure 15 As shown, with a metal oxide film 190 formed on the gate insulating film 150, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 144. Figure 15(Step S2008, "oxidation annealing"). During the process from the formation of the oxide semiconductor film 140 to the formation of the gate insulating film 150 on the oxide semiconductor layer 144, a large number of oxygen defects are generated on the upper surface 141 and side surfaces of the oxide semiconductor layer 144. Through the oxidation annealing described above, the oxygen released from the gate insulating films 120 and 150 is supplied to the oxide semiconductor layer 144, and the oxygen defects are repaired.

[0130] Oxygen released from the gate insulating film 120 by oxidation annealing is blocked by the metal oxide layer 132, thus preventing oxygen from being readily supplied to the lower surface of the oxide semiconductor layer 144. Oxygen released from the gate insulating film 120 diffuses from the region where the metal oxide layer 132 is not formed to the gate insulating film 150 disposed above the gate insulating film 120, and then reaches the oxide semiconductor layer 144 via the gate insulating film 150. As a result, oxygen released from the gate insulating film 120 is not readily supplied to the lower surface of the oxide semiconductor layer 144, but is mainly supplied to the side and upper surfaces of the oxide semiconductor layer 144. Furthermore, oxygen released from the gate insulating film 150 by oxidation annealing is supplied to the upper and side surfaces of the oxide semiconductor layer 144. During the aforementioned oxidation annealing, hydrogen is sometimes released from the gate insulating films 110 and 120, but this hydrogen is blocked by the metal oxide layer 132.

[0131] As described above, by means of oxidation annealing, it is possible to suppress the supply of oxygen to the lower surface of the oxide semiconductor layer 144 where the amount of oxygen defects is small, while simultaneously supplying oxygen to the upper surface 141 and the sides of the oxide semiconductor layer 144 where the amount of oxygen defects is large.

[0132] Similarly, in the oxidation annealing described above, the oxygen injected into the gate insulating film 150 is blocked by the metal oxide film 190, thus suppressing its release into the atmosphere. Therefore, through this oxidation annealing, the oxygen is efficiently supplied to the oxide semiconductor layer 144, and the oxygen defect is repaired.

[0133] Next, after oxidation annealing, the metal oxide film is etched (removed) at 190°. Figure 15 The step S1015 shown is "MO removal". The etching of the metal oxide film 190 can be performed using either wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. This etching removes the metal oxide film 190 formed over the entire surface. In other words, the removal of the metal oxide film 190 is performed without using a mask. Furthermore, this etching removes at least, from a top-down view, all of the metal oxide film 190 overlapping with the oxide semiconductor layer 144 formed in a certain pattern.

[0134] Then, a gate electrode 160 is formed on the gate insulating film 150. Figure 15The process shown in step S1009, "Top GE Formation," is similar to... Figure 3 Steps S1009 to S1013 are the same as those shown, so their description is omitted. By going through steps S1009 to S1013, a process can be formed. Figure 15 The semiconductor device 10 shown.

[0135] For the semiconductor device 10 manufactured by the above-described manufacturing method, compared with the manufacturing method of the semiconductor device 10 described in the first embodiment, the oxygen defects contained in the oxide semiconductor layer 144 can be further reduced. Therefore, for the semiconductor device 10 described in this embodiment, a mobility of 50 cm⁻¹ can be obtained within the range where the channel length L of the channel region 144CH is 2 μm or more and 4 μm or less, and the channel width of the channel region 144CH is 2 μm or more and 25 μm or less. 2 / Vs and above, 55cm 2 / Vs or above, or 60cm 2 Electrical characteristics above / Vs.

[0136] In the first and second embodiments, plasma treatment can be performed after the metal oxide film 130 is formed. In this specification, plasma treatment refers to a process in which plasma is generated within a space where the substrate to be treated is disposed, thereby exposing the substrate to plasma. Plasma treatment can be performed, for example, by anti-sputtering based on a sputtering apparatus or by etching using an inductively coupled plasma (ICP) apparatus.

[0137] Backsputtering involves applying voltage to the substrate side using an RF power supply under an argon atmosphere instead of applying voltage to the target side, creating plasma near the substrate. This allows ions to collide with the substrate surface, thereby modifying the surface. In cases of plasma treatment using backsputtering, for example, argon gas is introduced into the chamber to generate plasma before sputtering an oxide semiconductor film 140. Etching based on inductively coupled plasma modifies the substrate surface through ions and free radicals present in the plasma.

[0138] The surface of the metal oxide film 130 is modified by plasma treatment. Here, surface modification means either a change in the chemical composition of the surface of the metal oxide film 130, or a decrease in the surface roughness of the metal oxide film 130.

[0139] The state of the surface-modified metal oxide film 130 can be determined by the size of its water contact angle. By plasma treatment of the surface of the metal oxide film 130, the water contact angle of the metal oxide film 130 decreases. The water contact angle of the surface of the plasma-treated metal oxide film 130 becomes 20° or less, preferably 15° or less, and more preferably 10° or less. In this specification, the water contact angle is the value measured in accordance with ISO 19403-2:2017. When the metal oxide film 130 is treated by back sputtering as plasma treatment, the water contact angle becomes 20° or less. Furthermore, when the metal oxide film 130 is treated by etching based on inductively coupled plasma, the water contact angle becomes 15° or less. It should be noted that the lower limit for measuring the water contact angle is 2°.

[0140] The surface of the metal oxide film 130 can be removed by plasma treatment. The amount of surface material removed from the metal oxide film 130 is, for example, 1 nm to 10 nm or 1 nm to 5 nm.

[0141] Furthermore, plasma treatment can reduce the surface roughness of the metal oxide film 130. The surface roughness of the metal oxide film 130 (e.g., arithmetic mean roughness (Ra)) can be set to less than 1 nm, for example. The surface roughness can be evaluated using atomic force microscopy (AFM).

[0142] In this modified example, the surface of the metal oxide film 130 is modified. An oxide semiconductor film 140 with low crystal content is formed on the modified surface of the metal oxide film 130. Then, by performing OS annealing on the patterned oxide semiconductor layer 142, the crystallization at the interface between the metal oxide film 130 and the oxide semiconductor layer 144 is suppressed by hydroxyl groups and water during the crystallization of the oxide semiconductor layer 142. That is, the interface energy level density at the interface between the metal oxide film 130 and the oxide semiconductor layer 144 can be further reduced. Therefore, the reliability of the semiconductor device 10 can be further improved.

[0143] <Third Embodiment>

[0144] use Figures 17-20 The following describes a display device 20 that uses the semiconductor device 10 according to an embodiment of the present invention. In the embodiments shown below, the configuration of the circuit in which the semiconductor device 10 described in the first embodiment is applied to a liquid crystal display device will be described.

[0145] [Overview of display device 20]

[0146] Figure 17 This is a top view illustrating an outline of a display device 20 according to an embodiment of the present invention. Figure 17 As shown, the display device 20 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit board (FPC 330), and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. In the liquid crystal region 22 surrounded by the sealing portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 22 is the region that overlaps with the liquid crystal element 311 described later when viewed from above.

[0147] The sealing region 24, where the sealing portion 310 is provided, is the area surrounding the liquid crystal region 22. The FPC 330 is disposed on the terminal region 26. The terminal region 26 is the area of ​​the array substrate 300 exposed from the opposing substrate 320, and is disposed outside the sealing region 24. The outside of the sealing region 24 refers to the area where the sealing portion 310 is provided and the area surrounded by the sealing portion 310. The IC chip 340 is disposed on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0148] [Circuit configuration of display device 20]

[0149] Figure 18 This is a block diagram illustrating the circuit configuration of a display device 20 according to an embodiment of the present invention. Figure 18 As shown, a source driving circuit 302 is disposed adjacent to the liquid crystal region 22 where the pixel circuit 301 is disposed in the second direction D2 (column direction), and a gate driving circuit 303 is disposed adjacent to the liquid crystal region 22 in the first direction D1 (row direction). The source driving circuit 302 and the gate driving circuit 303 are disposed in the aforementioned sealed region 24. However, the region where the source driving circuit 302 and the gate driving circuit 303 are disposed is not limited to the sealed region 24; it can be any region as long as it is outside the region where the pixel circuit 301 is disposed.

[0150] Source wiring 304 extends from source driving circuit 302 in a second direction D2 and is connected to a plurality of pixel circuits 301 arranged along the second direction D2. Gate electrode 160 extends from gate driving circuit 303 in a first direction D1 and is connected to a plurality of pixel circuits 301 arranged along the first direction D1.

[0151] Terminal portion 306 is provided in terminal area 26. Terminal portion 306 is connected to source drive circuit 302 by connection wiring 307. Similarly, terminal portion 306 is connected to gate drive circuit 303 by connection wiring 307. The terminal portion 306 is connected to FPC 330, thereby connecting an external device to FPC 330 to display device 20, and each pixel circuit 301 provided in display device 20 is driven by signals from the external device.

[0152] The semiconductor device 10 shown in the first and second embodiments is used as a transistor included in the pixel circuit 301, the source driving circuit 302, and the gate driving circuit 303.

[0153] [Pixel circuit 301 of display device 20]

[0154] Figure 19 A circuit diagram illustrating the pixel circuitry of a display device 20 according to an embodiment of the present invention is provided. Figure 19 As shown, the pixel circuit 301 includes components such as a semiconductor device 10, a holding capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to the source electrode 201. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to the holding capacitor 350 and the liquid crystal element 311. In this embodiment, for ease of explanation, the electrode represented by the reference numeral "201" is called the source electrode, and the electrode represented by the reference numeral "203" is called the drain electrode. However, the electrode represented by the reference numeral "201" may function as the drain electrode, and the electrode represented by the reference numeral "203" may function as the source electrode.

[0155] [Composition of display device 20]

[0156] Figure 20 This is a cross-sectional view of a display device 20 according to an embodiment of the present invention. Figure 20 As shown, the display device 20 is a display device 20 that uses the semiconductor device 10.

[0157] like Figure 20 and Figure 21As shown, a gate electrode 105 is provided on the substrate 100. The gate electrode 105 is in a floating potential state. For the material of the gate electrode 105, please refer to the description of the source electrode 201 and the drain electrode 203. Furthermore, an oxide semiconductor layer 144 is provided on the gate electrode 105. A gate electrode 160 extends along a first direction D1 on the oxide semiconductor layer 144. The region of the gate electrode 160 that overlaps with the oxide semiconductor layer 144 functions as the gate electrode 160. A source wiring 304 and a drain electrode 203 are provided on the gate electrode 160. The source wiring 304 is connected to the source region 144S via an opening 171. The region of the source wiring 304 that is connected to the oxide semiconductor layer 144 functions as the source electrode 201. Furthermore, the drain electrode 203 is connected to the drain region 144D via an opening 173.

[0158] An insulating film 360 is disposed on the source electrode 201 and the drain electrode 203. A common electrode 370, which is commonly disposed for multiple pixels, is disposed on the insulating film 360. An insulating film 380 is disposed on the common electrode 370. An opening 381 is provided in the insulating films 360 and 380. A pixel electrode 390 is disposed on the insulating film 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0159] Figure 21 This is a top view of the pixel electrode 390 and common electrode 370 of a display device 20 according to an embodiment of the present invention. Figure 21 As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 when viewed from above, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a lateral electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. Through this lateral electric field, the liquid crystal molecules contained in the liquid crystal element 311 operate, thereby determining the grayscale of the pixel.

[0160] In this embodiment, the semiconductor device 10 is used in the configuration of the pixel circuit 301, but the semiconductor device 10 can also be used in peripheral circuits that include the source driving circuit 302 and the gate driving circuit 303.

[0161] <Fourth Embodiment>

[0162] use Figure 22 and Figure 23 This paper describes a display device 20 that uses the semiconductor device 10 according to an embodiment of the present invention. In this embodiment, the configuration of a circuit in which the semiconductor device 10 described in the first embodiment is applied to an organic EL display device will be described. The outline and circuit configuration of the display device 20 are as follows: Figure 22 and Figure 23The same applies as shown, therefore the explanation is omitted.

[0163] [Pixel circuit 301 of display device 20]

[0164] Figure 22 A circuit diagram illustrating the pixel circuit of a display device 20 according to an embodiment of the present invention is provided. Figure 22 As shown, the pixel circuit 301 includes components such as a driving transistor 11, a selection transistor 12, a holding capacitor 210, and a light-emitting element DO. The driving transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to the signal line 211, and the gate electrode of the selection transistor 12 is connected to the gate line 212. The source electrode of the driving transistor 11 is connected to the anode power supply line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power supply line 214. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The holding capacitor 210 is connected to both the gate electrode and the drain electrode of the driving transistor 11. A grayscale signal determining the light intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting the pixel row to which the aforementioned grayscale signal is written is supplied to the gate line 212.

[0165] [Cross-sectional structure of display device 20]

[0166] Figure 23 This is a cross-sectional view of a display device 20 according to an embodiment of the present invention. Figure 23 The configuration of the display device 20 shown is similar to Figure 20 The display device 20 shown is similar, but Figure 23 The structure in the display device 20 that is above the insulating film 360 is... Figure 20 The structure in the display device 20 that is positioned above the insulating film 360 is different. The following is about... Figure 23 The configuration of the display device 20 shown is related to... Figure 20 The display device 20 shown has the same configuration, so the description is omitted. Instead, the differences between the two will be explained.

[0167] like Figure 23As shown, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating film 360. The pixel electrode 390 is disposed above the insulating film 360 and inside the opening 381. An insulating film 362 is disposed above the pixel electrode 390. An opening 363 is disposed in the insulating film 362. The opening 363 corresponds to the light-emitting area. That is, the insulating film 362 defines the pixel. The light-emitting layer 392 and the common electrode 394 are disposed on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are disposed separately for each pixel. On the other hand, the common electrode 394 is commonly disposed in multiple pixels. The light-emitting layer 392 uses different materials depending on the display color of the pixel.

[0168] In the third and fourth embodiments, examples were given of applying the semiconductor device described in the first embodiment to a liquid crystal display device and an organic EL display device. However, the semiconductor device can also be applied to display devices other than these display devices (e.g., self-emissive display devices other than organic EL display devices or electronic paper display devices). In addition, the above-described semiconductor device 10 can be applied to display devices ranging from small and medium-sized to large-sized without particular limitation.

[0169] Example

[0170] (Example 1)

[0171] In this embodiment, the results of verifying the etch resistance of the oxide semiconductor film 140 are described.

[0172] In this embodiment, according to the second implementation method Figure 15 After the semiconductor device 10 is manufactured in the sequence shown, an optical microscope is used to take a photograph of the surface of the semiconductor device to confirm the presence or absence of the oxide semiconductor layer 144.

[0173] In this embodiment, Figure 15 In step S1002 shown, a 10 nm aluminum oxide film is formed as a metal oxide film 130. Next, in... Figure 15 In step S1003 shown, an IGO-based sputtering target is used to deposit an oxide semiconductor film 140 at a substrate temperature below 100°C. The conditions regarding oxygen partial pressure and oxide semiconductor film thickness are modified.

[0174] With an oxygen partial pressure of 2%, the film thickness of the oxide semiconductor film was changed to 20 nm, 30 nm, and 40 nm. Furthermore, with an oxygen partial pressure of 4%, the film thickness was changed to 20 nm, 30 nm, and 40 nm. Finally, with an oxygen partial pressure of 5%, the thickness was set to 30 nm.

[0175] exist Figure 15 In step S1004 shown, a photoresist mask is used and oxalic acid is used to etch the oxide semiconductor film 140. Figure 15 In step S1005, OS annealing is performed. Then, in Figure 15 In step S1006 shown, the oxide semiconductor layer 144 is used as a mask, and the metal oxide film 130 is etched using DHF. Hereinafter, according to... Figure 15 Semiconductor device 10 was fabricated in the order shown.

[0176] exist Figure 15 After the process in step S1013 shown is completed, an optical microscope is used to take a photograph of the surface of the semiconductor device. Figure 24 A photograph taken using an optical microscope to capture the surface of a semiconductor device.

[0177] like Figure 24 As shown, when the oxygen partial pressure is 2%, it was confirmed that the oxide semiconductor layer disappeared during etching for any of the film thicknesses of 20 nm, 30 nm, and 40 nm. Furthermore, when the oxygen partial pressure is 4% and 5%, it was confirmed that the oxide semiconductor layer did not disappear but remained.

[0178] When the oxygen partial pressure is 2%, it is believed that even after heat treatment following the deposition of the oxide semiconductor film, sufficient crystallization is not possible. Therefore, it is assumed that the oxide semiconductor layer disappears during etching of the metal oxide film 130. On the other hand, when the oxygen partial pressure is 3% or higher, it is believed that the oxide semiconductor layer is sufficiently crystallized through heat treatment following the deposition of the oxide semiconductor film, thus leaving an oxide semiconductor layer.

[0179] (Example 2)

[0180] Next, the method according to the first embodiment will be described. Figure 3 The results of verifying the electrical characteristics of the semiconductor device 10 manufactured in the order shown.

[0181] In this embodiment, Figure 3 In step S1003 shown, an IGO-based sputtering target is used to deposit an oxide semiconductor film 140 at a substrate temperature below 100°C. The conditions regarding oxygen partial pressure and oxide semiconductor film thickness are modified.

[0182] With an oxygen partial pressure of 5%, the film thickness of the oxide semiconductor film was changed to 10 nm, 20 nm, and 30 nm.

[0183] exist Figure 3In step S1004 shown, a photoresist mask is used and the oxide semiconductor film 140 is etched. Figure 3 In step S1005, OS annealing is performed. The following is in accordance with... Figure 3 Semiconductor device 10 was fabricated in the order shown.

[0184] Next, the electrical characteristics of the semiconductor device 10 are measured. The conditions for measuring the electrical characteristics of the semiconductor device 10 are as follows.

[0185] • Channel region dimensions: W / L = 4.5μm / 3μm

[0186] Source-drain voltage: 0.1V, 10V

[0187] • Gate voltage: -15V to +15V

[0188] • Measurement environment: room temperature, dark room

[0189] • Thickness of oxide semiconductor layer: 10nm, 20nm, 30nm

[0190] • Measurement locations: 26 points within the substrate surface

[0191] Figure 25 Electrical characteristics (Id-Vg characteristics) of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 10 nm. Figure 26 Electrical characteristics (Id-Vg characteristics) of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 20 nm. Figure 27 The electrical characteristics (Id-Vg characteristics) of a semiconductor device 10 having an oxide semiconductor layer with a film thickness of 30 nm are shown. The horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current (Id).

[0192] like Figure 25 As shown, the semiconductor device 10 with an oxide semiconductor layer having a film thickness of 10 nm did not exhibit switching characteristics. This is believed to be because, with an oxide semiconductor layer thickness of 10 nm, the oxide semiconductor layer did not crystallize but remained amorphous after heat treatment. Figure 26 and Figure 27 In this process, the semiconductor device 10 exhibits excellent electrical characteristics. The semiconductor device 10, with an oxide semiconductor layer having a thickness of 20 nm, achieves a mobility of 31.5 cm⁻¹. 2 / Vs. The mobility of semiconductor device 10, having an oxide semiconductor layer with a film thickness of 30 nm, is 31.4 cm. 2 / Vs.

[0193] (Example 3)

[0194] Next, the description of the second embodiment will be provided. Figure 15 The results of verifying the electrical characteristics of the semiconductor device 10 manufactured in the sequence shown are presented. In this embodiment, the conditions of oxygen partial pressure and film thickness are further modified in detail, and the results of verifying intrinsic mobility and reliability are explained.

[0195] In this embodiment, Figure 15 In step S1002 shown, an aluminum oxide film is formed as a metal oxide film 130. Additionally, in Figure 15 In step S1003 shown, an IGO-based sputtering target is used to deposit an oxide semiconductor film 140 at a substrate temperature below 100°C. The conditions regarding oxygen partial pressure and oxide semiconductor film thickness are modified.

[0196] For cases with oxygen partial pressures of 3%, 4%, and 5%, the film thickness of the oxide semiconductor film is changed to 15nm, 20nm, 25nm, and 30nm, respectively.

[0197] exist Figure 15 In step S1004 shown, a photoresist mask is used, and oxalic acid is used to etch the oxide semiconductor film 140. Figure 15 In step S1005, OS annealing is performed. Then, in Figure 15 In step S1006 shown, the oxide semiconductor layer 144 is used as a mask, and the metal oxide film 130 is etched using DHF. Hereinafter, according to... Figure 15 Semiconductor device 10 was fabricated in the order shown.

[0198] Next, the electrical characteristics of the semiconductor device 10 fabricated in this embodiment are measured. The conditions for measuring the electrical characteristics of the semiconductor device 10 are as follows.

[0199] • Dimensions of the 144CH channel region: W / L = 4.5μm / 3μm

[0200] Source-drain voltage: 0.1V, 10V

[0201] • Gate voltage: -15V to +15V

[0202] • Measurement environment: room temperature, dark room

[0203] • Thickness of oxide semiconductor layer: 10nm, 20nm, 30nm

[0204] • Measurement locations: 26 points within the substrate surface

[0205] Figure 28 The intrinsic mobility is given by various film formation conditions relative to the oxide semiconductor film. The horizontal axis represents the film formation conditions of the oxide semiconductor film, and the vertical axis represents the intrinsic mobility.

[0206] according to Figure 28 The results confirmed the following trend: the lower the oxygen partial pressure during oxide semiconductor film formation, the greater the intrinsic mobility; and the thinner the oxide semiconductor layer, the greater the intrinsic mobility. In other words, it was confirmed that the lower the oxygen partial pressure during oxide semiconductor film formation and the thinner the oxide semiconductor layer, the higher the intrinsic mobility of the oxide semiconductor layer.

[0207] Next, the results of reliability tests conducted on the semiconductor device fabricated in this embodiment will be explained. Here, PBTS and NBTIS (Negative Bias Illumination Temperature Stress) were performed as reliability tests. PBTS involves applying a positive voltage to the gate electrode of the semiconductor device and evaluating the change in threshold voltage before and after the voltage application. NBTIS involves applying a negative voltage to the gate electrode of the semiconductor device and evaluating the change in threshold voltage before and after the voltage application.

[0208] Figure 29 ΔVth represents the variation of the threshold voltage relative to various film formation conditions of the oxide semiconductor film. The horizontal axis represents the film formation conditions of the oxide semiconductor film, and the vertical axis represents the variation of the threshold voltage.

[0209] according to Figure 29 The results confirmed the following trend: the lower the oxygen partial pressure during oxide semiconductor film deposition, the smaller the threshold voltage variation; and the thinner the oxide semiconductor layer, the smaller the threshold voltage variation. In other words, it was confirmed that the lower the oxygen partial pressure during oxide semiconductor film deposition and the thinner the oxide semiconductor layer, the higher the reliability of the semiconductor device.

[0210] The above-described embodiments and modifications, which are embodiments of the present invention, can be appropriately combined and implemented as long as they do not contradict each other. In addition, embodiments obtained by adding, deleting, or changing the constituent elements, or adding, omitting, or changing the conditions, based on the semiconductor devices and display devices of the various embodiments and modifications, are also included within the scope of the present invention as long as they possess the spirit of the present invention.

[0211] It should be understood that the effects that are clearly defined according to the description in this specification or that can be easily predicted by those skilled in the art, even if they are different from the effects obtained by the various embodiments described above, are of course obtainable by the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first metal oxide film with aluminum as the main component is formed on the substrate; An amorphous oxide semiconductor film is formed on the first metal oxide film under an oxygen partial pressure of 3% to 5%. The oxide semiconductor film is processed into a patterned oxide semiconductor layer; The oxide semiconductor layer is crystallized by subjecting the patterned oxide semiconductor layer to a first heat treatment. The first metal oxide film is processed using the crystallized oxide semiconductor layer as a mask; A gate insulating film is formed on the oxide semiconductor layer. A gate electrode is formed on the gate insulating film. The oxide semiconductor film has a thickness greater than 10 nm and less than 30 nm.

2. The method for manufacturing a semiconductor device as described in claim 1, wherein, The temperature at which the oxide semiconductor film is formed is below 100°C.

3. The method for manufacturing a semiconductor device as described in claim 2, wherein, The temperature during the first heat treatment is above 300°C and below 500°C.

4. The method for manufacturing a semiconductor device as described in claim 1, wherein, The thickness of the first metal oxide film is more than 1 nm and less than 50 nm.

5. The method for manufacturing a semiconductor device as described in claim 1, wherein, After the gate insulating film is formed, a second metal oxide film with aluminum as the main component is formed, and a second heat treatment is performed.

6. The method for manufacturing a semiconductor device as described in claim 1, wherein, The oxide semiconductor layer contains indium and at least one other metal element. The ratio of indium to the indium and at least one other metal element is 50% or more.

7. The method for manufacturing a semiconductor device as claimed in claim 1, wherein, The crystallized oxide semiconductor layer has a polycrystalline structure.

Images