Method for forming semiconductor structure and method for manufacturing semiconductor device

Abstract

The application provides a semiconductor structure forming method and a semiconductor device manufacturing method, and the forming method comprises the following steps: providing a silicon substrate, a first layer structure and a second layer structure are sequentially formed on the silicon substrate; forming a fin-shaped conductive channel, a fin-shaped spacing layer and a sheet-shaped conductive channel, the ratio of the width of the fin-shaped spacing layer to the thickness of the first spacing layer is 0.8:1-1:0.5; forming a virtual gate; etching to expose a source-drain region, and forming a plurality of gaps in the fin-shaped spacing layer and the first spacing layer near the source-drain region; and forming an isolation structure in the plurality of gaps. In the application, the height of the gap formed in the first spacing layer is the same as or close to the width of the gap formed in the fin-shaped spacing layer, so that the isolation structure can be simultaneously formed in the gaps of the first spacing layer and the second spacing layer, thereby reducing the process difficulty of forming the isolation structure of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for forming a semiconductor structure and a method for fabricating a semiconductor device. Background Technology

[0002] In semiconductor structures that include p-type and n-type field-effect transistors arranged vertically, the use of all-around gates ensures electrical integrity while significantly saving chip area, enhancing device drive current, and improving chip device integration.

[0003] However, when forming an isolation structure (used to isolate the gate structure and source / drain structure) between the gaps between n-type and p-type field-effect transistors, between the channels within an n-type field-effect transistor, and between the channels within a p-type field-effect transistor, the formation of the isolation structure is often greatly hindered by the large differences in the gap height (process window) between these three types. This problem is particularly pronounced when the aspect ratio of the semiconductor structure is further increased. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a semiconductor structure and a method for fabricating a semiconductor device, so as to reduce the process difficulty of forming an isolation structure between the source / drain structure and the gate structure of a semiconductor structure.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0006] A silicon substrate is provided, wherein a first stacked structure and a second stacked structure are disposed on the first stacked structure, the first stacked structure includes a first spacer layer and a first channel material layer stacked alternately in sequence, and the second stacked structure includes a second spacer layer and a second channel material layer stacked alternately in sequence.

[0007] The second layered structure is used to form a fin-shaped conductive channel and a fin-shaped spacer layer, and the first layered structure is used to form a sheet-shaped conductive channel. The ratio of the width of the fin-shaped spacer layer to the thickness of the first spacer layer is 0.8:1 to 1:0.5.

[0008] A virtual gate is formed to cover the silicon substrate and fill the space above the fin-shaped conductive channel. The virtual gate covers the gate region and source / drain region of the semiconductor structure.

[0009] Remove the dummy gate, finned conductive channel, and sheet-like conductive channel from the source / drain regions, and form a plurality of gaps recessed in the finned spacer layer and the first spacer layer near the source / drain regions; and

[0010] An isolation structure is formed within a plurality of the aforementioned gaps, the isolation structure being used to isolate the gate structure and source / drain structure of the semiconductor structure.

[0011] Optionally, the first spacer layer, the first channel material layer, the second spacer layer, and the second channel material layer are all silicon-containing superlattice layers, and the conductivity types of the first channel material layer and the second channel material layer are opposite.

[0012] Optionally, the first spacer layer and the second spacer layer are made of the same material, the first channel material layer is of N-type conductivity, and the second channel material layer is of P-type conductivity.

[0013] Optionally, the step of forming the sheet-like conductive channel includes:

[0014] The second layered structure sequentially forms a first material layer, a first mandrel layer, a second material layer, and a second mandrel layer;

[0015] The second mandrel layer is graphically represented to form at least one second mandrel;

[0016] At least one first sidewall structure is formed on the sidewall of the second mandrel, the width of the first sidewall structure being the same as the width of the fin-shaped conductive channel;

[0017] The second material layer, the second mandrel, and the first mandrel layer are etched sequentially to remove the second mandrel and form the first mandrel in the first mandrel layer;

[0018] Etch the first material layer and the second material layer, and remove the first sidewall structure to form at least one fin-like structure with the remaining second material layer; and,

[0019] The first stacked structure and the second stacked structure are etched using the first mandrel as a mask, and the remaining first channel material layer is used as the sheet-like conductive channel.

[0020] Optionally, the step of forming the fin-shaped conductive channel includes:

[0021] Using the fin-like structure as a mask, the first core, the first material layer, and the second stacked structure are etched sequentially, with the remaining first channel material layer serving as the fin-like conductive channel and the remaining second spacer layer serving as the fin-like spacer layer.

[0022] Optionally, the material of the first sidewall structure includes titanium oxide, and both the first material layer and the second material layer include a silicon nitride layer and a silicon oxide layer formed sequentially.

[0023] Optionally, the plurality of gaps include a first gap formed in the first spacer layer and a second gap formed in the fin-shaped spacer layer, wherein the ratio of the thickness of the first gap to the width of the second gap is 0.8:1 to 1:0.5.

[0024] Optionally, both the first spacer layer and the second spacer layer are made of germanium-silicon, and both the first channel material layer and the second channel material layer are made of silicon, so that the first gap and the second gap are formed simultaneously when the virtual gate, fin conductive channel and sheet conductive channel of the source and drain regions are removed.

[0025] Optionally, the isolation structure is made of silicon nitride, and the isolation structure is formed in the first gap and the second gap using an ALD process.

[0026] According to another aspect of the present invention, a method for fabricating a semiconductor device is also provided, the method for fabricating a semiconductor device including the semiconductor structure formation method described above.

[0027] In summary, the semiconductor structure formation method and semiconductor device fabrication method provided by the present invention, by forming a fin-shaped spacer layer between the fin-shaped conductive channel and the sheet-shaped conductive channel, and the ratio of the width of the fin-shaped spacer layer to the thickness of the first spacer layer in the first stacked structure is 0.8:1 to 1:0.5, can make the height (thickness) of the gap formed in the first spacer layer the same or nearly the same as the width of the gap formed in the fin-shaped spacer layer. Thus, an isolation structure can be formed simultaneously in the gap between the first spacer layer and the second spacer layer, thereby reducing the process difficulty of forming the isolation structure of the semiconductor structure. Attached Figure Description

[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0029] Figure 1 This is a flowchart of the method for forming a semiconductor structure provided in Embodiment 1;

[0030] Figures 2 to 11 This embodiment provides a schematic diagram of the corresponding steps of a method for forming a semiconductor structure.

[0031] In the attached image:

[0032] 10-Silicon substrate;

[0033] 20 - First layered structure; 21 - First spacer layer; 22 - First channel material layer; 221 - Sheet-shaped conductive channel;

[0034] 30 - Second stacked structure; 31 - Second spacer layer; 32 - Second channel material layer; 321 - Fin-shaped conductive channel; 311 - Fin-shaped spacer layer;

[0035] 41-First material layer; 41a-Silicon nitride layer; 41b-Silicon oxide layer; 42-First mandrel layer; 43-Second material layer; 43a-Silicon nitride layer; 43b-Silicon oxide layer; 44-Second mandrel layer; 45-First sidewall structure; 441-Second mandrel; 421-First mandrel; 442-Trench; 431-Fin structure;

[0036] 51-Virtual gate; 52-First gap; 53-Second gap; 54-Isolation structure;

[0037] D1 - First direction; D2 - Second direction. Detailed Implementation

[0038] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0039] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0040] Example 1

[0041] Figure 1 This is a flowchart of the method for forming a semiconductor structure provided in Example 1.

[0042] like Figure 1 As shown, the method for forming a semiconductor structure provided in this embodiment includes the following steps:

[0043] S01: A silicon substrate is provided, wherein a first stacked structure and a second stacked structure are provided on the silicon substrate, the first stacked structure includes a first spacer layer and a first channel material layer stacked alternately in sequence, and the second stacked structure includes a second spacer layer and a second channel material layer stacked alternately in sequence.

[0044] S02: A finned conductive channel and a finned spacer layer are formed using the second stacked structure, and a sheet-like conductive channel is formed using the first stacked structure, wherein the ratio of the width of the finned spacer layer to the thickness of the first spacer layer is 0.8:1 to 1:0.5.

[0045] S03: A virtual gate is formed to cover the silicon substrate and fill the space above the fin-shaped conductive channel. The virtual gate covers the gate region and source / drain region of the semiconductor structure.

[0046] S04: Remove the virtual gate, fin-shaped conductive channel and sheet-shaped conductive channel in the source and drain regions, and form a plurality of gaps in the fin-shaped spacer layer and the first spacer layer near the source and drain regions;

[0047] S05: An isolation structure is formed within a plurality of the aforementioned gaps, the isolation structure being used to isolate the gate structure and source / drain structure of the semiconductor structure.

[0048] Figures 2 to 11 The diagram below shows the corresponding structural steps of the semiconductor structure formation method provided in Example 1. Next, we will combine... Figures 2 to 11 The method for forming the semiconductor structure is described in detail.

[0049] First, please refer to Figure 2 In step S01, a silicon substrate 10 is provided, on which a first stacked structure 20 and a second stacked structure 30 are sequentially formed. The first stacked structure 20 includes alternating layers of a first spacer layer 21 and a first channel material layer 22, and the second stacked structure 30 includes alternating layers of a second spacer layer 31 and a second channel material layer 32.

[0050] The silicon substrate 10 can be any suitable silicon substrate material well known to those skilled in the art, such as at least one of the following: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, a single-crystal silicon substrate is used as an example to illustrate the silicon substrate 10.

[0051] Each layer in the first stacked structure 20 and the second stacked structure 30 formed on the silicon substrate 10 can be a superlattice structure layer including silicon formed by epitaxial process. A transistor of semiconductor structure is formed in the first stacked structure 20 on the silicon substrate 10, and another complementary transistor of semiconductor structure is formed in the second stacked structure 30 on the first stacked structure 20. That is, the first channel material layer 22 and the second channel material layer 32 have opposite conductivity types. During etching, the first spacer layer 21 and the second spacer layer 31 have relatively significant etching selectivity relative to the first channel material layer 22 and the second channel material layer 32, for example, 4:1 to 15:1, so as to facilitate the subsequent formation of the gate structure (virtual gate).

[0052] In this embodiment, a p-type field-effect transistor can be formed using a first stacked structure 20, which includes two alternately stacked first spacer layers 21 and two first channel material layers 22. An n-type field-effect transistor can be formed using a second stacked structure 30, which includes a second spacer layer 31 and a second channel material layer 32. The first channel material layer 22 can be made of silicon or silicon germanium (SiGe), the first spacer layer 21 can be made of silicon germanium, the second channel material layer 32 can be made of silicon or silicon carbide (SiC), and the second spacer layer 31 can be made of silicon germanium. The silicon germanium has a different germanium content than the second and third silicon germanium to achieve etching selectivity among the three. It is easy to understand that the first spacer layer 21 serves as an isolation layer within the p-type field-effect transistor, and the second spacer layer 31 serves as an isolation layer (boundary isolation) between the p-type and n-type field-effect transistors. The thickness of the second spacer layer 31 is greater than the thickness of the first spacer layer 21. Moreover, the thicker (higher) the second spacer layer 31 is, the better it is for shielding the interference between p-type field-effect transistors and n-type field-effect transistors. In practice, the thickness of the second spacer layer 31 can be 3 to 5 times the thickness of the first spacer layer 21.

[0053] Preferably, the first spacer layer 21 and the second spacer layer 31 can be made of the same or nearly the same material, that is, the germanium content of the second germanium silicon and the third germanium silicon is the same, so as to facilitate the subsequent simultaneous etching of the first spacer layer 21 and the second spacer layer 31, thereby simplifying the manufacturing process.

[0054] Furthermore, taking the example of an n-type field-effect transistor formed in the second stacked structure 30 with a fin-shaped channel, the thickness of the second channel material layer 32 can be thicker than the thickness of the first channel material layer 22. Of course, if the thickness of the second channel material layer 32 is relatively thin, the channel shape of the formed n-type field-effect transistor can be linear.

[0055] Next, step S02 is performed to form a patterned mask layer on the second stacked structure 30. Using the patterned mask layer, a fin-shaped conductive channel 321 and a fin-shaped spacer layer 311 are formed in the second stacked structure 30, and a sheet-shaped conductive channel 221 is formed in the first stacked structure 20. The ratio of the width of the fin-shaped spacer layer 311 to the thickness of the first spacer layer 21 is 0.8:1 to 1:0.5.

[0056] The patterned mask layer may include a first material layer 41, a first core layer 42, a second material layer 43 and a second core layer 44 formed sequentially. The second core layer 44 is used to form a fin-shaped conductive channel 321 and a fin-shaped spacer layer 311, and the first core layer 42 is used to form a sheet-like conductive channel 221.

[0057] In this embodiment, taking the formation of a semiconductor structure on a silicon substrate 10 as an example, wherein the p-type field-effect transistor of the semiconductor structure has two sheet-like conductive channels 221 and the n-type field-effect transistor has two fin-like conductive channels 321, the formation steps may include, for example:

[0058] Please refer to Figure 3 A first material layer 41, a first core layer 42, a second material layer 43, and a second core layer 44 are formed on the second channel material layer 32. The first material layer 41 and the second material layer 43 may each include a silicon nitride layer and a silicon oxide layer formed sequentially. The first core layer 42 and the second core layer 44 may both be made of polycrystalline silicon.

[0059] Please refer to Figure 4 A second mandrel layer 44 is patterned to form a second mandrel 441, and two first sidewall structures 45 are formed on the sidewalls of the second mandrel 441. The second mandrel 441 may be located in the middle region of the second material layer 43. The material of the first sidewall structure 45 is different from the other materials of the mask layer. The material of the first sidewall structure 45 may be, for example, titanium oxide (TiO2). The steps of forming the first sidewall structure 45 may be, for example, as follows: firstly, a first sidewall material layer covering the surface of the second material layer 43 and the outer wall of the second mandrel 441 is formed; then, the first sidewall material layer on the surface of the second material layer 43 and the top surface of the second mandrel 441 is etched away, and the remaining first sidewall material layer located on the sidewall of the second mandrel 441 serves as the first sidewall structure 45.

[0060] It should be noted that the first sidewall structure 45 is used to define the subsequent fin-shaped conductive channel 321 and fin-shaped spacer layer 311. The sum of the widths of the two first sidewall structures 45 and the first mandrel 421 is used to define the subsequent sheet-like conductive channel 221. That is, the width of the first sidewall structure 45 (i.e., the thickness of the first sidewall material layer) matches (is the same as or nearly the same as) the width of the fin-shaped conductive channel 321, and the sum of the widths of the two first sidewall structures 45 and the first mandrel 421 matches the width of the sheet-like conductive channel 221. Moreover, the width W of the first sidewall structure 45 (i.e., the width W of the fin-shaped spacer layer 311) is the same as or nearly the same as the thickness H of the first spacer layer 21 in the first laminated structure 20. For example, the ratio of the width W of the fin-shaped spacer layer 311 to the thickness H of the first spacer layer 21 is 0.8:1 to 1:0.5, so as to facilitate the subsequent synchronous formation of the isolation structure. Of course, in practice, the width W of the first side wall structure 45 can be appropriately increased to prevent dimensional loss during the downward transmission of the graphic.

[0061] Please refer to Figure 5 Using the first sidewall structure 45 and the second mandrel 441 as a mask, the second material layer 43 and the first mandrel layer 42 are etched, and the pattern is transferred to the second material layer 43 and the first mandrel layer 42 to expose part of the first material layer 41. The remaining first mandrel layer 42 is used as the first mandrel 421. Since the second mandrel 441 and the first mandrel layer 42 have the same material, the second mandrel 441 can be removed simultaneously when the first mandrel 421 is formed, and a groove 442 is formed between the two first sidewall structures 45 to expose the second material layer 43.

[0062] Please refer to Figure 6 The first material layer 41 is etched to transfer the pattern of the first mandrel 421 to the first material layer 41 to expose the surface of the second channel material layer 32. Since the material of the second material layer 43 can be the same as that of the first material layer 41, the second material layer 43 at the bottom of the trench 442 can also be etched simultaneously to extend the trench 442 downward to the surface of the first mandrel 421. Then the first sidewall structure 45 is removed, and the remaining second material layer 43 forms two fin structures 431.

[0063] Please refer to Figure 7 Using the fin-like structure 431 and the first mandrel 421 as masks, the first stacked structure 20 and the second stacked structure 30 are etched to expose a portion of the surface of the silicon substrate 10. The remaining first channel material layer 22 in the first stacked structure 20 is used as a sheet-like conductive channel 221, the width of which is the same as or nearly the same as the width of the first mandrel 421. The width of the remaining second stacked structure 30 is also the same as or nearly the same as the width of the first mandrel 421.

[0064] It should be noted that since each layer in the first stacked structure 20 and the second stacked structure 30 contains silicon, and the etching rates of the first spacer layer 21 and the second spacer layer 31 are greater than the etching rates of the first channel material layer 22 or the second channel material layer 32, during etching, the sidewalls of the first spacer layer 21 and the second spacer layer 31 will be recessed inward (not shown in the figure), which is beneficial for the subsequent removal of the first spacer layer 21 and the second spacer layer 31 to form a gate structure surrounding the conductive channel.

[0065] Please refer to Figure 8 Using two fin-like structures 431 as masks, the first mandrel 421, the first material layer 41, and the second stacked structure 30 are sequentially etched to expose the surface of the first stacked structure 20 (sheet-like conductive channel 221). The remaining second channel material layer 32 and second spacer layer 31 form two fin-like conductive channels 321 and two fin-like spacer layers 311. The width of the two fin-like conductive channels 321 and the two fin-like spacer layers 311 is the same as or nearly the same as the width of the fin-like structure 431 (i.e., the first sidewall structure 45). In practice, the first mandrel 421 and the first material layer 41 can be etched using the fin-like structure 431. That is, after the pattern of the fin-like structure 431 is transferred to the first mandrel 421 and the first material layer 41, the fin-like structure 431 can be removed to reduce the aspect ratio of subsequent etching, thereby reducing the difficulty of the etching process. Of course, after etching to form two fin-shaped conductive channels 321 and two fin-shaped spacer layers 311, the remaining first mandrel 421 and first material layer 41 can also be removed.

[0066] Next, please refer to Figure 9 In step S03, a virtual gate 51 is formed to cover the silicon substrate 10 and fill the space above the second conductive channel. The virtual gate 51 covers the gate region and source / drain region of the semiconductor structure.

[0067] In this embodiment, a post-gate process is used, that is, first a virtual gate 51 is formed, and a portion of the virtual gate 51 is used to cover the protective gate region. Then, an isolation structure 54 is formed between the gate region and the source / drain region. Next, the source / drain structure is formed. Then, the virtual gate 51 of the gate region is removed to form the gate structure (e.g., a gate all around).

[0068] The specific steps may include, for example, forming a third core material layer covering the silicon substrate 10 and the structure on the silicon substrate 10, filling it above the fin-shaped conductive channel 321, then performing a photolithography process to remove the third core material layer between adjacent semiconductor structures, so that the third core material layer covers the gate region and source / drain region of the semiconductor structure, and forming a second sidewall structure on the sidewall of the third core material layer to isolate adjacent semiconductor structures. The material of the second sidewall structure may be, for example, silicon nitride. The extension direction of the sheet-like conductive channel 221 and the fin-shaped conductive channel 321 is the second direction D2, the two fin-shaped conductive channels 321 are arranged along the first direction D1, and the gate region and source / drain region of the semiconductor structure are arranged along the second direction D2 (the extension direction of the conductive channel). Figure 9 This is a cross-sectional schematic diagram of the area near the interface between the gate region and the source / drain region of a semiconductor structure.

[0069] Preferably, the material of the third core material layer can be polycrystalline silicon, so that its material is similar to that of the first stacked structure 20 and the second stacked structure 30, in order to facilitate subsequent etching.

[0070] Next, please refer to Figure 10 In step S04, the virtual gate 51, the second stacked structure 30 and the first stacked structure 20 of the source and drain regions are etched away, and a number of gaps are formed in the fin spacer layer 311 and the first spacer layer 21 near the source and drain regions.

[0071] Specifically, a patterned photoresist layer can be formed, with openings in the patterned photoresist layer exposing the source / drain regions of the semiconductor structure. Dry etching removes the virtual gate 51, the second stacked structure 30, and the first stacked structure 20 within the openings (source / drain regions), exposing a portion of the surface of the silicon substrate 10 for subsequent formation of the source / drain structure of the semiconductor structure in the source / drain regions. Next, an isotropic etching process can be used to remove a portion of the first spacer layer 21 and a portion of the finned spacer layer 311 (second spacer layer 31) near the source / drain regions to form inwardly recessed gaps, allowing for the subsequent formation of an isolation structure 54 within the gaps to isolate the source / drain structure and the gate structure. The gap formed in the first spacer layer 21 can be a first gap 52, and the gap formed in the second spacer layer 31 can be a second gap 53. In one specific embodiment, since the first spacer layer 21 and the second spacer layer 31 are made of the same material, the first gap 52 and the second gap 53 can be formed simultaneously during the etching process.

[0072] Preferably, the faster etching rate of the first spacer layer 21 and the second spacer layer 31 compared to the first channel material layer 22 (sheet-like conductive channel 221) and the second channel material layer 32 (fin-like conductive channel 321) can be utilized to form a first gap 52 in the first spacer layer 21 and a second gap 53 in the second spacer layer 31 while etching to expose (open) the source / drain regions. To achieve the above effect, in one specific embodiment, the first spacer layer 21 and the second spacer layer 31 are both made of germanium-silicon, while the first channel material layer 22 and the first channel material layer 22 are both made of silicon; in another specific embodiment, the first channel material layer 22 may be made of first germanium-silicon, the second channel material layer 32 may be made of silicon (or silicon carbide), and the first spacer layer 21 and the second spacer layer 31 may both be made of second germanium-silicon, with the germanium content of the second germanium-silicon being greater than that of the first germanium-silicon. The higher the germanium content during etching, the faster the etching rate, thus achieving the above effect.

[0073] Next, please refer to Figure 11 In step S05, an isolation structure 54 is formed in the first gap 52 and the second gap 53. The isolation structure 54 is used to isolate the gate structure and source / drain structure of the semiconductor structure.

[0074] Since the width W of the fin-shaped spacer layer 311 is the same as or nearly the same as the thickness T of the first spacer layer 21, the thickness of the first gap 52 is the same as or nearly the same as the width of the second gap 53. Therefore, isolation material layers can be filled into the first gap 52 and the second gap 53 in a conformal (conformal) manner to simultaneously form isolation structures 54. Furthermore, even if the gap between the p-type and n-type field-effect transistors (the height of the second gap 53) is much larger than the height (thickness) of the first gap 52, the isolation structure 54 can still be formed simultaneously using the method of this embodiment. This eliminates the limitation on the formation process of the isolation structure 54, thus reducing the difficulty of forming the semiconductor isolation structure 54. It should be understood that if the gap (spacing) between the p-type field-effect transistor and the n-type field-effect transistor does not form the second gap 53 in this embodiment but forms a gap with the same width as the sheet-like conductive channel 221, then it is impossible to simultaneously form the isolation structure 54 within the first gap 52 and the gap between the p-type field-effect transistor and the n-type field-effect transistor. In other embodiments with a large depth-to-width ratio and a small source-drain structure (source-drain region), the height of the gap between the p-type field-effect transistor and the n-type field-effect transistor is even greater than the size (length or width) of the source-drain region. In other words, even if the source-drain region is filled with the isolation material layer, it is not possible to fill the gap between the p-type field-effect transistor and the n-type field-effect transistor to form the isolation structure 54.

[0075] The isolation material layer is a material with better isolation effect and higher etching selectivity than the materials in the first stacked structure 20 and the second stacked structure 30, such as silicon nitride or silicon carbide nitride. Taking silicon nitride as an example, the etching selectivity ratio of the isolation material layer relative to the first stacked structure 20 and the second stacked structure 30 (silicon or germanium silicon) can be 5:1 to 15:1. The isolation material layer can be formed by ALD (atomic layer deposition) process to improve its step coverage.

[0076] Next, an anisotropic etching process can be used to remove part of the isolation material layer on the sidewall of the source / drain region to expose the end faces of the sheet-like conductive channel 221 and the fin-like conductive channel 321, so that the source / drain structure can be formed by epitaxially using the exposed end faces; the first spacer layer and the second spacer layer are removed, and the gate structure is formed in the space remaining after the first spacer layer and the second spacer layer are removed.

[0077] Of course, the semiconductor structure formation method exemplified in this embodiment may also include other subsequent processes, but the above steps can be formed using methods commonly used in the art, which will not be described in detail here.

[0078] Example 2

[0079] Example 2 provides a method for forming a semiconductor structure. The method for forming the semiconductor structure provided in this example is similar to that in Example 1, with the only difference being that the semiconductor structure in this example can have any suitable number of sheet-like conductive channels and any suitable number of fin-like conductive channels. Taking a semiconductor structure with three sheet-like conductive channels and four fin-like conductive channels as an example, when forming the first stacked structure, the first stacked structure can have three layers of first channel material to form three sheet-like conductive channels; in the second stacked structure, there is one layer of second channel material, but in the patterned second core layer, two spaced-apart second cores can be formed to form four spaced-apart first sidewall structures, thereby forming four fin-like conductive channels.

[0080] Example 3

[0081] Example 3 provides a method for fabricating a semiconductor device, the semiconductor device including a semiconductor structure, the semiconductor structure in the semiconductor device being formed using the semiconductor structure formation method described above, that is, the method for fabricating the semiconductor device includes the semiconductor structure formation method described above.

[0082] In summary, the semiconductor structure formation method and semiconductor device fabrication method provided by the present invention, by forming a fin-shaped spacer layer between the fin-shaped conductive channel and the sheet-shaped conductive channel, and the ratio of the width of the fin-shaped spacer layer to the thickness of the first spacer layer in the first stacked structure is 0.8:1 to 1:0.5, can make the height of the gap formed in the first spacer layer the same or nearly the same as the width of the gap formed in the fin-shaped spacer layer. Thus, an isolation structure can be formed simultaneously in the gap between the first spacer layer and the second spacer layer, thereby reducing the process difficulty of forming the isolation structure of the semiconductor structure.

[0083] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A silicon substrate is provided, wherein a first stacked structure and a second stacked structure are disposed on the first stacked structure, the first stacked structure includes a first spacer layer and a first channel material layer stacked alternately in sequence, and the second stacked structure includes a second spacer layer and a second channel material layer stacked alternately in sequence. The second layered structure is used to form a fin-shaped conductive channel and a fin-shaped spacer layer, and the first layered structure is used to form a sheet-shaped conductive channel. The ratio of the width of the fin-shaped spacer layer to the thickness of the first spacer layer is 0.8:1 to 1:0.

5. A virtual gate is formed to cover the silicon substrate and fill the space above the fin-shaped conductive channel. The virtual gate covers the gate region and source / drain region of the semiconductor structure. Remove the dummy gate, finned conductive channel, and sheet-like conductive channel from the source / drain regions, and form a plurality of gaps recessed in the finned spacer layer and the first spacer layer near the source / drain regions; and An isolation structure is formed within a plurality of the aforementioned gaps, the isolation structure being used to isolate the gate structure and source / drain structure of the semiconductor structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first spacer layer, the first channel material layer, the second spacer layer, and the second channel material layer are all silicon-containing superlattice layers, and the first channel material layer and the second channel material layer have opposite conductivity types.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The first spacer layer and the second spacer layer are made of the same material. The first channel material layer has a P-type conductivity, and the second channel material layer has an N-type conductivity.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps of forming the sheet-like conductive channel include: The second layered structure sequentially forms a first material layer, a first mandrel layer, a second material layer, and a second mandrel layer; The second mandrel layer is graphically represented to form at least one second mandrel; At least one first sidewall structure is formed on the sidewall of the second mandrel, the width of the first sidewall structure being the same as the width of the fin-shaped conductive channel; The second material layer, the second mandrel, and the first mandrel layer are etched sequentially to remove the second mandrel and form the first mandrel in the first mandrel layer; Etch the first material layer and the second material layer, and remove the first sidewall structure to form at least one fin-like structure with the remaining second material layer; and, The first stacked structure and the second stacked structure are etched using the first mandrel as a mask, and the remaining first channel material layer is used as the sheet-like conductive channel.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The step of forming the fin-shaped conductive channel includes: Using the fin-like structure as a mask, the first core, the first material layer, and the second stacked structure are etched sequentially, with the remaining first channel material layer serving as the fin-like conductive channel and the remaining second spacer layer serving as the fin-like spacer layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the first sidewall structure includes titanium oxide, and both the first material layer and the second material layer include a silicon nitride layer and a silicon oxide layer formed sequentially.

7. The method for forming a semiconductor structure according to any one of claims 1 to 6, characterized in that, The plurality of gaps includes a first gap formed in the first spacer layer and a second gap formed in the fin-shaped spacer layer, wherein the ratio of the thickness of the first gap to the width of the second gap is 0.8:1 to 1:0.

5.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, Both the first spacer layer and the second spacer layer are made of germanium-silicon, and both the first channel material layer and the second channel material layer are made of silicon, so that the first gap and the second gap are formed simultaneously when the virtual gate, fin conductive channel and sheet conductive channel of the source and drain regions are removed.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The isolation structure is made of silicon nitride and is formed in the first gap and the second gap using an ALD process.

10. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes the method for forming a semiconductor structure as described in any one of claims 1 to 9.

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