Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a surface of the semiconductor substrate comprising a pad oxide layer and an isolation trench penetrating through the pad oxide layer and extending into the semiconductor substrate; an isolation structure located in the isolation trench and higher than the surface of the pad oxide layer, the isolation structure comprising an oxide layer located at the bottom and sidewall of the isolation trench, a barrier layer located at the surface of the oxide layer, and a filling layer located at the surface of the barrier layer and filling the isolation trench, wherein the filling layer completely covers the barrier layer. The application provides a semiconductor structure and a forming method thereof, the barrier layer is divided into two unconnected parts, and the removal of the second part does not affect the first part, so that the isolation effect of the shallow trench isolation structure is improved, and the reliability of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Shallow trench isolation (STI) is the mainstream technology for isolation devices in large-scale integrated circuits. It overcomes the shortcomings of traditional local oxidation on silicon (LOCOS) technology, such as severe bird-beak effect, narrow width effect, and surface roughness. The STI structure is filled with high-density plasma silicon oxide deposition (HDPOX), which damages the inner sidewalls of the STI. Therefore, STIs are typically covered by sidewall oxide layers. Furthermore, to further reduce leakage, sidewall silicon nitride is formed on the surface of the sidewall oxide layer.

[0003] However, the presence of sidewall silicon nitride also triggers some weaknesses at the active region corner (AA corner), which will affect gate silicon oxide integrity (GOI) and time-dependent dielectric breakdown (TDDB).

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the isolation effect of shallow trench isolation structures and improve device reliability.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the surface of which includes a pad oxide layer, a hard mask layer, and an isolation trench extending through the hard mask layer and the pad oxide layer into the semiconductor substrate; forming an oxide layer at the bottom and sidewalls of the isolation trench in the semiconductor substrate; forming a barrier layer at the bottom and sidewalls of the isolation trench and on the surface of the hard mask layer; forming a filling layer in the isolation trench to fill the isolation trench, wherein a portion of the barrier layer at the junction of the pad oxide layer and the barrier layer is removed to form a gap, the filling layer fills the gap and extends to the surface of the oxide layer to divide the barrier layer into a first portion and a second portion, the first portion being lower than the surface of the semiconductor substrate and the second portion being higher than the surface of the semiconductor substrate; removing the second portion of the barrier layer and the hard mask layer, wherein the oxide layer, the first portion of the barrier layer, and the filling layer constitute an isolation structure.

[0007] In some embodiments of this application, the method for forming the filling layer is a high-density plasma chemical vapor deposition process, in which plasma sputtering bombards the barrier layer to form the gap.

[0008] In some embodiments of this application, the process parameters of the high-density ion beam deposition process include: the ratio of deposition rate to sputtering rate is set such that a portion of the barrier layer at the junction of the pad oxide layer and the barrier layer is removed to form a gap, and the filling layer fills the gap and extends to the surface of the oxide layer to divide the barrier layer into a first part and a second part.

[0009] In some embodiments of this application, the method for forming an oxide layer at the bottom and sidewalls of the isolation trench located in the semiconductor substrate is a thermal oxidation process.

[0010] In some embodiments of this application, the thickness of the barrier layer is 1400 angstroms to 2000 angstroms.

[0011] In some embodiments of this application, the method for forming the semiconductor structure further includes forming a gate layer on the surface of the pad oxide layer on both sides of the isolation trench.

[0012] In some embodiments of this application, the method of forming a gate layer on the surface of the pad oxide layer on both sides of the isolation trench includes: forming a gate material layer on the surface of the pad oxide layer and the surface of the fill layer; etching away the gate material layer on the surface of the fill layer and part of the surface of the pad oxide layer to form the gate layer.

[0013] Another aspect of this application provides a semiconductor structure comprising: a semiconductor substrate, the surface of which includes a pad oxide layer and an isolation trench extending through the pad oxide layer into the semiconductor substrate; and an isolation structure located in the isolation trench and above the surface of the pad oxide layer, the isolation structure including an oxide layer located at the bottom and sidewalls of the isolation trench, a barrier layer located on the surface of the oxide layer, and a filling layer located on the surface of the barrier layer and filling the isolation trench, wherein the filling layer completely covers the barrier layer.

[0014] In some embodiments of this application, the thickness of the barrier layer is 1400 angstroms to 2000 angstroms.

[0015] In some embodiments of this application, the semiconductor structure further includes a gate layer located on the surface of the pad oxide layer on both sides of the isolation trench.

[0016] This application provides a semiconductor structure and a method for forming the same, which divides the barrier layer into two unconnected parts. Removing the second part will not affect the first part, thereby improving the isolation effect of the shallow trench isolation structure and enhancing device reliability. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 4 These are schematic diagrams illustrating the steps involved in forming some semiconductor structures.

[0020] Figures 5 to 11 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] Figures 1 to 4 This is a schematic diagram of the steps in some methods for forming semiconductor structures.

[0024] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, on the surface of which a pad oxide layer 110 and a hard mask layer 120 are formed. An isolation structure is also formed in the semiconductor substrate 100, the isolation structure including a filling layer 150, a barrier layer 140 located on the sidewalls and bottom of the filling layer 150, and an oxide layer 130 located at the bottom of the barrier layer 140.

[0025] refer to Figure 2 As shown, etching removes the barrier layer 140 and hard mask layer 120 above the pad oxide layer 110. However, in actual processes, due to the difficulty in controlling the precision of the etching process, when etching away the barrier layer 140 and hard mask layer 120 above the pad oxide layer 110, the portion of the barrier layer 140 below the pad oxide layer 110 may also react with the etchant and be etched away, leaving a depression 160 (e.g., a small narrow hole or crack). This depression 160 may become larger in subsequent cleaning processes.

[0026] refer to Figure 3 As shown, a gate material layer 170a is formed on the surface of the pad oxide layer 110 and the fill layer 150, and the gate material layer 170a fills the recess 160.

[0027] refer to Figure 4 As shown, the gate material layer 170a is etched to form the gate layer 170 on the surface of the pad oxide layer 110. However, since the gate material layer 170a in the reverse-angled recess 160 is difficult to etch, a gate material layer 170a remains in the recess 160. The material of the gate material layer 170a is generally polysilicon, and this polysilicon residue may pose a high risk of electrical bridging between different devices and cause chip malfunction.

[0028] To address the aforementioned issues, this application provides a semiconductor structure and its formation method, which divides the barrier layer into two unconnected parts. Removing the second part does not affect the first part, prevents the formation of depressions, and eliminates polysilicon residue. This improves the isolation effect of the shallow trench isolation structure and enhances device reliability.

[0029] Figures 5 to 11 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 5 As shown, a semiconductor substrate 200 is provided, the surface of which includes a pad oxide layer 210, a hard mask layer 220, and an isolation trench 230 that penetrates the hard mask layer 220 and the pad oxide layer 210 and extends into the semiconductor substrate 200.

[0031] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0032] In some embodiments of this application, the material of the pad oxide layer 210 is, for example, silicon oxide. The method for forming the pad oxide layer 210 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). The pad oxide layer 210 serves as a buffer layer for growing the hard mask layer 220.

[0033] In some embodiments of this application, the material of the hard mask layer 220 is, for example, silicon nitride. The method for forming the hard mask layer 220 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). The hard mask layer 220 serves as an etching mask during the etching process to form the isolation trench 230.

[0034] In some embodiments of this application, the isolation trench 230 is formed by an etching process, and the isolation trench 230 is used to form an isolation structure.

[0035] refer to Figure 6 An oxide layer 240 is formed at the bottom and sidewalls of the isolation trench 230 located in the semiconductor substrate 200, as shown.

[0036] In some embodiments of this application, the method for forming an oxide layer 240 at the bottom and sidewalls of the isolation trench 230 located in the semiconductor substrate 200 is a thermal oxidation process. The material of the oxide layer 240 is, for example, silicon oxide. The function of the oxide layer 240 is to prevent damage to the semiconductor substrate on the sidewalls of the isolation trench 230 when a fill layer is subsequently formed using a high-density plasma chemical vapor deposition (HDPCVD) process.

[0037] refer to Figure 7 As shown, a barrier layer 250 is formed at the bottom and sidewalls of the isolation trench 230 and on the surface of the hard mask layer 220. The barrier layer 250 serves to further reduce leakage of the filler layer 260.

[0038] In some embodiments of this application, the material of the barrier layer 250 is, for example, silicon nitride. Methods for forming the barrier layer 250 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0039] In some embodiments of this application, the thickness of the barrier layer 250 is 1400 angstroms to 2000 angstroms, for example, 1600 angstroms or 1800 angstroms. The thickness of the barrier layer 250 differs from that of conventional processes. The thickness of the barrier layer 250 needs to be adjusted in conjunction with the process parameters of the HDPCVD process so that the HDPCVD process precisely positions the boundary (i.e., the junction of the pad oxide layer 210, the barrier layer 250, and the oxide layer 240) at this boundary. Figure 7 The area within the dashed box is breached, creating a gap, while the barrier layer 250 in other areas remains unbroken.

[0040] It should be noted that, for the sake of simplicity, the attached diagrams do not show the actual dimensions and shapes, but rather use simple bar graphs to illustrate the various film layers. In reality, due to shape factors, the positions at the junctions of the pad oxide layer 210, the barrier layer 250, and the oxide layer 240 (i.e., the locations shown in the attached diagrams) are not shown in proportion to the actual dimensions or shapes. Figure 7 (The position of the dashed box in the middle) The thickness of the blocking layer 250 is thinner than that of other positions because this position is a corner with a concave and convex shape. The blocking layer 250 is a smooth arc shape at this position, so the thickness will be thinner.

[0041] refer to Figure 8 As shown, a filling layer 260 is formed in the isolation trench 230 to fill the isolation trench 230. At the junction of the pad oxide layer 210, the barrier layer 250, and the oxide layer 240, part of the barrier layer 250 is removed to form a gap. The filling layer 260 fills the gap and extends to the surface of the oxide layer 240, dividing the barrier layer 250 into a first part and a second part. The first part is lower than the surface of the semiconductor substrate 200, and the second part is higher than the surface of the semiconductor substrate 200.

[0042] In some embodiments of this application, the method for forming the filling layer 260 is a high-density plasma chemical vapor deposition (HDPCVD) process, in which plasma sputtering bombards the barrier layer 250 to form the gap.

[0043] In some embodiments of this application, the process parameters of the high-density ion beam deposition process include: the ratio of deposition rate to sputtering rate is set such that a portion of the barrier layer at the junction of the pad oxide layer and the barrier layer is removed to form a gap, and the filling layer fills the gap and extends to the surface of the oxide layer to divide the barrier layer into a first part and a second part.

[0044] HDP exhibits excellent filling capability because deposition and sputtering occur simultaneously. The deposition equation is as follows:

[0045] SiH4 + N2O → SiO2 + byproduct

[0046] And sputtering uses Ar + or Xe + The bombardment process, accelerated under an electric field, results in high-energy ions. Due to their large size and weight, the physical impact effect is good, effectively breaking apart SiN at corners. Then, SiO2 is deposited to cover the broken SiN.

[0047] High-density plasma chemical vapor deposition (HDP-CVD) is controlled by the DS ratio, which is the deposition rate / sputter rate. By increasing the sputtering power before deposition, the corners ( Figure 7 The barrier layer at the corner (within the dashed box) is more fragile and easily damaged than the barrier layer at the non-corner locations, and is removed during plasma bombardment. Furthermore, the barrier layer at the corner is inherently thinner. Therefore, by controlling the process parameters of HDPCVD (deposition time, sputtering time, and sputtering power), it is possible to create a gap in the barrier layer at the corner and fill the gap with a filler layer.

[0048] In conventional processes, the barrier layer is a single unit, which leads to depressions during subsequent etching of the barrier layer and hard mask layer. However, in the present application, by controlling the HDPCVD process parameters, the fill layer 260 divides the barrier layer 250 into two parts, protecting the first part of the barrier layer below the surface of the semiconductor substrate 200. This prevents depressions from forming during subsequent etching of the second part of the barrier layer above the surface of the semiconductor substrate 200 and the hard mask layer 220.

[0049] refer to Figure 9 As shown, after removing the second portion of the barrier layer 250 and the hard mask layer 220, the oxide layer 240, the first portion of the barrier layer 250, and the filler layer 260 constitute an isolation structure 270. The isolation structure 270 is used to isolate adjacent active devices.

[0050] In some embodiments of this application, the method for removing the second portion of the barrier layer 250 and the hard mask layer 220 is a wet etching process. Since the material of the barrier layer 250 and the hard mask layer 220 is the same, they can be removed simultaneously.

[0051] Because the filler layer 260 divides the barrier layer 250 into two parts and protects the first part of the barrier layer below the surface of the semiconductor substrate 200, the etching process stops at the surface of the pad oxide layer 210 and the sidewalls of the filler layer 260 when the second part of the barrier layer 250 and the hard mask layer 220 are removed, and no more depressions are formed in the isolation structure.

[0052] refer to Figure 10 and Figure 11 As shown, a gate layer 280 is formed on the surface of the pad oxide layer 210 on both sides of the isolation trench.

[0053] Specifically, refer to Figure 10 As shown, a gate material layer 280a is formed on the surface of the pad oxide layer 210 and the surface of the fill layer 260; Reference Figure 11 As shown, the gate material layer 280a is formed by etching away the surface of the filling layer 260 and part of the surface of the pad oxide layer 210.

[0054] In some embodiments of this application, the gate material layer 280a is made of, for example, polysilicon. Methods for forming the gate material layer 280a include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0055] In the technical solution of this application, there is no polysilicon residue within the isolation structure 270. This improves the isolation effect of the isolation structure 270, reduces the risk of electrical bridging between adjacent devices, and enhances device reliability.

[0056] This application provides a method for forming a semiconductor structure, which divides the barrier layer into two unconnected parts. Removing the second part will not affect the first part, thereby improving the isolation effect of the shallow trench isolation structure and improving the reliability of the device.

[0057] Embodiments of this application also provide a semiconductor structure, referencing Figure 11As shown, it includes: a semiconductor substrate 200, the surface of which includes a pad oxide layer 210 and an isolation trench extending through the pad oxide layer 210 and into the semiconductor substrate 200; and an isolation structure 270 located in the isolation trench and above the surface of the pad oxide layer 210, the isolation structure 270 including an oxide layer 240 located at the bottom and sidewalls of the isolation trench, a barrier layer 250 located on the surface of the oxide layer 240, and a filling layer 260 located on the surface of the barrier layer 250 and filling the isolation trench, wherein the filling layer 260 completely covers the barrier layer 250.

[0058] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0059] In some embodiments of this application, the material of the pad oxide layer 210 is, for example, silicon oxide.

[0060] In some embodiments of this application, the isolation trench is used to form an isolation structure 270.

[0061] Continue to refer to Figure 11 As shown, in some embodiments of this application, the material of the oxide layer 240 is, for example, silicon oxide. The function of the oxide layer 240 is to prevent damage to the semiconductor substrate on the sidewalls of the isolation trench when the fill layer 260 is subsequently formed using a high-density plasma chemical vapor deposition (HDPCVD) process.

[0062] Continue to refer to Figure 11 As shown, in some embodiments of this application, the material of the barrier layer 250 is, for example, silicon nitride. The function of the barrier layer 250 is to further reduce leakage of the filler layer 260.

[0063] In some embodiments of this application, the thickness of the barrier layer 250 is 1400 angstroms to 2000 angstroms, for example, 1600 angstroms or 1800 angstroms.

[0064] Continue to refer to Figure 11As shown, in some embodiments of this application, the material of the filling layer 260 is silicon oxide formed by HDPCVD process.

[0065] Continue to refer to Figure 11 As shown, the semiconductor structure further includes a gate layer 280 located on the surface of the pad oxide layer 210 on both sides of the isolation trench.

[0066] In some embodiments of this application, the material of the gate layer 280 is, for example, polysilicon.

[0067] In conventional semiconductor structures, polysilicon residue often remains at the junctions of the barrier layer, pad oxide layer, and oxide layer, affecting device reliability. However, in the present application's solution, since the fill layer 260 completely covers the surface of the barrier layer 250, there is no polysilicon residue within the isolation structure 270. This improves the isolation effect of the isolation structure 270, reduces the risk of electrical bridging between adjacent devices, and enhances device reliability.

[0068] This application provides a semiconductor structure and a method for forming the same, which divides the barrier layer into two unconnected parts. Removing the second part will not affect the first part, thereby improving the isolation effect of the shallow trench isolation structure and enhancing device reliability.

[0069] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0070] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0071] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0072] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0073] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the surface of which includes a pad oxide layer, a hard mask layer, and an isolation trench that penetrates the hard mask layer and the pad oxide layer and extends into the semiconductor substrate; An oxide layer is formed at the bottom and sidewalls of the isolation trench located in the semiconductor substrate; A barrier layer is formed at the bottom and sidewalls of the isolation trench and on the surface of the hard mask layer; A filling layer is formed in the isolation trench to fill the isolation trench. The filling layer is formed by a high-density plasma chemical vapor deposition process. In the high-density plasma chemical vapor deposition process, plasma sputtering bombards the barrier layer. Part of the barrier layer at the junction of the pad oxide layer and the barrier layer is removed to form a gap. The filling layer fills the gap and extends to the surface of the oxide layer, dividing the barrier layer into a first part and a second part. The first part is lower than the surface of the semiconductor substrate, and the second part is higher than the surface of the semiconductor substrate. The second portion of the barrier layer and the hard mask layer are removed, and the oxide layer, the first portion of the barrier layer, and the filler layer constitute an isolation structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters of the high-density ion beam deposition process include: the ratio of deposition rate to sputtering rate is set such that a portion of the barrier layer at the junction of the pad oxide layer and the barrier layer is removed to form a gap, and the filling layer fills the gap and extends to the surface of the oxide layer to divide the barrier layer into a first part and a second part.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming an oxide layer at the bottom and sidewalls of the isolation trench located in the semiconductor substrate is a thermal oxidation process.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer is 1400 angstroms to 2000 angstroms.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A gate layer is formed on the surface of the pad oxide layer on both sides of the isolation trench.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, A method for forming a gate layer on the surface of the pad oxide layer on both sides of the isolation trench includes: A gate material layer is formed on the surface of the pad oxide layer and the surface of the fill layer; The gate layer is formed by etching away the gate material layer on the surface of the fill layer and part of the pad oxide layer.

7. A semiconductor structure, characterized in that, Formed using any one of claims 1 to 6, comprising: A semiconductor substrate, the surface of which includes a pad oxide layer and an isolation trench that penetrates the pad oxide layer and extends into the semiconductor substrate; An isolation structure is located in the isolation trench and above the surface of the pad oxide layer. The isolation structure includes an oxide layer located at the bottom and sidewalls of the isolation trench, a barrier layer located on the surface of the oxide layer, and a filling layer located on the surface of the barrier layer that fills the isolation trench, wherein the filling layer completely covers the barrier layer.

8. The semiconductor structure as described in claim 7, characterized in that, The thickness of the barrier layer is 1400 angstroms to 2000 angstroms.

9. The semiconductor structure as described in claim 7, characterized in that, Also includes: Gate layer located on the surface of the pad oxide layer on both sides of the isolation trench.

Images