Highly reliable sapphire substrate gan power device and method of manufacturing the same

Abstract

The application discloses a high-reliability sapphire substrate GaN power device and a preparation method thereof, relates to the technical field of semiconductor devices, and comprises a sapphire substrate, a GaN high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer, a gate mesa structure, a first passivation layer, an electrode layer and a second passivation layer, wherein the electrode layer comprises a source electrode, a gate electrode and a drain electrode; a heat dissipation opening is arranged through the sapphire substrate, and the projection of the gate electrode is located in the heat dissipation opening; an AlN layer and a back field plate metal layer are arranged in the heat dissipation opening, the AlN layer is connected with the GaN high-resistance buffer layer, and the back field plate metal layer extends out of the heat dissipation opening and covers the lower surface of the sapphire substrate. The AlN layer and the back field plate metal layer are filled in the heat dissipation opening arranged in the sapphire substrate, and the back field plate metal layer further covers the lower surface of the sapphire substrate, so that the heat dissipation capacity of the power device is effectively improved, and the reliability of the power device is greatly enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a high-reliability sapphire substrate GaN power device and its fabrication method. Background Technology

[0002] Compared to GaN power devices on Si substrates, GaN power devices on sapphire substrates offer advantages such as higher crystal quality from sapphire epitaxy, lower device fabrication costs, and suitability for high-voltage power environments. However, the thermal conductivity of sapphire substrates is significantly lower than that of Si substrates, resulting in a much lower heat dissipation capacity for GaN power devices on sapphire substrates. This makes GaN power devices on sapphire substrates prone to thermal breakdown, performance degradation, and device failure due to heat accumulation during use, severely impacting their reliability. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a highly reliable GaN power device on a sapphire substrate and its fabrication method. By setting heat dissipation ports in the sapphire substrate and filling them with an AlN layer and a back field metal layer, and the back field metal layer also covering the lower surface of the sapphire substrate, the heat dissipation capacity of the GaN power device on the sapphire substrate can be effectively improved, thereby greatly enhancing the reliability of the GaN power device on the sapphire substrate.

[0004] The present invention provides a highly reliable GaN power device on a sapphire substrate. The GaN power device on a sapphire substrate includes a sapphire substrate and GaN high-resistivity buffer layer, GaN channel layer, AlGaN barrier layer, gate mesa structure, first passivation layer, electrode layer and second passivation layer sequentially stacked on the sapphire substrate. The electrode layer includes a source electrode, a gate electrode and a drain electrode arranged sequentially at intervals.

[0005] A heat dissipation port is provided in the sapphire substrate, extending from the lower surface of the sapphire substrate to the lower surface of the GaN high-resistivity buffer layer; the projection of the gate electrode on the sapphire substrate is located in the heat dissipation port; an AlN layer and a back surface plate metal layer are sequentially disposed in the heat dissipation port from top to bottom, the AlN layer and the GaN high-resistivity buffer layer are in contact, and the back surface plate metal layer extends out of the heat dissipation port and covers the lower surface of the sapphire substrate.

[0006] Specifically, mesa isolation structures are formed on both sides of the GaN high-resistivity buffer layer, the GaN channel layer, and the AlGaN barrier layer. The mesa isolation structures extend from the upper surface of the AlGaN barrier layer into the GaN high-resistivity buffer layer. The gate mesa structure is close to one of the mesa isolation structures. The first passivation layer covers the surfaces of the mesa isolation structure, the AlGaN barrier layer, and the gate mesa structure.

[0007] The source electrode and the drain electrode are located on opposite sides of the gate mesa structure, and the source electrode and the drain electrode extend through the first passivation layer to the upper surface of the AlGaN barrier layer; the gate electrode is disposed on the gate mesa structure, and the bottom of the gate electrode is in contact with the upper surface of the first passivation layer; the source electrode is close to the gate electrode, and the drain electrode is away from the gate electrode;

[0008] The second passivation layer fills the uneven surfaces of the first passivation layer, the source electrode, and the drain electrode.

[0009] Specifically, the sapphire substrate GaN power device further includes a third passivation layer, a field plate metal layer, a fourth passivation layer, and an electrode connection layer sequentially stacked on the second passivation layer. The projection of the field plate metal layer on the second passivation layer covers the electrode layer. The field plate metal layer includes a source field plate and a drain field plate, which are spaced apart. The source field plate extends vertically to the upper surface of the source electrode, and the drain field plate extends vertically to the upper surface of the drain electrode.

[0010] The electrode connection layer includes a source connection block, a gate connection block, and a drain connection block. The source connection block, the gate connection block, and the drain connection block are spaced apart. The source connection block extends vertically to the upper surface of the source field plate, the gate connection block extends vertically to the upper surface of the gate electrode, and the drain connection block extends vertically to the upper surface of the drain field plate.

[0011] Specifically, the lower surface of the back surface metal layer is connected to a pad layer based on conductive die bond adhesive or solder paste.

[0012] This invention also provides a method for fabricating a high-reliability GaN power device on a sapphire substrate. The method comprises the following steps:

[0013] S1. Sequentially form a GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer, a gate mesa structure, a first passivation layer, a source electrode and a drain electrode, a second passivation layer, and a gate electrode on a sapphire substrate.

[0014] S2. A heat dissipation port is etched in a predetermined area of ​​the sapphire substrate, and the heat dissipation port exposes the GaN high-resistivity buffer layer; the projection of the gate electrode on the sapphire substrate is located in the heat dissipation port;

[0015] S3. An AlN layer is deposited in the heat dissipation port, wherein the thickness of the AlN layer is less than the depth of the heat dissipation port;

[0016] S4. A back field metal layer is deposited on the side of the sapphire substrate away from the GaN high-resistivity buffer layer, and the back field metal layer covers the AlN layer and the sapphire substrate.

[0017] Specifically, step S1 includes:

[0018] S110. A GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer are sequentially grown on a sapphire substrate to obtain an epitaxial wafer.

[0019] S111. An isolation pit is formed by etching in a predetermined area of ​​the epitaxial wafer. The isolation pit extends from the upper surface of the P-type GaN layer to the GaN high-resistivity buffer layer.

[0020] S112. The P-type GaN layer in the preset area is removed by mask etching to expose the AlGaN barrier layer, and the remaining P-type GaN layer forms a gate mesa structure on the AlGaN barrier layer.

[0021] The isolation pit forms a mesa isolation structure, which extends from the upper surface of the AlGaN barrier layer to the GaN high-resistivity buffer layer.

[0022] S113. A first passivation layer is deposited along the surface of the mesa isolation structure, the AlGaN barrier layer and the gate mesa structure.

[0023] S114. A source opening and a drain opening are etched in a preset area of ​​the first passivation layer; the source opening and the drain opening are respectively located on both sides of the gate mesa structure, the source opening is close to the gate mesa structure, and the drain opening is far away from the gate mesa structure; the source opening and the drain opening expose the AlGaN barrier layer.

[0024] S115. A source electrode is deposited in the source opening to form a source electrode, and a drain electrode is deposited in the drain opening to form a drain electrode;

[0025] S116. A second passivation layer is deposited on the surface of the first passivation layer, the source electrode, and the drain electrode, and the second passivation layer fills the uneven surfaces of the first passivation layer, the source electrode, and the drain electrode.

[0026] S117. A gate opening is formed by etching in a preset area of ​​the second passivation layer. The gate opening is located above the gate mesa structure and exposes the first passivation layer.

[0027] S118, A gate electrode is deposited in the gate opening to form a gate electrode.

[0028] Specifically, after step S118, the following is also included:

[0029] S119. A third passivation layer is deposited on the surface of the second passivation layer and the gate electrode;

[0030] S120. Source holes and drain holes are etched in a preset area of ​​the third passivation layer, the source holes exposing the source electrode and the drain holes exposing the drain electrode.

[0031] S121. A source electrode post is deposited in the source electrode cavity to form a source electrode post, and a drain electrode post is deposited in the drain electrode cavity to form a drain electrode post;

[0032] S122, A source field plate and a drain field plate are deposited in a predetermined region of the third passivation layer; the source field plate is connected to the source terminal, and the drain field plate is connected to the drain terminal; the projection of the source field plate on the second passivation layer covers the source electrode and the gate electrode, and the projection of the drain field plate on the second passivation layer covers the drain electrode.

[0033] S123. A fourth passivation layer is deposited on the surface of the third passivation layer, the source field plate, and the drain field plate;

[0034] S124. Source connection holes, gate connection holes, and drain connection holes are etched in a preset area of ​​the fourth passivation layer; the source connection holes expose the source field plate, the gate connection holes expose the gate electrode, and the drain connection holes expose the drain field plate.

[0035] S125. A source connection post is deposited in the source connection hole to form a source connection post, a gate connection post is deposited in the gate connection hole to form a gate connection post, and a drain connection post is deposited in the drain connection hole to form a drain connection post.

[0036] S126. A source connection block, a gate connection block, and a drain connection block are deposited in a preset region of the fourth passivation layer; the source connection block is connected to the source connection post, the gate connection block is connected to the gate connection post, and the drain connection block is connected to the drain connection post.

[0037] Specifically, the procedure before step S111 also includes:

[0038] The surface of the epitaxial wafer is cleaned with acetone solution and SPM solution respectively to obtain a first clean epitaxial wafer. The first clean epitaxial wafer is rinsed with flowing deionized water to obtain a second clean epitaxial wafer. The second clean epitaxial wafer is dried with nitrogen gas.

[0039] The SPM solution is a mixture of sulfuric acid and hydrogen peroxide.

[0040] Specifically, step S115 also includes:

[0041] The source electrode and the drain electrode are annealed in a nitrogen atmosphere; the annealing temperature is 500-1000℃.

[0042] Specifically, the process before step S2 also includes:

[0043] The sapphire substrate is thinned to 100-300 μm, and the bottom surface of the thinned sapphire substrate is polished.

[0044] Compared with the prior art, the beneficial effects of the present invention are:

[0045] This invention incorporates a heat dissipation port within a sapphire substrate, penetrating the substrate. The port is filled with an AlN layer and a back surface metal layer. The AlN layer directly contacts the GaN high-resistivity buffer layer. The AlN layer, possessing high thermal conductivity, guides heat from within the GaN power device on the sapphire substrate to the back surface metal layer, which then diffuses the heat. The back surface metal layer covers the lower surface of the sapphire substrate, providing a large heat dissipation area and accelerating heat dissipation. The AlN layer and the back surface metal layer effectively enhance the heat dissipation capacity of the GaN power device on the sapphire substrate, preventing heat accumulation during use and reducing the risk of performance degradation and device failure. This significantly improves the reliability of the GaN power device on the sapphire substrate. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the overall structure of the GaN power device on a sapphire substrate in an embodiment of the present invention;

[0048] Figure 2This is a flowchart of the fabrication method of GaN power device on sapphire substrate in an embodiment of the present invention;

[0049] Figure 3 This is a flowchart of step S1 in an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the epitaxial wafer structure in an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of the isolation pit in an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the gate mesa structure in an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of the structure of the first passivation layer in an embodiment of the present invention;

[0054] Figure 8 This is a schematic diagram of the source and drain openings in an embodiment of the present invention;

[0055] Figure 9 This is a schematic diagram of the source electrode and drain electrode in an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of the structure of the second passivation layer in an embodiment of the present invention;

[0057] Figure 11 This is a schematic diagram of the gate opening structure in an embodiment of the present invention;

[0058] Figure 12 This is a schematic diagram of the planar structure of the gate electrode in an embodiment of the present invention;

[0059] Figure 13 This is a three-dimensional structural diagram of the gate electrode in an embodiment of the present invention;

[0060] Figure 14 This is a schematic diagram of the structure of the third passivation layer in an embodiment of the present invention;

[0061] Figure 15 This is a schematic diagram of the source and drain holes in an embodiment of the present invention;

[0062] Figure 16 This is a schematic diagram of the source and drain terminals in an embodiment of the present invention;

[0063] Figure 17 This is a schematic diagram of the source field plate and drain field plate in an embodiment of the present invention;

[0064] Figure 18 This is a schematic diagram of the structure of the fourth passivation layer in an embodiment of the present invention;

[0065] Figure 19 This is a schematic diagram of the source connection hole, gate connection hole, and drain connection hole in an embodiment of the present invention;

[0066] Figure 20 This is a schematic diagram of the source connection post, gate connection post, and drain connection post in an embodiment of the present invention;

[0067] Figure 21 This is a schematic diagram of the source connection block, gate connection block, and drain connection block in an embodiment of the present invention;

[0068] Figure 22 This is a schematic diagram of the heat dissipation port structure in an embodiment of the present invention;

[0069] Figure 23 This is a schematic diagram of the AlN layer structure in an embodiment of the present invention;

[0070] Figure 24 This is a schematic diagram of the structure of the back surface metal layer in an embodiment of the present invention.

[0071] In the attached figures: 1. Sapphire substrate; 2. GaN high-resistivity buffer layer; 3. GaN channel layer; 4. AlGaN barrier layer; 5. P-type GaN layer; 50. Gate mesa structure; 6. First passivation layer; 71. Source electrode; 72. Drain electrode; 73. Gate electrode; 8. Second passivation layer; 9. Third passivation layer; 10. Fourth passivation layer; 110. Isolation pit; 120. Mesa isolation structure; 210. Source opening; 220. Drain opening; 230. Gate opening; 310. Source via. 311, Source terminal block; 312, Source field plate; 320, Drain via; 321, Drain terminal block; 322, Drain field plate; 410, Source connection via; 411, Source connection post; 412, Source connection block; 420, Drain connection via; 421, Drain connection post; 422, Drain connection block; 430, Gate connection via; 431, Gate connection post; 432, Gate connection block; 510, Heat sink; 511, AlN layer; 512, Backplane metal layer; 600, Pad layer. Detailed Implementation

[0072] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0073] This invention provides a highly reliable GaN power device on a sapphire substrate. Figure 1This diagram illustrates the overall structure of a GaN power device on a sapphire substrate according to an embodiment of the present invention. The GaN power device on a sapphire substrate includes a sapphire substrate 1 and GaN high-resistivity buffer layer 2, GaN channel layer 3, AlGaN barrier layer 4, gate mesa structure 50, first passivation layer 6, electrode layer, and second passivation layer 8 sequentially stacked on the sapphire substrate 1. The electrode layer includes a source electrode 71, a gate electrode 73, and a drain electrode 72 arranged sequentially at intervals. A heat dissipation port is provided in the sapphire substrate 1, extending from the lower surface of the sapphire substrate 1 to the lower surface of the GaN high-resistivity buffer layer 2. The projection of the gate electrode 73 on the sapphire substrate 1 is located in the heat dissipation port. An AlN layer 511 and a back surface metal layer 512 are sequentially disposed in the heat dissipation port from top to bottom. The AlN layer 511 and the GaN high-resistivity buffer layer 2 are connected, and the back surface metal layer 512 extends out of the heat dissipation port and covers the lower surface of the sapphire substrate 1.

[0074] This invention provides a heat dissipation port in a sapphire substrate 1, which penetrates the substrate 1. The port is filled with an AlN layer 511 and a back surface metal layer 512. The AlN layer 511 directly contacts the GaN high-resistivity buffer layer 2. The AlN layer 511, with its high thermal conductivity, guides heat from the GaN power device on the sapphire substrate to the back surface metal layer 512, which then diffuses the heat. The back surface metal layer 512 covers the lower surface of the sapphire substrate 1, providing a large heat dissipation area and accelerating heat dissipation. The AlN layer 511 and the back surface metal layer 512 effectively improve the heat dissipation capacity of the GaN power device on the sapphire substrate, preventing heat accumulation during use and reducing the risk of performance degradation and device failure. This significantly enhances the reliability of the GaN power device on the sapphire substrate.

[0075] Furthermore, the back surface metal layer 512 can terminate the electric field lines and balance the electric field inside the GaN power device on the sapphire substrate, thereby effectively increasing the overall voltage withstand performance of the power device.

[0076] For details, please refer to Figure 1Mesa isolation structures are formed on both sides of the GaN high-resistivity buffer layer 2, the GaN channel layer 3, and the AlGaN barrier layer 4. The mesa isolation structures extend from the upper surface of the AlGaN barrier layer 4 into the GaN high-resistivity buffer layer 2, and divide the epitaxial layers (GaN high-resistivity buffer layer 2, GaN channel layer 3, and AlGaN barrier layer 4) into independent small units. The gate mesa structure 50 is close to one of the mesa isolation structures. The first passivation layer 6 covers the surfaces of the mesa isolation structure, the AlGaN barrier layer 4, and the gate mesa structure 50. The first passivation layer 6 can passivate and isolate the two-dimensional electron gas, avoid leakage current in the power device, and eliminate the current collapse effect.

[0077] The source electrode 71 and the drain electrode 72 are located on opposite sides of the gate mesa structure 50, and extend through the first passivation layer 6 to the upper surface of the AlGaN barrier layer 4; the gate electrode 73 is disposed on the gate mesa structure 50, and the bottom of the gate electrode 73 is in contact with the upper surface of the first passivation layer 6; the source electrode 71 is close to the gate electrode 73, and the drain electrode 72 is away from the gate electrode 73;

[0078] The second passivation layer 8 fills the uneven surfaces of the first passivation layer 6, the source electrode 71, and the drain electrode 72. The second passivation layer 8 can isolate the water vapor migration and ion migration inside the power device, thereby effectively improving the breakdown voltage performance of the power device.

[0079] For further details, please refer to Figure 1 The sapphire substrate GaN power device further includes a third passivation layer 9, a field plate metal layer, a fourth passivation layer 10, and an electrode connection layer sequentially stacked on the second passivation layer 8. The projection of the field plate metal layer on the second passivation layer 8 covers the electrode layer. The field plate metal layer includes a source field plate 312 and a drain field plate 322, which are spaced apart. The source field plate 312 extends vertically to the upper surface of the source electrode 71, and the drain field plate 322 extends vertically to the upper surface of the source electrode 71. The electrode connection layer extends vertically to the upper surface of the drain electrode 72; the electrode connection layer includes a source connection block 412, a gate connection block 432, and a drain connection block 422, the source connection block 412, the gate connection block 432, and the drain connection block 422 are spaced apart, the source connection block 412 extends vertically to the upper surface of the source field plate 312, the gate connection block 432 extends vertically to the upper surface of the gate electrode 73, and the drain connection block 422 extends vertically to the upper surface of the drain field plate 322.

[0080] The third passivation layer 9 can isolate the gate electrode 73 to facilitate the formation of the source field plate 312 and the drain field plate 322, which can adjust the breakdown voltage and capacitance effect of the power device. The field plate metal layer increases the electrode length of the source electrode 71 and the drain electrode 72, allowing the electric field lines to terminate at the source field plate 312 and the drain field plate 322, dispersing the electric field lines concentrated on the gate electrode 73 near the channel gate and the channel drain, thereby effectively improving the breakdown voltage of the power device. The fourth passivation layer 10 can isolate the source field plate 312 and the drain field plate 322 to facilitate the formation of the source connection block 412, the gate connection block 432 and the drain connection block 422, so that the gate electrode 73, the source field plate 312 and the drain field plate 322 can be redistributed on the fourth passivation layer 10 through the electrode connection layer, so as to facilitate the subsequent soldering and packaging of the power device.

[0081] For details, please refer to Figure 1 The projection of the source field plate 312 on the second passivation layer 8 covers the source electrode 71 and the gate electrode 73, and the projection of the drain field plate 322 on the second passivation layer 8 covers the drain electrode 72; the projections of the source field plate 312 and the drain field plate 322 on the second passivation layer 8 avoid the mesa isolation structure, so as to avoid damage to the field plate metal layer when cutting and dicing along the mesa isolation structure.

[0082] In some specific embodiments, please refer to Figure 1 The lower surface of the back surface metal layer 512 is connected to a pad layer 600 based on conductive die bond adhesive or solder paste. During packaging, the pad layer 600 is soldered to the pins, and then the pins are connected to the ground wire, so that the back surface metal layer 512 and the ground terminal are connected together. Because the barrier height formed by the GaN channel layer 3 or the AlGaN barrier layer 4 is relatively low, some electrons are prone to leaking over the barrier to the GaN high-resistivity buffer layer 2, forming an additional depletion region and a high electric field in the GaN high-resistivity buffer layer 2. The excessively high electric field can easily cause the GaN high-resistivity buffer layer 2 to break down. By grounding the back field metal layer 512, a low potential surface can be formed, so that the high electric field concentrated in the GaN high-resistivity buffer layer 2 is vertically cut off by the back field metal layer 512, balancing the electric field distribution. Moreover, the grounded back field metal layer 512 can also terminate the edge electric field of the gate electrode 73 part downward, which can reduce the risk of GaN high-resistivity buffer layer 2 breakdown caused by the electric field lines concentrating in a small space, thereby effectively increasing the overall withstand voltage performance of the power device.

[0083] This invention also provides a method for fabricating a high-reliability GaN power device on a sapphire substrate, the method being used to fabricate the aforementioned GaN power device on the sapphire substrate. Figure 2A flowchart illustrating a method for fabricating a GaN power device on a sapphire substrate according to an embodiment of the present invention is shown, including the following steps:

[0084] S1. Sequentially form a GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer, a gate mesa structure, a first passivation layer, a source electrode and a drain electrode, a second passivation layer, and a gate electrode on a sapphire substrate.

[0085] Specifically, Figure 3 The following is a flowchart illustrating step S1 in an embodiment of the present invention. Step S1 includes:

[0086] S110. A GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer are sequentially grown on a sapphire substrate to obtain an epitaxial wafer.

[0087] Figure 4 A schematic diagram of the epitaxial wafer structure in an embodiment of the present invention is shown.

[0088] The growth of each film layer was carried out using a metal-organic chemical vapor deposition (MOCVD) system.

[0089] Specifically, the thickness of the sapphire substrate 1 ranges from 100 to 1000 μm; the thickness of the GaN high-resistivity buffer layer 2 ranges from 1 to 4 μm; the thickness of the GaN channel layer 3 ranges from 0.1 to 1 μm; the thickness of the AlGaN barrier layer 4 ranges from 0.01 to 0.5 μm; and the thickness of the P-type GaN layer 5 ranges from 0.01 to 0.5 μm.

[0090] S111. An isolation pit is formed by etching in a predetermined area of ​​the epitaxial wafer. The isolation pit extends from the upper surface of the P-type GaN layer to the GaN high-resistivity buffer layer.

[0091] Figure 5 A schematic diagram of the isolation pit in an embodiment of the present invention is shown.

[0092] The plasma etching (ICP) method is used to etch from the upper surface of the P-type GaN layer 5 in a predetermined area until a portion of the GaN high-resistivity buffer layer 2 is etched, thereby forming an isolation pit 110. The isolation pit 110 divides the epitaxial layers (GaN high-resistivity buffer layer 2, GaN channel layer 3, AlGaN barrier layer 4 and P-type GaN layer 5) into independent small units, providing a basis for the formation of individual power devices.

[0093] Specifically, the etching gas can be one or more of BCl3, Cl2, Ar, and N2.

[0094] In some specific embodiments, before etching to form the isolation pit 110, the surface of the epitaxial wafer is cleaned with acetone solution and SPM solution respectively to obtain a first clean epitaxial wafer, the first clean epitaxial wafer is rinsed with flowing deionized water to obtain a second clean epitaxial wafer, and the second clean epitaxial wafer is dried with nitrogen gas for later use; the SPM solution is a mixed solution of sulfuric acid and hydrogen peroxide, and the SPM solution is prepared by mixing 98% H2SO4 and 30% H2O2 in a 4:1 ratio.

[0095] S112. The P-type GaN layer in the preset area is removed by mask etching to expose the AlGaN barrier layer, and the remaining P-type GaN layer forms a gate mesa structure on the AlGaN barrier layer.

[0096] Figure 6 A schematic diagram of the gate mesa structure in an embodiment of the present invention is shown.

[0097] The areas of the P-type GaN layer 5 that need to be preserved are protected by photolithography patterning, and the areas of the P-type GaN layer 5 that do not need to be preserved are etched away by plasma etching (ICP) to form the gate mesa structure 50. The etching gas can be one or more of BCl3, Cl2, Ar, and N2.

[0098] The gate mesa structure 50 can raise the potential barrier at the channel, thereby depleting the two-dimensional electron gas in the channel and turning the normally on GaN device into a normally off enhancement-mode GaN device.

[0099] Specifically, after the P-type GaN layer 5 in the preset area is etched away, the isolation pit 110 forms a mesa isolation structure 120. The mesa isolation structure 120 extends from the upper surface of the AlGaN barrier layer 4 into the GaN high-resistivity buffer layer 2. The mesa isolation structure 120 divides the epitaxial layer (GaN high-resistivity buffer layer 2, GaN channel layer 3 and AlGaN barrier layer 4) into individual small units, which facilitates subsequent dicing and splitting along the mesa isolation structure 120.

[0100] S113. A first passivation layer is deposited along the surface of the mesa isolation structure, the AlGaN barrier layer and the gate mesa structure.

[0101] Figure 7 A schematic diagram of the structure of the first passivation layer in an embodiment of the present invention is shown.

[0102] The first passivation layer 6 is deposited by means of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The first passivation layer 6 can passivate and isolate two-dimensional electron gas, prevent leakage current from power devices, and eliminate current collapse effect.

[0103] The material of the first passivation layer 6 can be SiN, SiO2, or SiO2. x N y One or more of them, wherein the thickness of the first passivation layer 6 ranges from 5 to 200 nm.

[0104] S114. Etch a source opening and a drain opening in a preset area of ​​the first passivation layer;

[0105] Figure 8 A schematic diagram of the source and drain openings in an embodiment of the present invention is shown.

[0106] The source opening 210 and the drain opening 220 are formed by etching using plasma etching (ICP). The etching gas can be one or more of Ar, O2, N2, CF4, and SF6.

[0107] Specifically, the source opening 210 and the drain opening 220 are located on opposite sides of the gate mesa structure 50, with the source opening 210 close to the gate mesa structure 50 and the drain opening 220 far from the gate mesa structure 50; the source opening 210 and the drain opening 220 expose the AlGaN barrier layer 4, providing a basis for the formation of the source electrode 71 and the drain electrode 72.

[0108] S115. A source electrode is deposited in the source opening to form a source electrode, and a drain electrode is deposited in the drain opening to form a drain electrode;

[0109] Figure 9 A schematic diagram of the source electrode and drain electrode in an embodiment of the present invention is shown.

[0110] Metal materials are deposited in the source opening 210 and drain opening 220 by means of magnetron sputtering or electron beam evaporation, and then the metal is patterned by plasma etching ICP or photoresist wet stripping process to form source electrode 71 and drain electrode 72. The material of source electrode 71 and drain electrode 72 can be one or more of Ti, Ni, Al, Au, Pt, Ag, W, Cu, TiW, TiN, and the thickness of source electrode 71 and drain electrode 72 ranges from 0.2 to 1 μm.

[0111] Specifically, after the source electrode 71 and the drain electrode 72 are formed, they are annealed in a nitrogen atmosphere to form a good ohmic contact; the annealing temperature is 500-1000℃.

[0112] S116. A second passivation layer is deposited on the surface of the first passivation layer, the source electrode, and the drain electrode, and the second passivation layer fills the uneven surfaces of the first passivation layer, the source electrode, and the drain electrode.

[0113] Figure 10 A schematic diagram of the structure of the second passivation layer in an embodiment of the present invention is shown.

[0114] The second passivation layer 8 is deposited by means of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The second passivation layer 8 can isolate water vapor migration and ion migration inside the power device, thereby effectively improving the breakdown voltage performance of the power device. The second passivation layer 8 fills the uneven surface, which facilitates the formation of subsequent film layers.

[0115] The material of the second passivation layer 8 can be SiN, SiO2, or SiO2. x N y One or more of them.

[0116] S117. A gate opening is formed by etching in a preset area of ​​the second passivation layer. The gate opening is located above the gate mesa structure and exposes the first passivation layer.

[0117] Figure 11 A schematic diagram of the gate opening structure in an embodiment of the present invention is shown.

[0118] The second passivation layer 8 above the gate mesa structure 50 is removed by dry etching or wet etching to form the gate opening 230, providing a basis for the formation of the gate electrode 73.

[0119] S118. A gate electrode is deposited in the gate opening to form a gate electrode;

[0120] Figure 12 A schematic diagram of the planar structure of the gate electrode in an embodiment of the present invention is shown.

[0121] The gate electrode 73 is formed by electron beam evaporation. The material of the gate electrode 73 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, and Ag. The thickness of the gate electrode 73 ranges from 0.1 to 1 μm.

[0122] Figure 13 A three-dimensional structural schematic diagram of the gate electrode in an embodiment of the present invention is shown.

[0123] The main body of the gate electrode 73 is a relatively thin strip structure. In order to facilitate the subsequent lead-out of the gate electrode 73, a gate metal connection part with a larger area is usually formed at one end of the gate electrode 73.

[0124] Furthermore, after step S118, the following is also included:

[0125] S119. A third passivation layer is deposited on the surface of the second passivation layer and the gate electrode;

[0126] Figure 14 A schematic diagram of the structure of the third passivation layer in an embodiment of the present invention is shown.

[0127] The third passivation layer 9 is deposited by means of plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The third passivation layer 9 can isolate the gate electrode 73 to facilitate the subsequent formation of the source field plate 312 and the drain field plate 322, and can adjust the voltage withstand performance and capacitance effect of the power device.

[0128] The material of the third passivation layer 9 can be SiN, SiO2, or SiO2. x N y One or more of them, the thickness of the third passivation layer 9 ranges from 0.2 to 1.5 μm.

[0129] S120. Source holes and drain holes are etched in a preset area of ​​the third passivation layer, the source holes exposing the source electrode and the drain holes exposing the drain electrode.

[0130] Figure 15 A schematic diagram of the source and drain holes in an embodiment of the present invention is shown.

[0131] The film layer above the source electrode 71 and the drain electrode 72 is removed by dry etching or wet etching to form source hole 310 and drain hole 320, which provides a basis for subsequent forming of source post 311 and drain post 321.

[0132] S121. A source electrode post is deposited in the source electrode cavity to form a source electrode post, and a drain electrode post is deposited in the drain electrode cavity to form a drain electrode post;

[0133] Figure 16 A schematic diagram of the source and drain terminals in an embodiment of the present invention is shown.

[0134] Source post 311 and drain post 321 are deposited using electron beam evaporation. The materials of source post 311 and drain post 321 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, and Ag.

[0135] S122, A source field plate and a drain field plate are deposited in the preset region of the third passivation layer;

[0136] Figure 17The diagram illustrates the structure of the source field plate and the drain field plate in an embodiment of the present invention. The source field plate 312 and the drain field plate 322 are deposited using electron beam evaporation. The materials of the source field plate 312 and the drain field plate 322 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, and Ag. The thickness of the source field plate 312 and the drain field plate 322 ranges from 0.2 to 2 μm.

[0137] The source field plate 312 and the source terminal 311 are connected as one unit, and the drain field plate 322 and the drain terminal 321 are connected as one unit. The projection of the source field plate 312 on the second passivation layer 8 covers the source electrode 71 and the gate electrode 73, and the projection of the drain field plate 322 on the second passivation layer 8 covers the drain electrode 72. The source field plate 312 and the source terminal 311 increase the electrode length of the source electrode 71, and the drain field plate 322 and the drain terminal 321 increase the electrode length of the drain electrode 72. This allows the electric field lines to terminate at the source field plate 312 and the drain field plate 322, dispersing the electric field lines concentrated on the gate electrode 73 near the channel gate and the channel drain, thereby effectively improving the breakdown voltage performance of the power device.

[0138] The projections of the source field plate 312 and the drain field plate 322 onto the second passivation layer 8 avoid the mesa isolation structure 120, thus preventing damage to the field plate metal layer when cutting and dicing along the mesa isolation structure 120.

[0139] S123. A fourth passivation layer is deposited on the surface of the third passivation layer, the source field plate, and the drain field plate;

[0140] Figure 18 A schematic diagram of the structure of the fourth passivation layer in an embodiment of the present invention is shown.

[0141] The fourth passivation layer 10 is deposited by means of plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The fourth passivation layer 10 can isolate the source field plate 312 and the drain field plate 322, so as to facilitate the subsequent formation of the source connection block 412, the gate connection block 432, and the drain connection block 422. This allows the gate electrode 73, the source field plate 312, and the drain field plate 322 to achieve the redistribution of the electrode region on the fourth passivation layer 10 through the electrode connection layer, so as to facilitate the subsequent soldering and packaging of the power device.

[0142] The material of the fourth passivation layer 10 can be SiN, SiO2, or SiO2. x N y One or more of them, the thickness of the fourth passivation layer 10 ranges from 0.3 to 3 μm.

[0143] S124. Source connection hole, gate connection hole and drain connection hole are etched in the preset area of ​​the fourth passivation layer.

[0144] Figure 19 A schematic diagram of the source connection hole, gate connection hole, and drain connection hole in an embodiment of the present invention is shown.

[0145] First, the fourth passivation layer 10 on a portion of the surface of the source field plate 312 and the drain field plate 322 is removed by dry etching or wet etching to form source connection holes 410 and drain connection holes 420; the source connection holes 410 expose the source field plate 312 and the drain connection holes 420 expose the drain field plate 322.

[0146] The third passivation layer 9 and the fourth passivation layer 10 on a portion of the surface of the gate metal connection portion of the gate electrode 73 are then removed by dry etching or wet etching to form a gate connection hole 430. The gate connection hole 430 exposes the gate metal connection portion of the gate electrode 73 and does not contact the source field plate 312.

[0147] S125. A source connection post is deposited in the source connection hole to form a source connection post, a gate connection post is deposited in the gate connection hole to form a gate connection post, and a drain connection post is deposited in the drain connection hole to form a drain connection post.

[0148] Figure 20 A schematic diagram of the source connection post, gate connection post, and drain connection post in an embodiment of the present invention is shown.

[0149] First, source connection post 411 and drain connection post 421 are deposited using electron beam evaporation, and then gate connection post 431 is deposited using electron beam evaporation. The materials of source connection post 411, drain connection post 421 and gate connection post 431 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, Ag and AuSn.

[0150] S126. A source connection block, a gate connection block, and a drain connection block are deposited in a predetermined region of the fourth passivation layer.

[0151] Figure 21 A schematic diagram of the source connection block, gate connection block, and drain connection block in an embodiment of the present invention is shown.

[0152] Source connector 412, gate connector 432, and drain connector 422 are deposited using electron beam evaporation. The materials of source connector 412, gate connector 432, and drain connector 422 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, Ag, and AuSn. The thickness of source connector 412, gate connector 432, and drain connector 422 ranges from 0.2 to 2 μm. The source connector 412 and the source connector post 411 are connected as one unit, the gate connector 432 and the gate connector post 431 are connected as one unit, and the drain connector 422 and the drain connector post 421 are connected as one unit.

[0153] The source connection block 412, the gate connection block 432 and the drain connection block 422 redistribute the electrode regions on the fourth passivation layer 10 to facilitate subsequent soldering and packaging of the power device.

[0154] S2. A heat dissipation port is etched in a predetermined area of ​​the sapphire substrate, and the heat dissipation port exposes the GaN high-resistivity buffer layer; the projection of the gate electrode on the sapphire substrate is located in the heat dissipation port;

[0155] Figure 22 A schematic diagram of the heat dissipation port in an embodiment of the present invention is shown.

[0156] The heat dissipation port 510 is formed by wet stripping of photoresist for photolithography. The heat dissipation port 510 exposes the GaN high-resistivity buffer layer 2, which facilitates heat dissipation. Moreover, the remaining sapphire substrate 1 can play a self-supporting role. Compared with the fully stripped substrate structure, the process of opening the heat dissipation port 510 is simpler and more stable, and will not cause thin film breakage and bonding support problems due to the fully stripped substrate.

[0157] Specifically, the distance from the left side of the source electrode 71 to the right side of the gate electrode 73 is L1, the distance from the left side of the source electrode 71 to the right side of the drain electrode 72 is L2, and the width of the heat dissipation port 510 is A. The constraint relationship between L1, L2, and A is: L1≤A≤L2. The heat of the power device is generally concentrated at the edge of the gate electrode 73, so the heat dissipation port 510 must encompass the projection of the gate electrode 73 onto the sapphire substrate 1 to facilitate heat dissipation and effectively alleviate the heat accumulation problem caused by the low heat dissipation coefficient of the sapphire substrate 1.

[0158] Before etching to form the heat dissipation port 510, the process further includes: thinning the sapphire substrate 1 to 100-300 μm and polishing the bottom surface of the thinned sapphire substrate 1.

[0159] Specifically, a grinding machine is used to thin the sapphire substrate 1, and a polishing machine is used to polish the sapphire substrate 1.

[0160] The thickness of the polished sapphire substrate 1 ranges from 80 to 280 μm. If the thickness of the sapphire substrate 1 is less than 80 μm, it is easy to cause breakage.

[0161] S3. An AlN layer is deposited in the heat dissipation port, wherein the thickness of the AlN layer is less than the depth of the heat dissipation port;

[0162] Figure 23 A schematic diagram of the AlN layer in an embodiment of the present invention is shown.

[0163] A 1-2 μm thick AlN layer 511 is deposited in the heat dissipation port 510 using magnetron sputtering technology. AlN has a high dielectric constant and high thermal conductivity, which allows the AlN layer 511 to prevent leakage current from flowing down the GaN channel layer 3 and the GaN high-resistivity buffer layer 2. It can also guide the heat inside the GaN power device on the sapphire substrate out, thereby improving the heat dissipation capability of the power device.

[0164] AlN layer 511 can also serve as a back field dielectric layer, with its thickness controlled to not exceed 2μm. If AlN layer 511 is too thick, it will weaken the effectiveness of the subsequently deposited back field metal layer 512 and make AlN layer 511 prone to cracking due to stress, affecting the subsequent deposition of back field metal layer 512.

[0165] S4. A back field metal layer is deposited on the side of the sapphire substrate away from the GaN high-resistivity buffer layer, and the back field metal layer covers the AlN layer and the sapphire substrate;

[0166] Figure 24 A schematic diagram of the structure of the back surface metal layer in an embodiment of the present invention is shown.

[0167] A back surface metal layer 512 is deposited on the surface of AlN layer 511 using magnetron sputtering technology. The back surface metal layer 512 fills the heat dissipation port 510 and covers the bottom surface of sapphire substrate 1. The thickness of the back surface metal layer 512 covering the bottom surface of sapphire substrate 1 (excluding the back surface metal layer 512 filling the heat dissipation port 510) ranges from 200 to 2000 nm. The AlN layer 511 guides the heat inside the GaN power device on the sapphire substrate to the back surface metal layer 512, which then diffuses the heat. The back surface metal layer 512 covers the lower surface of the sapphire substrate 1, providing a large heat dissipation area and accelerating the heat dissipation effect. The AlN layer 511 and the back surface metal layer 512 effectively improve the heat dissipation capacity of the GaN power device on the sapphire substrate, helping to avoid heat accumulation during use, thereby reducing the risk of performance degradation and device failure, and greatly enhancing the reliability of the GaN power device on the sapphire substrate.

[0168] Furthermore, the depletion region of the power device is the channel range from the source electrode 71 to the drain electrode 72, especially the channel range from the gate electrode 73 to the drain electrode 72, which is also the range of the heat sink 510; part of the back field metal layer 512 fills the heat sink 510, and the AlN layer 511 is used as the dielectric layer, which can effectively disperse the electric field of the depletion region.

[0169] Specifically, the material of the back field plate metal layer 512 can be one or more of Ti, Ni, Cr, Au, Pt, Sn, Al, Cu, Ag, and AuSn.

[0170] During packaging, power devices are soldered onto pad layer 600 using a highly thermally conductive die bond (such as Ag glue) or solder paste. The pad layer 600 is then used to solder pins, which are then connected to the ground wire, thus connecting the back panel metal layer 512 and the ground terminal together. Because the barrier height formed by the GaN channel layer 3 or the AlGaN barrier layer 4 is relatively low, some electrons are prone to leaking over the barrier to the GaN high-resistivity buffer layer 2, forming an additional depletion region and a high electric field in the GaN high-resistivity buffer layer 2. The excessively high electric field can easily cause the GaN high-resistivity buffer layer 2 to break down. By grounding the back field metal layer 512, a low potential surface can be formed, so that the high electric field concentrated in the GaN high-resistivity buffer layer 2 is vertically cut off by the back field metal layer 512, balancing the electric field distribution. Moreover, the grounded back field metal layer 512 can also terminate the edge electric field of the gate electrode 73 part downward, which can reduce the risk of GaN high-resistivity buffer layer 2 breakdown caused by the electric field lines concentrating in a small space, thereby effectively increasing the overall withstand voltage performance of the power device.

[0171] This invention can improve the heat dissipation effect of GaN power devices on sapphire substrates, increase the internal heat transfer capacity of GaN power devices on sapphire substrates, and solve the problem of heat accumulation in the near-junction region of GaN; it can also improve the withstand voltage performance of GaN power devices on sapphire substrates; thereby effectively improving the high-power characteristics and reliability of GaN power devices on sapphire substrates.

[0172] Compared to substrate transfer technology, the method of this invention is more effective and less expensive.

[0173] The above provides a detailed description of a high-reliability GaN power device on a sapphire substrate and its fabrication method provided by embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A high-reliability GaN power device on a sapphire substrate, characterized in that, The sapphire substrate GaN power device includes a sapphire substrate and GaN high-resistivity buffer layer, GaN channel layer, AlGaN barrier layer, gate mesa structure, first passivation layer, electrode layer and second passivation layer sequentially stacked on the sapphire substrate. The electrode layer includes source electrode, gate electrode and drain electrode arranged sequentially at intervals. A heat dissipation port is provided in the sapphire substrate, extending from the lower surface of the sapphire substrate to the lower surface of the GaN high-resistivity buffer layer; the projection of the gate electrode on the sapphire substrate is located in the heat dissipation port; an AlN layer and a back surface plate metal layer are sequentially disposed in the heat dissipation port from top to bottom, the AlN layer and the GaN high-resistivity buffer layer are connected, and the back surface plate metal layer extends out of the heat dissipation port and covers the lower surface of the sapphire substrate; The source electrode and the drain electrode are located on both sides of the gate mesa structure, and the source electrode and the drain electrode extend through the first passivation layer to the upper surface of the AlGaN barrier layer; The gate electrode is disposed on the gate mesa structure, and the bottom of the gate electrode is in contact with the upper surface of the first passivation layer; The source electrode is close to the gate electrode, and the drain electrode is far from the gate electrode; The second passivation layer fills the uneven surfaces of the first passivation layer, the source electrode, and the drain electrode.

2. The sapphire substrate GaN power device as described in claim 1, characterized in that, Mesa isolation structures are formed on both sides of the GaN high-resistivity buffer layer, the GaN channel layer, and the AlGaN barrier layer. The mesa isolation structures extend from the upper surface of the AlGaN barrier layer into the GaN high-resistivity buffer layer. The gate mesa structure is close to one of the mesa isolation structures. The first passivation layer covers the surfaces of the mesa isolation structure, the AlGaN barrier layer, and the gate mesa structure.

3. The sapphire substrate GaN power device as described in claim 2, characterized in that, The sapphire substrate GaN power device further includes a third passivation layer, a field plate metal layer, a fourth passivation layer, and an electrode connection layer sequentially stacked on the second passivation layer. The projection of the field plate metal layer on the second passivation layer covers the electrode layer. The field plate metal layer includes a source field plate and a drain field plate, which are spaced apart. The source field plate extends vertically to the upper surface of the source electrode, and the drain field plate extends vertically to the upper surface of the drain electrode. The electrode connection layer includes a source connection block, a gate connection block, and a drain connection block. The source connection block, the gate connection block, and the drain connection block are spaced apart. The source connection block extends vertically to the upper surface of the source field plate, the gate connection block extends vertically to the upper surface of the gate electrode, and the drain connection block extends vertically to the upper surface of the drain field plate.

4. The sapphire substrate GaN power device as described in claim 1, characterized in that, The lower surface of the backplane metal layer is connected to a pad layer based on conductive die bond adhesive or solder paste.

5. A method for fabricating a high-reliability GaN power device on a sapphire substrate, characterized in that, The preparation method described above is used to prepare the sapphire substrate GaN power device according to any one of claims 1 to 4, and includes the following steps: S1. Sequentially form a GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer, a gate mesa structure, a first passivation layer, a source electrode and a drain electrode, a second passivation layer, and a gate electrode on a sapphire substrate. S2. A heat dissipation port is etched in a predetermined area of ​​the sapphire substrate, and the heat dissipation port exposes the GaN high-resistivity buffer layer; the projection of the gate electrode on the sapphire substrate is located in the heat dissipation port; S3. An AlN layer is deposited in the heat dissipation port, wherein the thickness of the AlN layer is less than the depth of the heat dissipation port; S4. A back field metal layer is deposited on the side of the sapphire substrate away from the GaN high-resistivity buffer layer, and the back field metal layer covers the AlN layer and the sapphire substrate.

6. The preparation method according to claim 5, characterized in that, Step S1 includes: S110. A GaN high-resistivity buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer are sequentially grown on a sapphire substrate to obtain an epitaxial wafer. S111. An isolation pit is formed by etching in a predetermined area of ​​the epitaxial wafer. The isolation pit extends from the upper surface of the P-type GaN layer to the GaN high-resistivity buffer layer. S112. The P-type GaN layer in the preset area is removed by mask etching to expose the AlGaN barrier layer, and the remaining P-type GaN layer forms a gate mesa structure on the AlGaN barrier layer. The isolation pit forms a mesa isolation structure, which extends from the upper surface of the AlGaN barrier layer to the GaN high-resistivity buffer layer. S113. A first passivation layer is deposited along the surface of the mesa isolation structure, the AlGaN barrier layer and the gate mesa structure. S114. A source opening and a drain opening are etched in a preset area of ​​the first passivation layer; the source opening and the drain opening are respectively located on both sides of the gate mesa structure, the source opening is close to the gate mesa structure, and the drain opening is far away from the gate mesa structure; the source opening and the drain opening expose the AlGaN barrier layer. S115. A source electrode is deposited in the source opening to form a source electrode, and a drain electrode is deposited in the drain opening to form a drain electrode; S116. A second passivation layer is deposited on the surface of the first passivation layer, the source electrode, and the drain electrode, and the second passivation layer fills the uneven surfaces of the first passivation layer, the source electrode, and the drain electrode. S117. A gate opening is formed by etching in a preset area of ​​the second passivation layer. The gate opening is located above the gate mesa structure and exposes the first passivation layer. S118, A gate electrode is deposited in the gate opening to form a gate electrode.

7. The preparation method according to claim 6, characterized in that, The process also includes the following after step S118: S119. A third passivation layer is deposited on the surface of the second passivation layer and the gate electrode; S120. Source holes and drain holes are etched in a preset area of ​​the third passivation layer, the source holes exposing the source electrode and the drain holes exposing the drain electrode. S121. A source electrode post is deposited in the source electrode cavity to form a source electrode post, and a drain electrode post is deposited in the drain electrode cavity to form a drain electrode post; S122, A source field plate and a drain field plate are deposited in a predetermined region of the third passivation layer; the source field plate is connected to the source terminal, and the drain field plate is connected to the drain terminal; the projection of the source field plate on the second passivation layer covers the source electrode and the gate electrode, and the projection of the drain field plate on the second passivation layer covers the drain electrode. S123. A fourth passivation layer is deposited on the surface of the third passivation layer, the source field plate, and the drain field plate; S124. Source connection holes, gate connection holes, and drain connection holes are etched in a preset area of ​​the fourth passivation layer; the source connection holes expose the source field plate, the gate connection holes expose the gate electrode, and the drain connection holes expose the drain field plate. S125. A source connection post is deposited in the source connection hole to form a source connection post, a gate connection post is deposited in the gate connection hole to form a gate connection post, and a drain connection post is deposited in the drain connection hole to form a drain connection post. S126. A source connection block, a gate connection block, and a drain connection block are deposited in a preset region of the fourth passivation layer; the source connection block is connected to the source connection post, the gate connection block is connected to the gate connection post, and the drain connection block is connected to the drain connection post.

8. The preparation method according to claim 6, characterized in that, The steps preceding step S111 also include: The surface of the epitaxial wafer is cleaned with acetone solution and SPM solution respectively to obtain a first clean epitaxial wafer. The first clean epitaxial wafer is rinsed with flowing deionized water to obtain a second clean epitaxial wafer. The second clean epitaxial wafer is dried with nitrogen gas. The SPM solution is a mixture of sulfuric acid and hydrogen peroxide.

9. The preparation method according to claim 6, characterized in that, Step S115 also includes: The source electrode and the drain electrode are annealed in a nitrogen atmosphere; the annealing temperature is 500-1000℃.

10. The preparation method according to claim 5, characterized in that, The steps preceding step S2 also include: The sapphire substrate is thinned to 100-300 μm, and the bottom surface of the thinned sapphire substrate is polished.

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