A semiconductor structure and a method of fabricating the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a chip stack disposed on the substrate by a plurality of first conductive structures, wherein the first conductive structure comprises a first conductive bump, the first conductive bump comprises at least one concave surface, and the concave surfaces on adjacent first conductive bumps are oppositely disposed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Typically, high-bandwidth memory (HBM) chips are stacked on the top surface of a package substrate. The HBM chip is electrically connected to the package substrate via conductive bumps. The development of 3D packaging stacking technology, driven by the demand for high bandwidth and low power consumption, has led to higher chip stacking and denser through-silicon via (TSV) interconnects. However, higher HBM integration density results in larger parasitic parameters in the interconnects. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor structure and a method for preparing the same.

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0005] substrate;

[0006] A chip stack is disposed on the substrate through multiple first conductive structures;

[0007] The first conductive structure includes a first conductive bump, which includes at least one concave surface, and the concave surfaces on adjacent first conductive bumps are arranged opposite to each other.

[0008] In some embodiments, the first conductive structure is arranged in a square pattern, and in each of the multiple first conductive structures arranged in a square pattern, the concave surfaces of the first conductive bumps of the two first conductive structures at the diagonal positions are arranged opposite each other.

[0009] In some embodiments, the distance from the intersection of the diagonals of each of the four square arrangements to the concave surface of each of the first conductive bumps is a first distance, and the distance from the concave surface of the first conductive bump to the center of the first conductive bump is a second distance, and the ratio of the first distance to the second distance is 5:3 to 5:2.

[0010] In some embodiments, the first conductive bump further includes at least one convex surface, which is disposed adjacent to the concave surface.

[0011] In some embodiments, in each of the multiple first conductive structures arranged in a square, the first conductive bump of each first conductive structure includes multiple concave surfaces, and a convex surface is disposed between two adjacent concave surfaces, wherein the area of ​​the concave surface is larger than the area of ​​the convex surface.

[0012] In some embodiments, the first conductive structure further includes a first through-silicon via (TSV) and a first test pad, wherein the TSV is located on the first conductive bump and the first test pad is located between the TSV and the first conductive bump.

[0013] In some embodiments, the first conductive bump includes a first pad and a first solder ball, wherein the first pad is located on the first solder ball;

[0014] Wherein, the orthographic projection of the first pad on the substrate is located inside the orthographic projection of the first solder ball on the substrate.

[0015] In some embodiments, the first pad includes a first sub-pad and a second sub-pad, wherein the first sub-pad is located on the second sub-pad;

[0016] The volume of the first sub-pad is smaller than the volume of the second sub-pad.

[0017] In some embodiments, the chip stack comprises a plurality of chips stacked sequentially, each chip comprising n first conductive structures, where n is greater than or equal to 2;

[0018] In a projection along a plane perpendicular to the substrate, the projections of the first through-silicon vias of the corresponding first conductive structures in two adjacent chip layers do not overlap.

[0019] In some embodiments, it also includes:

[0020] The second conductive structure is located at the intersection of the diagonals of each square arrangement; the second conductive structure includes a second conductive bump, the second conductive bump including at least one concave surface.

[0021] In some embodiments, each concave surface of the second conductive bump is disposed opposite to one concave surface of the first conductive bump adjacent to it.

[0022] In some embodiments, the first conductive structure is a signal conductive structure, and the second conductive structure is a ground conductive structure.

[0023] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0024] Provide substrate;

[0025] A chip stack is formed, and a plurality of first conductive structures are formed on the chip stack; the chip stack is disposed on the substrate through the first conductive structures.

[0026] The first conductive structure includes a first conductive bump, which includes at least one concave surface, and the concave surfaces on adjacent first conductive bumps are arranged opposite to each other.

[0027] In some embodiments, forming the first conductive structure includes:

[0028] An initial first conductive structure is formed, the initial first conductive structure including an initial first conductive bump, the initial first conductive bump being circular in shape;

[0029] At least one first mask layer is formed on each of the initial first conductive bumps, the first mask layer covering a portion of the periphery of the initial first conductive bump;

[0030] The portion of the initial first conductive bump covered by the first mask layer is etched away to form the first conductive structure.

[0031] In some embodiments, the first conductive structure is arranged in a square pattern, and in each of the multiple first conductive structures arranged in a square pattern, the concave surfaces of the first conductive bumps of the two first conductive structures at the diagonal positions are arranged opposite each other.

[0032] In some embodiments, it also includes:

[0033] A second conductive structure is formed at the intersection of each of the four diagonal lines arranged in a square. The second conductive structure includes a second conductive bump, and the second conductive bump includes at least one concave surface.

[0034] In some embodiments, forming the second conductive structure includes:

[0035] An initial second conductive structure is formed at the intersection of each of the four diagonal lines arranged in a square; the initial second conductive structure includes an initial second conductive bump, and the initial second conductive bump is circular in shape;

[0036] A second mask layer is formed at the middle position of the initial second conductive bump, the second mask layer including at least one concave surface;

[0037] The portion of the initial second conductive bump not covered by the second mask layer is etched away to form the second conductive structure.

[0038] In this embodiment, when a signal passes through one of the first conductive bumps, the edge field radiation effect causes parasitic RLC to be introduced into other surrounding first conductive bumps, and this RLC is inversely proportional to the distance; the farther the distance, the weaker the edge field radiation effect. Therefore, by setting the concave surfaces of adjacent first conductive bumps opposite each other, the overlap range of the edge field in space is reduced, thereby reducing the parasitic parameters caused by edge field radiation. Simultaneously, by setting the first conductive bump to include at least one concave surface, the volume of the first conductive bump is reduced, thereby reducing the parasitic capacitance of the first conductive bump itself. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the first conductive structure in the prior art;

[0041] Figure 2 A perspective view of the first conductive structure provided in an embodiment of this disclosure;

[0042] Figure 3 This is a schematic diagram of the structure of the first conductive structure provided in an embodiment of the present disclosure;

[0043] Figure 4 This is an enlarged view of the convex surface of the first conductive bump;

[0044] Figure 5a and Figure 5b Other examples of the first conductive structure provided in the embodiments of this disclosure;

[0045] Figure 6a This is a schematic diagram of the structure of the first conductive structure provided in another embodiment of the present disclosure;

[0046] Figure 6b A perspective view of a first conductive structure provided in another embodiment of this disclosure;

[0047] Figure 7 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0048] Figure 8 This is a schematic diagram showing the connection between two adjacent chip layers via a first interconnect line.

[0049] Figure 9 A flowchart illustrating a method for fabricating a semiconductor structure according to embodiments of this disclosure;

[0050] Figures 10a to 10h This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process.

[0051] Explanation of reference numerals in the attached figures:

[0052] 10-Substrate;

[0053] 20 - Chip stack; 21 - Chip;

[0054] 30, 30' - First conductive structure; 31, 31' - First conductive bump; 311 - First pad; 311a - First sub-pad; 311b - Second sub-pad; 312 - First solder ball; 301 - Concave surface; 302 - Convex surface; 32 - First through-silicon via; 33 - First test pad; 300 - Initial first conductive structure; 310 - Initial first conductive bump;

[0055] 40 - Second conductive structure; 41 - Second conductive bump; 400 - Initial second conductive structure; 410 - Initial second conductive bump;

[0056] 61 - First mask layer; 62 - Second mask layer;

[0057] 71 - First interconnect. Detailed Implementation

[0058] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0060] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0064] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0065] In existing technologies, such as Figure 1 As shown, the first conductive bump 31' in the first conductive structure 30' is circular in shape. The circular first conductive bump 31' has a large RLC parasitic parameter, which has an increasingly greater impact on signal integrity and thus affects the performance of the memory.

[0066] This disclosure provides a semiconductor structure.

[0067] Figure 2 This is a perspective view of the first conductive structure provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the first conductive structure provided in an embodiment of the present disclosure.

[0068] like Figure 2 and Figure 3 As shown, the first conductive structure 30 includes a first conductive bump 31, the first conductive bump 31 includes at least one concave surface 301, and the concave surfaces 301 on adjacent first conductive bumps 31 are disposed opposite to each other.

[0069] In this embodiment, when a signal passes through one of the first conductive bumps, the edge field radiation effect causes parasitic RLC to be introduced into other surrounding first conductive bumps, and this RLC is inversely proportional to the distance; the farther the distance, the weaker the edge field radiation effect. Therefore, by setting the concave surfaces of adjacent first conductive bumps opposite each other, the overlap range of the edge field in space is reduced, thereby reducing the parasitic parameters caused by edge field radiation. Simultaneously, by setting the first conductive bump to include at least one concave surface, the volume of the first conductive bump is reduced, thereby reducing the parasitic capacitance of the first conductive bump itself.

[0070] In one embodiment, the first conductive structure 30 is arranged in a square pattern, and in each of the multiple first conductive structures 30 arranged in a square pattern, the concave surfaces 301 of the first conductive bumps 31 of the two first conductive structures 30 at the diagonal positions are arranged opposite each other.

[0071] In this embodiment, the concave surfaces of the first conductive bumps at the diagonal positions are arranged opposite each other. This increases the distance between the first conductive bumps, thereby reducing the edge field between the first conductive bumps and thus reducing the RLC parasitic parameters.

[0072] In some implementations, such as Figure 3As shown, the first conductive structures 30 are arranged in a square, that is, the four conductive structures form a rectangle. In some other embodiments, the four first conductive structures may also be formed into a rhombus or trapezoidal shape.

[0073] In one embodiment, see Figure 3 The first conductive bump 31 further includes at least one convex surface 302, which is disposed adjacent to the concave surface 301. By providing the convex surface, it is easier to subsequently weld the first conductive structure, ensuring the welding quality of the first conductive bump 31.

[0074] Figure 4 This is an enlarged view of the convex surface of the first conductive bump, as shown below. Figure 4 As shown, the convex surface 302 has an outward convex shape.

[0075] like Figure 3 As shown, in each of the multiple first conductive structures 30 arranged in a square, the first conductive bump 31 of each first conductive structure 30 includes multiple concave surfaces 301, and a convex surface 302 is provided between two adjacent concave surfaces 301. The area of ​​the concave surface 301 is larger than the area of ​​the convex surface 302.

[0076] The concave surface is designed to increase the distance between the two first conductive bumps, thereby reducing the parasitic parameters of RLC. Therefore, the area of ​​the concave surface is set to be larger to facilitate the reduction of parasitic parameters. The convex surface is designed to facilitate welding and ensure welding quality. Since the area of ​​the convex surface does not need to be set too large, it is only necessary to facilitate welding.

[0077] In some embodiments, such as Figure 5a As shown, the first conductive bump 31 includes a concave surface 301, which is positioned opposite to the center position of each of the four square-shaped bumps. In this embodiment, each first conductive bump has only one concave surface, but this concave surface is positioned opposite to the concave surface of each first conductive bump. Therefore, parasitic parameters can be reduced to a certain extent, and process steps can be reduced, thus lowering manufacturing costs.

[0078] In other embodiments, such as Figure 5b As shown, the first conductive bump 31 includes two concave surfaces 301, and the concave surfaces 301 of two adjacent first conductive bumps 31 are arranged opposite to each other. In this embodiment, two concave surfaces are provided, which can further reduce parasitic parameters. At the same time, because only two concave surfaces are provided, the area of ​​the convex surface is relatively large, which increases the welding area and ensures the welding quality.

[0079] In other embodiments, such as Figure 3 As shown, each first conductive structure 30 has a first conductive bump 31 including a plurality of concave surfaces 301.

[0080] In one embodiment, such as Figure 3 As shown, the distance from the intersection of the diagonals of each square arrangement to the concave surface 301 of each of the first conductive bumps 31 is the first distance h1, and the distance from the concave surface 301 of the first conductive bump 31 to the center of the first conductive bump 31 is the second distance h2. The ratio of the first distance h1 to the second distance h2 is 5:3 to 5:2.

[0081] If the ratio of the first distance to the second distance is set too large, it means that the concave surface of the first conductive bump is too close to the center of the first conductive bump, which will result in an excessively small area of ​​the first conductive bump, affecting its conductivity. Conversely, if the ratio of the first distance to the second distance is set too small, it means that the concave surface of the first conductive bump is close to the intersection of the diagonals, which reduces the distance between adjacent first conductive bumps and increases parasitic parameters. Therefore, setting the ratio of the first distance to the second distance to 5:3 to 5:2 ensures the conductivity of the first conductive bump while reducing parasitic parameters.

[0082] In one embodiment, such as Figure 2 As shown, the first conductive structure 30 further includes a first through-silicon via 32 and a first test pad 33. The first through-silicon via 32 is located on the first conductive bump 31, and the first test pad 33 is located between the first through-silicon via 32 and the first conductive bump 31.

[0083] The first through-silicon via and the first conductive bump ensure electrical connection between the subsequent substrate and the chip stack, and the first test pad can be used to test functionality.

[0084] The conductive material inside the first through-silicon via 32 includes, but is not limited to, Cu, and the conductive material is wrapped with an insulating material, including, but not limited to, SiO2. The material of the first test pad 33 includes, but is not limited to, Al.

[0085] In one embodiment, such as Figure 3 As shown, the first conductive bump 31 includes a first pad 311 and a first solder ball 312, with the first pad 311 located on the first solder ball 312; wherein, the orthographic projection of the first pad 311 on the substrate is located inside the orthographic projection of the first solder ball 312 on the substrate.

[0086] like Figure 2 As shown, the first pad 311 includes a first sub-pad 311a and a second sub-pad 311b, with the first sub-pad 311a located on the second sub-pad 311b; wherein the volume of the first sub-pad 311a is smaller than the volume of the second sub-pad 311b.

[0087] In some embodiments, when forming the first sub-pad 311a and the second sub-pad 311b, an insulating layer is first applied to the first test pad, covering the first test pad. Then, the insulating layer is exposed to form an opening on the first test pad. That is, the depth of the opening is equal to the thickness of the insulating layer on the first test pad, meaning the width of the opening can be less than the width of the first test pad. This results in a smaller volume for the first sub-pad 311a and a larger volume for the second sub-pad 311b. If a larger opening width is desired during exposure, for example, if the opening width is greater than the width of the first test pad, the opening depth increases, which will be affected by diffuse reflection during exposure, leading to abnormal exposure patterns. This results in a smaller first sub-pad 311a and a larger first sub-pad 311b. It should be noted that the first sub-pad 311a and the second sub-pad 311b can be formed simultaneously.

[0088] In some embodiments, when the first conductive bump 31 is octagonal, eight concave surfaces can also be provided on the first conductive bump 31, thereby reducing the parasitic parameters generated by the first conductive bump 31.

[0089] Table 1 shows the simulation data of each square-arranged first conductive structure in the prior art, and Table 2 shows the simulation data of each square-arranged first conductive structure in the embodiments of this disclosure. It should be explained that in the prior art, the shape of the first conductive bump of the first conductive structure is as follows: Figure 1 The circle shown.

[0090] Table 1

[0091]

[0092]

[0093] Table 2

[0094] First conductive structure 1 137.28 35.2 48.12 First conductive structure 2 137.27 35.2 48.12 First conductive structure 3 137.26 35.2 48.11 First conductive structure 4 137.24 35.2 48.15

[0095] A comparison of Tables 1 and 2 shows that the parasitic resistance R, parasitic inductance L, and parasitic capacitance C of the first conductive structure in this embodiment are reduced by 11.52%, 2.28%, and 7.96%, respectively. Therefore, the first conductive structure provided in this embodiment can reduce parasitic parameters and improve device performance.

[0096] In one embodiment, such as Figure 6a and Figure 6b As shown, the semiconductor structure further includes: a second conductive structure 40, which is located at the intersection of the diagonals of each of the four-sided arrangement; the second conductive structure 40 includes a second conductive bump 41, which includes at least one concave surface.

[0097] A second conductive structure 40 is added in the middle of the first conductive structure 30 arranged in a square. The first conductive structure 30 is a signal conductive structure, that is, the first conductive structure 30 transmits high-voltage signals, and the second conductive structure 40 is a ground conductive structure, that is, the second conductive structure 40 transmits low-voltage signals. Since the signal will choose the nearest ground or power source as the return path during the transmission process, and the second conductive structure is closer to the first conductive structure, the capacity of the electromagnetic flow to the ground conductive structure, that is, the second conductive structure, increases, and the capacity flowing to the first conductive structure will be relatively reduced. This can effectively reduce the edge field effect and thus reduce the RLC parasitic parameters in the return path segment.

[0098] In one embodiment, each concave surface of the second conductive bump 41 is disposed opposite to one concave surface of the adjacent first conductive bump 31. The opposing concave surfaces of the second and first conductive bumps increase the distance between them, thereby reducing crosstalk.

[0099] Table 3 shows the simulation data for each of the four-sided arrangement of the first conductive structure after the addition of the second conductive structure.

[0100] Table 3

[0101] First conductive structure 1 136.91 35.02 38.76 First conductive structure 2 136.86 35.01 38.75 First conductive structure 3 136.86 35.00 38.70 First conductive structure 4 136.85 35.00 38.71

[0102] A comparison of Tables 2 and 3 shows that the parasitic resistance R, parasitic inductance L, and parasitic capacitance C of the first conductive structure decreased by 0.3%, 0.57%, and 19.61%, respectively, after the addition of the second conductive structure. This demonstrates that adding the second conductive structure can reduce parasitic parameters, especially parasitic capacitance, thereby improving device performance.

[0103] In one embodiment, such as Figure 7 As shown, the first conductive structure can be used in a multi-chip stacked structure to electrically connect adjacent chips and improve the connection method to further reduce RLC parasitic parameters.

[0104] Specifically, such as Figure 7 As shown, the semiconductor structure includes: a substrate 10; and a chip stack 20 disposed on the substrate 10 through a plurality of first conductive structures 30.

[0105] In one embodiment, the substrate 10 may be a printed circuit board (PCB), a redistributed substrate, or a logic chip.

[0106] The substrate may include a base (not shown) and an upper insulating dielectric layer and a lower insulating dielectric layer (not shown) located on the upper and lower surfaces of the base, respectively.

[0107] The substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0108] The upper insulating dielectric layer and the lower insulating dielectric layer can be solder resist layers, for example, the materials of the upper insulating dielectric layer and the lower insulating dielectric layer can be green paint.

[0109] In one embodiment, adjacent chip layers 21 can also be connected via a first conductive bump 31 and a first through-silicon via 32. Then, for... Figure 7 The connection method between adjacent chips in the chip stack shown will be further described.

[0110] In one embodiment, such as Figure 7 and Figure 8 As shown, the chip stack 20 includes a plurality of chips 21 stacked sequentially, and each chip 21 includes n first conductive structures 30, where n is greater than or equal to 2.

[0111] In the projection along the plane direction perpendicular to the substrate 10, the projections of the first through-silicon vias 32 of the corresponding first conductive structures 30 in two adjacent chip layers 21 do not overlap.

[0112] In this embodiment, the projections of the first through-silicon vias (TSVs) of corresponding first conductive structures within adjacent chip layers do not overlap, indicating that the corresponding TSVs within adjacent chip layers are offset at a certain angle. This allows the same signal to rotate and rise within the structure formed by stacked chips, reducing crosstalk between different signals. Simultaneously, the optimized spatial structure enables the formation of a higher bandwidth memory.

[0113] In one embodiment, such as Figure 8 As shown, the semiconductor structure further includes a first interconnect 71, through which corresponding first conductive structures 30 in adjacent layers of the chip 21 are connected. By forming the first interconnect 71 in the chip, the connection of the first conductive structures 30 when spirally arranged is achieved, thereby ensuring normal signal transmission.

[0114] Specifically, such as Figure 8As shown, each chip layer may include multiple first conductive structures 30, namely CH0, CH1, CH2, and CH3. The corresponding CH0 within each chip layer is connected via a first interconnect 71 and rotates upwards at a certain angle. Similarly, CH1, CH2, and CH3 are also connected via first interconnect 71 and rotate upwards at a certain angle. The first interconnects connecting corresponding first conductive structures within the same layer are deflected at a certain angle, thus reducing the area of ​​the first interconnects facing each other and consequently reducing crosstalk between the first interconnects.

[0115] In one embodiment, one end of the first interconnect is connected to the first through-silicon via, and the other end of the first interconnect is connected to the first conductive bump.

[0116] The first interconnect is a metal wire, such as Figure 8 As shown, it includes metal wires M0 to M4.

[0117] like Figure 8 As shown, one end of the first interconnect 71 is M0, which is connected to the first through-silicon via (TSV) or the first conductive bump of the first conductive structure within one of the chip layers. The other end, M4, is connected to the first conductive bump or the first TSV of the corresponding first conductive structure within an adjacent chip. That is, if one end is connected to the first TSV, the other end is connected to the first conductive bump, and vice versa. M0 and M4 are connected by M1, M2, and M3.

[0118] It needs to be explained that, Figure 8 The end face of CH0 in the lower-level chip connected by M0 and the end face of CH0 in the upper-level chip connected by M4 should be on the same horizontal plane, that is, the first interconnect line should be parallel to the plane of the chip. Specifically, see [link to relevant documentation]. Figure 7 The signal is transmitted in the direction of the arrow, from the first conductive structure in one layer of the chip to the corresponding first conductive structure in the adjacent layer of the chip, wherein the first interconnect is located at the position indicated by the arrow parallel to the plane of the chip.

[0119] like Figure 8As shown, the first conductive structures 30 (e.g., CH0 and CH1) within the semiconductor structure are arranged spirally in the stacking direction, rather than vertically. This means that the distance between the same first conductive structure 30 (e.g., CH0) in adjacent chip layers increases. If the first conductive structures 30 (e.g., CH0 and CH1) within the semiconductor structure were arranged vertically, all first conductive structures 30 within the chip would generate signal crosstalk due to edge field effects. Furthermore, because the first conductive structures 30 are vertically arranged, the same first conductive structures 30 in adjacent chips are closer together, leading to a superposition of crosstalk effects. Moreover, the longer the signal formed by the first conductive structure 30, the stronger the superposition of crosstalk effects, ultimately causing signal distortion in the top-layer chip.

[0120] In this embodiment, since the first conductive structures 30 (e.g., CH0 and CH1) are spirally arranged, the distance between the same first conductive structure 30 (e.g., CH0) in two adjacent chip layers will increase. As a result, when two different signals crosstalk within the same chip, the crosstalk effect will not be superimposed on the other chip, thereby improving the impact of crosstalk on the signal.

[0121] like Figure 8 As shown, the first conductive structure 30 can be a through-silicon via (TSV) structure. CH0 and CH1 can represent different TSVs, that is, TSVs that transmit different signals.

[0122] This disclosure also provides a method for fabricating a semiconductor structure; please refer to the appendix for details. Figure 9 As shown in the figure, the method includes the following steps:

[0123] Step 901: Provide a substrate;

[0124] Step 902: Form a chip stack, and form a plurality of first conductive structures on the chip stack; the chip stack is disposed on the substrate through the first conductive structures; wherein, the first conductive structure includes a first conductive bump, the first conductive bump includes at least one concave surface, and the concave surfaces on adjacent first conductive bumps are disposed opposite to each other.

[0125] The method for preparing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0126] Figures 10a to 10h This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process.

[0127] See first Figure 10a Step 901 is executed, providing substrate 10.

[0128] In one embodiment, the substrate 10 may be a printed circuit board (PCB), a redistributed substrate, or a logic chip.

[0129] The substrate may include a base (not shown) and an upper insulating dielectric layer and a lower insulating dielectric layer (not shown) located on the upper and lower surfaces of the base, respectively.

[0130] The substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0131] The upper insulating dielectric layer and the lower insulating dielectric layer can be solder resist layers, for example, the materials of the upper insulating dielectric layer and the lower insulating dielectric layer can be green paint.

[0132] Next, see Figures 10b to 10e Step 902 is executed to form a chip stack 20, and a plurality of first conductive structures 30 are formed on the chip stack 20. The chip stack 20 is disposed on the substrate 10 through the first conductive structures 30. The first conductive structure 30 includes a first conductive bump 31, and the first conductive bump 31 includes at least one concave surface 301. The concave surfaces 301 on adjacent first conductive bumps 31 are disposed opposite to each other.

[0133] See first Figure 10b A chip stack 20 is formed on the substrate 10, the chip stack 20 comprising a plurality of chips 21 stacked sequentially.

[0134] Next, see Figures 10c to 10e The preparation process of the first conductive structure is explained in detail.

[0135] The formation of the first conductive structure 30 includes:

[0136] An initial first conductive structure 300 is formed, the initial first conductive structure 300 includes an initial first conductive bump 310, the initial first conductive bump 310 being circular in shape;

[0137] At least one first mask layer 61 is formed on each of the initial first conductive bumps 310, and the first mask layer 61 covers a portion of the periphery of the initial first conductive bump 310;

[0138] The portion of the initial first conductive bump 310 covered by the first mask layer 61 is etched away to form the first conductive structure 30.

[0139] In one embodiment, the first mask layer 61 is circular in shape, such that the first conductive bump formed after the initial first conductive bump 310 is partially removed includes at least one concave surface.

[0140] It is understandable that the first mask layer may also be other arc-shaped structures.

[0141] In one embodiment, the first conductive structure 30 is arranged in a square pattern, and in each of the multiple first conductive structures 30 arranged in a square pattern, the concave surfaces 301 of the first conductive bumps 31 of the two first conductive structures 30 at the diagonal positions are arranged opposite each other.

[0142] In this embodiment, the concave surfaces of the first conductive bumps at the diagonal positions are arranged opposite each other. This increases the distance between the first conductive bumps, thereby reducing the edge field between the first conductive bumps and thus reducing the RLC parasitic parameters.

[0143] In some implementations, such as Figure 10e As shown, the first conductive structures 30 are arranged in a square, that is, the four conductive structures form a rectangle. In some other embodiments, the four first conductive structures may also be formed into a rhombus or trapezoidal shape.

[0144] In one embodiment, see Figure 10e The first conductive bump 31 further includes at least one convex surface 302, which is disposed adjacent to the concave surface 301. By providing the convex surface, it is easier to subsequently weld the first conductive structure, ensuring the welding quality of the first conductive bump 31.

[0145] like Figure 10e As shown, in each of the multiple first conductive structures 30 arranged in a square, the first conductive bump 31 of each first conductive structure 30 includes multiple concave surfaces 301, and a convex surface 302 is provided between two adjacent concave surfaces 301. The area of ​​the concave surface 301 is larger than the area of ​​the convex surface 302.

[0146] The concave surface is designed to increase the distance between the two first conductive bumps, thereby reducing the parasitic parameters of RLC. Therefore, the area of ​​the concave surface is set to be larger to facilitate the reduction of parasitic parameters. The convex surface is designed to facilitate soldering, since there is no need to set the area of ​​the convex surface too large; it is only necessary to facilitate soldering.

[0147] In one embodiment, such as Figure 10eAs shown, the distance from the intersection of the diagonals of each square arrangement to the concave surface 301 of each of the first conductive bumps 31 is the first distance h1, and the distance from the concave surface 301 of the first conductive bump 31 to the center of the first conductive bump 31 is the second distance h2. The ratio of the first distance h1 to the second distance h2 is 5:3 to 5:2.

[0148] If the ratio of the first distance to the second distance is set too large, it means that the concave surface of the first conductive bump is too close to the center of the first conductive bump, which will result in an excessively small area of ​​the first conductive bump, affecting its conductivity. Conversely, if the ratio of the first distance to the second distance is set too small, it means that the concave surface of the first conductive bump is close to the intersection of the diagonals, which reduces the distance between adjacent first conductive bumps and increases parasitic parameters. Therefore, setting the ratio of the first distance to the second distance to 5:3 to 5:2 ensures the conductivity of the first conductive bump while reducing parasitic parameters.

[0149] In one embodiment, such as Figure 2 As shown, the first conductive structure 30 further includes a first through-silicon via 32 and a first test pad 33. The first through-silicon via 32 is located on the first conductive bump 31, and the first test pad 33 is located between the first through-silicon via 32 and the first conductive bump 31.

[0150] The first through-silicon via and the first conductive bump ensure electrical connection between the subsequent substrate and the chip stack, and the first test pad can be used to test functionality.

[0151] The conductive material inside the first through-silicon via 32 includes, but is not limited to, Cu, and the conductive material is wrapped with an insulating material, including, but not limited to, SiO2. The material of the first test pad 33 includes, but is not limited to, Al.

[0152] In one embodiment, such as Figure 10e As shown, the first conductive bump 31 includes a first pad 311 and a first solder ball 312, with the first pad 311 located on the first solder ball 312; wherein, the orthographic projection of the first pad 311 on the substrate 10 is located inside the orthographic projection of the first solder ball 312 on the substrate 10.

[0153] like Figure 2 As shown, the first pad 311 includes a first sub-pad 311a and a second sub-pad 311b, with the first sub-pad 311a located on the second sub-pad 311b; wherein the volume of the first sub-pad 311a is smaller than the volume of the second sub-pad 311b.

[0154] The first sub-pad is connected to the first test pad. Therefore, the first sub-pad is smaller in size, which can reduce the contact area with the first test pad and thus reduce the contact resistance.

[0155] Next, see Figures 10f to 10h The method further includes forming a second conductive structure 40 at the intersection of each diagonal of the four-sided arrangement, the second conductive structure 40 including a second conductive bump 41, the second conductive bump 41 including at least one concave surface.

[0156] In one embodiment, forming the second conductive structure 40 includes:

[0157] An initial second conductive structure 400 is formed at the intersection of each of the four diagonal lines arranged in a square; the initial second conductive structure 400 includes an initial second conductive bump 410, which is circular in shape.

[0158] A second mask layer 62 is formed at the middle position of the initial second conductive bump 410, the second mask layer 62 including at least one concave surface;

[0159] The portion of the initial second conductive bump 410 not covered by the second mask layer 62 is etched away to form the second conductive structure 40.

[0160] A second conductive structure 40 is added in the middle of the first conductive structure 30 arranged in a square. The first conductive structure 30 is a signal conductive structure, that is, the first conductive structure 30 transmits high-voltage signals, and the second conductive structure 40 is a ground conductive structure, that is, the second conductive structure 40 transmits low-voltage signals. Since the signal will choose the nearest ground or power source as the return path during the transmission process, and the second conductive structure is closer to the first conductive structure, the capacity of the electromagnetic flow to the ground conductive structure, that is, the second conductive structure, increases, and the capacity flowing to the first conductive structure will be relatively reduced. This can effectively reduce the edge field effect and thus reduce the RLC parasitic parameters in the return path segment.

[0161] In one embodiment, each concave surface of the second conductive bump 41 is disposed opposite to one concave surface of the adjacent first conductive bump 31. The opposing concave surfaces of the second and first conductive bumps increase the distance between them, thereby reducing crosstalk.

[0162] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: substrate; A chip stack is disposed on the substrate through multiple first conductive structures; Wherein, the first conductive structure includes a first conductive bump, the first conductive bump includes at least one concave surface, and the concave surfaces on adjacent first conductive bumps are arranged opposite to each other; the first conductive structures are arranged in a square, and in each square arrangement of multiple first conductive structures, the concave surfaces of the first conductive bumps of the two first conductive structures at the diagonal position are arranged opposite to each other.

2. The semiconductor structure according to claim 1, characterized in that, The distance from the intersection of the diagonals of each of the four square arrangements to the concave surface of each of the first conductive bumps is the first distance, and the distance from the concave surface of the first conductive bump to the center of the first conductive bump is the second distance. The ratio of the first distance to the second distance is 5:3 to 5:

2.

3. The semiconductor structure according to claim 2, characterized in that, The first conductive bump further includes at least one convex surface, which is disposed adjacent to the concave surface.

4. The semiconductor structure according to claim 3, characterized in that, In each of the multiple first conductive structures arranged in a square, the first conductive bump of each first conductive structure includes multiple concave surfaces, and a convex surface is provided between two adjacent concave surfaces, wherein the area of ​​the concave surface is larger than the area of ​​the convex surface.

5. The semiconductor structure according to claim 1, characterized in that, The first conductive structure further includes a first through-silicon via (TSV) and a first test pad, wherein the TSV is located on the first conductive bump and the first test pad is located between the TSV and the first conductive bump.

6. The semiconductor structure according to claim 1, characterized in that, The first conductive bump includes a first pad and a first solder ball, with the first pad located on the first solder ball; Wherein, the orthographic projection of the first pad on the substrate is located inside the orthographic projection of the first solder ball on the substrate.

7. The semiconductor structure according to claim 6, characterized in that, The first pad includes a first sub-pad and a second sub-pad, with the first sub-pad located on the second sub-pad; The volume of the first sub-pad is smaller than the volume of the second sub-pad.

8. The semiconductor structure according to claim 5, characterized in that, The chip stack comprises multiple chips stacked sequentially, each chip containing n first conductive structures, where n is greater than or equal to 2; In a projection along a plane perpendicular to the substrate, the projections of the first through-silicon vias of the corresponding first conductive structures in two adjacent chip layers do not overlap.

9. The semiconductor structure according to claim 2, characterized in that, Also includes: The second conductive structure is located at the intersection of the diagonals of each square arrangement; The second conductive structure includes a second conductive bump, and the second conductive bump includes at least one concave surface.

10. The semiconductor structure according to claim 9, characterized in that, Each concave surface of the second conductive bump is disposed opposite to one of the concave surfaces of the first conductive bump adjacent to it.

11. The semiconductor structure according to claim 9, characterized in that, The first conductive structure is a signal conductive structure, and the second conductive structure is a ground conductive structure.

12. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A chip stack is formed, and a plurality of first conductive structures are formed on the chip stack. The chip stack is disposed on the substrate through the first conductive structure; Wherein, the first conductive structure includes a first conductive bump, the first conductive bump includes at least one concave surface, and the concave surfaces on adjacent first conductive bumps are arranged opposite to each other; the first conductive structures are arranged in a square, and in each square arrangement of multiple first conductive structures, the concave surfaces of the first conductive bumps of the two first conductive structures at the diagonal position are arranged opposite to each other.

13. The method according to claim 12, characterized in that, The formation of the first conductive structure includes: An initial first conductive structure is formed, the initial first conductive structure including an initial first conductive bump, the initial first conductive bump being circular in shape; At least one first mask layer is formed on each of the initial first conductive bumps, the first mask layer covering a portion of the periphery of the initial first conductive bump; The portion of the initial first conductive bump covered by the first mask layer is etched away to form the first conductive structure.

14. The method according to claim 12, characterized in that, Also includes: A second conductive structure is formed at the intersection of each of the four diagonal lines arranged in a square. The second conductive structure includes a second conductive bump, and the second conductive bump includes at least one concave surface.

15. The method according to claim 14, characterized in that, The formation of the second conductive structure includes: An initial second conductive structure is formed at the intersection of each of the four diagonal lines arranged in a square; the initial second conductive structure includes an initial second conductive bump, and the initial second conductive bump is circular in shape; A second mask layer is formed at the middle position of the initial second conductive bump, the second mask layer including at least one concave surface; The portion of the initial second conductive bump not covered by the second mask layer is etched away to form the second conductive structure.

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