Semiconductor structure and layout structure

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a memory and a layout structure, the semiconductor structure comprising: a high-speed circuit module comprising a clock signal, the frequency of the clock signal being greater than a first threshold; a first conductive metal layer comprising a plurality of power supply wires extending along a first direction and arranged at intervals, and electrically connected to the high-speed circuit module; a redistribution layer located on the first conductive metal layer, the redistribution layer comprising: a plurality of power supply pads, and a conductive wire connected to the power supply pads; wherein the power supply pads are located on one side of the high-speed circuit module, and the projection area of the power supply pads does not overlap with the high-speed circuit module; the conductive wire comprises a first wire area formed by repeated bending, the first wire area at least partially covers the high-speed circuit module, and the conductive wire is used for electrically connecting the power supply wires and the power supply pads.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and layout structure. Background Technology

[0002] LPDDR (Low Power Double Data Rate Synchronous Dynamic Random-Access Memory) is a type of dynamic random access memory characterized by low power consumption and high speed. To meet its high-speed and low-power requirements, the design of the power supply and related circuitry is crucial.

[0003] In related technologies, when the power pad positions are fixed, it is a design challenge to use RDL (Redistribution Layer) to directly connect the power signal to the high-speed circuit of LPDDR and simultaneously power other modules of the memory, such as the memory cell array. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and layout structure.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0006] A high-speed circuit module includes a clock signal, the frequency of which is greater than a first threshold.

[0007] A first conductive metal layer, comprising a plurality of power wires extending along a first direction and spaced apart, electrically connected to the high-speed circuit module;

[0008] A redistribution layer, located on the first conductive metal layer, includes: a plurality of power pads and conductive lines connected to the power pads; wherein the power pads are located on one side of the high-speed circuit module, and the projected area of ​​the power pads does not overlap with the high-speed circuit module; the conductive lines include a first conductor area formed by repeated bending, the first conductor area at least partially covering the high-speed circuit module, and the conductive lines are used to electrically connect the power conductors and the power pads.

[0009] In some embodiments, the plurality of power pads are used to provide different power supply voltages;

[0010] Each power conductor includes multiple power lines, each power line being used to connect to different power pads; wherein, each power line is electrically connected to the conductive line of the corresponding power source through multiple connection holes.

[0011] In some embodiments, the conductive lines connected to the plurality of power pads with different power supply voltages are distributed at equal intervals in the first conductor region.

[0012] In some embodiments, the plurality of power pads with different power supply voltages include at least: a first power pad, a second power pad, and a third power pad arranged sequentially along a first direction; the first direction is the extension direction of the power conductor;

[0013] The conductive line connected to the first power pad is the first conductive line;

[0014] The conductive line connected to the second power pad is the second conductive line;

[0015] The conductive line connected to the third power pad is the third conductive line.

[0016] In some embodiments, the second conductive wire is bent within the first conductor region to form: a plurality of alternating first recessed regions and second recessed regions extending along a first direction;

[0017] Wherein, the notch in the first recessed region faces the opposite direction to the notch in the second recessed region;

[0018] The first conductive line includes a plurality of first branches extending into the first recessed region along the first direction; the third conductive line includes a plurality of second branches extending into the second recessed region along the first direction.

[0019] In some embodiments, it also includes:

[0020] The storage cell array area is located on the side of the high-speed circuit module away from the power pad; the storage cell array area includes multiple storage cell arrays; the power pad and the storage cell array are connected through conductive lines of the redistribution layer.

[0021] In some embodiments, the conductive lines of the redistribution layer further include a second conductive area for connecting the memory cell array; wherein the conductive lines of the second conductive area do not overlap with the projection area of ​​the high-speed circuit module; and the conductive lines of the first conductive area and the second conductive area are interconnected.

[0022] In some embodiments, the semiconductor structure includes a first region and a second region arranged in parallel;

[0023] The redistribution layer of the first region and the redistribution layer of the second region each include a plurality of power pads; wherein, the power pads of the first region are connected to the memory cell array of the first region through the conductive lines of the first region; and the power pads of the second region are connected to the memory cell array of the second region through the conductive lines of the second region.

[0024] In some embodiments, at least one power pad in the first region is supplied with the same power voltage as at least one power pad in the second region.

[0025] In some embodiments, the difference in resistance values ​​of the conductive lines connected to the power pads in the first and second regions for providing the same power supply voltage is less than a preset threshold.

[0026] In some embodiments, the resistance values ​​of the conductive lines connected to the power pads in the first and second regions for providing the same power supply voltage are the same.

[0027] In some embodiments, the first conductor region of the conductive line connected to the power pad in the first region and the first conductor region of the conductive line connected to the power pad in the second region are axially symmetrically distributed.

[0028] Secondly, embodiments of this disclosure also provide a layout structure, including:

[0029] The high-speed circuit module layout includes at least a clock signal containing a frequency greater than a first threshold.

[0030] The first conductive metal layer layout includes multiple power wire patterns extending along a first direction, used to represent the layout of the high-speed circuit module electrically connected to the circuit.

[0031] A redistribution layer layout is located on the first conductive metal layer layout. The redistribution layer layout includes: multiple power pad patterns and conductive line patterns connected to the power pad patterns; wherein, the power pad patterns are located on one side of the high-speed circuit module layout, and the projected area of ​​the power pad patterns does not overlap with the high-speed circuit module layout; the conductive line patterns include a first conductor area formed by repeated bending, the first conductor area at least partially covering the high-speed circuit module layout, and the conductive line patterns connect the power conductor patterns and the power pad patterns.

[0032] In some embodiments, the plurality of power pad patterns include at least: a first power pad pattern, a second power pad pattern, and a third power pad pattern arranged sequentially along a first direction; the first direction is the extension direction of the power conductor pattern;

[0033] The conductive line pattern connected to the first power pad pattern is the first conductive line pattern.

[0034] The conductive line pattern connected to the second power pad pattern is the second conductive line pattern;

[0035] The conductive line pattern connected to the third power pad pattern is the third conductive line pattern.

[0036] In some embodiments, the second conductive line pattern is bent within the first conductive area to form: a plurality of alternating first recessed regions and second recessed regions extending along a first direction;

[0037] Wherein, the notch in the first recessed region faces the opposite direction to the notch in the second recessed region;

[0038] The first conductive line pattern includes multiple first branch lines extending into the first recessed region along the first direction; the third conductive line pattern includes multiple second branch lines extending into the second recessed region along the first direction.

[0039] In some embodiments, the layout structure further includes:

[0040] The memory cell array area layout is located on the side of the high-speed circuit module layout away from the power pad pattern; the memory cell array area layout includes multiple memory cell array patterns; the power pad pattern and the memory cell array pattern are connected through the conductive line pattern of the redistribution layer layout.

[0041] In the technical solution of this embodiment, multiple power pads are located on a redistribution layer and connected to a first conductive metal layer via conductive lines on the redistribution layer having a first conductive area formed by repeated bending, and electrically connected to a high-speed circuit module. This effectively increases the contact area between the conductive lines and the high-speed circuit module, allowing the power supply to directly power the high-speed circuit and facilitating power reduction. Simultaneously, the conductive lines in the redistribution layer can also extend and connect to other circuit modules without affecting the power supply to the high-speed circuit. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0043] Figure 2 This is a schematic diagram of a partial cross-section of a semiconductor structure according to an embodiment of the present disclosure;

[0044] Figure 3 This is a schematic diagram of power supply wires arranged at intervals in a semiconductor structure according to an embodiment of the present disclosure;

[0045] Figure 4 This is a schematic diagram of multiple power lines included in a power conductor in a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 5 This is a schematic diagram of the distribution of conductive lines in a semiconductor structure according to an embodiment of the present disclosure;

[0047] Figure 6This is a schematic diagram of a semiconductor structure including a memory cell array according to an embodiment of the present disclosure;

[0048] Figure 7 This is a schematic diagram of a semiconductor structure comprising different partitions according to an embodiment of the present disclosure;

[0049] Figure 8 This is a schematic diagram of a layout structure according to an embodiment of the present disclosure. Detailed Implementation

[0050] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, some technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described in detail.

[0052] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0053] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0055] like Figure 1 As shown, this disclosure provides a semiconductor structure 100, including:

[0056] High-speed circuit module 110 includes a clock signal, the frequency of which is greater than a first threshold.

[0057] The first conductive metal layer 120 includes a plurality of power wires 121 extending along a first direction and arranged at intervals, which are electrically connected to the high-speed circuit module 110.

[0058] A redistribution layer 130 is located on the first conductive metal layer 120. The redistribution layer 130 includes a plurality of power pads 131 and conductive lines 132 connected to the power pads 131. The power pads 131 are located on one side of the high-speed circuit module 110, and the projected area of ​​the power pads 131 does not overlap with the high-speed circuit module 110. The conductive lines 132 include a first conductor region 132a formed by repeated bending. The first conductor region 132a at least partially covers the high-speed circuit module 110. The conductive lines 132 are used to electrically connect the power conductors 121 and the power pads 131.

[0059] The semiconductor structures disclosed in this embodiment can be applied to memory, including but not limited to DRAM, Static Random Access Memory (SRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Nano Random Access Memory (NRAM). In particular, they can be applied to LPDDR memory.

[0060] DDR is a common type of memory module, while LPDDR is a type of memory module with low power consumption characteristics, which can be used in products such as smartphones and smartwatches that are sensitive to power consumption and size.

[0061] Furthermore, LPDDR5 is characterized by its high speed, employing a high-speed circuit design in its digital logic circuitry to enhance data processing rates. Generally, high-speed circuits can also be referred to as high-frequency circuits, operating based on the rapidly changing clock signal edges to perform digital circuit operations. When the data transmission rate of the digital logic circuit exceeds a first threshold (e.g., 4800 megabits per second (Mbps)), the circuit can be considered a high-speed circuit. Here, the high-speed circuit module 110 broadly refers to any logic circuit module with high-speed characteristics within the memory used in the semiconductor structure 100 of this embodiment.

[0062] The first conductive metal layer 120 includes at least power lines 121 for providing power signals to the high-speed circuit module 110. These power lines 121 may be part of the high-speed circuit module 110, meaning the high-speed circuit module 110 may include some power lines located on the first conductive metal layer 120. Additionally, the high-speed circuit module 110 may also include devices and circuit modules located in other metal layers or structural layers of the semiconductor structure. For example, the first conductive metal layer 120 may be the top metal layer M4 in a memory structure.

[0063] In this embodiment, the power supply wire 121 in the first conductive metal layer 120 may include multiple wires extending along a first direction, each of which can be used to provide power signals to different locations of the high-speed circuit module 110. Here, the first direction may be as follows: Figure 1 The X direction is shown.

[0064] In this embodiment of the disclosure, the redistribution layer 130 is located on the first conductive metal layer 120, meaning that on such a redistribution layer 130 is located on the first conductive metal layer 120. Figure 1 In the Z direction shown, the redistribution layer 130 is another metal layer covering the first conductive metal layer 120. For example... Figure 2 As shown, an insulating material layer 124, such as an oxide or an organic compound like TEOS (tetraethoxysilane) as shown, may be covered on the first conductive metal layer 120. The redistribution layer 130 covers the insulating material layer and is connected to the first conductive metal layer 120 through vias 122 penetrating the insulating material layer. The redistribution layer 130 may include various signal pads, including power pads, data interface pads, ground pads, etc. Figure 2 As shown, another insulating material 125, such as PI (Polyimide), silicon nitride, and other oxide or organic compound materials, can be covered on the redistribution layer 130. The positions of various signal pads can be left exposed without being covered by the insulating material, allowing other signal terminals to connect.

[0065] The materials used for the first conductive metal layer 120 and the redistribution layer 130 can be aluminum, copper, or other conductive materials, such as titanium nitride (TiN).

[0066] In this embodiment of the disclosure, the conductive line 132 in the redistribution layer 130 has a first conductive region 132a formed by repeated bending. The first conductive region 132a is located on the power pad 131 as shown in the figure. Figure 1 The conductive line 132 extends from the power pad 131 to the first conductor area 132a and is repeatedly bent, resulting in more overlap between the conductive line 132 and the power conductor 121 above the first conductive metal layer 120. This allows for more vias between the first conductive metal layer 120 and the redistribution layer 130, increasing the contact area between the two conductor layers and reducing contact resistance. Since the power conductor 121 in the first conductive metal layer 120 can be directly used to supply power to high-speed circuits, the above design effectively reduces power consumption and ensures power supply to high-speed circuits.

[0067] like Figure 3 As shown, the multiple power conductors 121 can be arranged in parallel at intervals, thereby covering a larger area and providing power voltage to different nodes of the first conductive metal layer 120. In this way, different nodes can be connected to their corresponding metal wires nearby, eliminating the need for excessive jumpers.

[0068] Each power wire 121 can be connected to the aforementioned conductive wire 132 through a through hole ( Figure 3Electrical connections are made (not shown in the diagram), so each power supply wire 121 can include a power supply line that provides the same power signal.

[0069] In some embodiments, the plurality of power pads are used to provide different power supply voltages;

[0070] Each power conductor includes multiple power lines, each power line being used to connect to different power pads; wherein, each power line is electrically connected to the conductive line of the corresponding power source through multiple connection holes.

[0071] Each power conductor 121 may include multiple power lines, which may also be arranged in parallel at intervals, such as... Figure 4 As shown. Different power lines are used to connect different power supplies. The conductive lines 132 connected to different power supply pads can be connected to a power supply line by a through hole 122 at the position where the projection of the corresponding power line overlaps in the first conductor area 132a.

[0072] For example, such as Figure 4 As shown, the power supply wire 121 includes a first power supply line VDD2H, a second power supply line VSS, and a third power supply line VDD2L arranged at intervals.

[0073] It should be noted that, Figure 4 The arrangement of the three power lines is shown exemplarily only and is not intended to limit the power lines to straight lines, nor does it imply that the power lines must be parallel. In fact, each power line can have bends, and for example, several power lines can have interlocking patterns.

[0074] In addition, each power line may have multiple through holes 122 for connection with conductive lines 132. The through holes 122 on two adjacent power lines may be staggered, and the adjacent through holes 122 on the same power line may also be staggered, thereby reducing signal interference between the through holes and facilitating the improvement of structural stability during manufacturing.

[0075] In some embodiments, the conductive lines connected to the plurality of power pads with different power supply voltages are distributed at equal intervals in the first conductor region.

[0076] like Figure 1 As shown, multiple power pads for providing different power supply voltages are connected to their respective conductive lines, which are repeatedly bent within the first conductor region. Within the first conductor region, the conductive lines connected to different power pads must not cross, and the bending points can be regularly alternating. Within the first conductor region, different conductive lines can be evenly spaced, which facilitates connection to the first conductive metal layer 120 and reduces crosstalk between signals.

[0077] In some embodiments, such as Figure 5 As shown, the plurality of power pads with different power supply voltages include at least: a first power pad 501, a second power pad 502 and a third power pad 503 arranged sequentially along a first direction; the first direction is the extension direction of the power conductor 121;

[0078] The conductive line connected to the first power pad 501 is the first conductive line 511;

[0079] The conductive line connected to the second power pad 502 is the second conductive line 512;

[0080] The conductive line connected to the third power pad 503 is the third conductive line 513.

[0081] The first power pad 501 can be a pad VDD2H providing a first high power supply voltage, the second power pad 502 can be a pad VSS providing a low power supply voltage or grounding, and the third power pad 503 can be a pad VDD2L providing a second high power supply voltage. Here, VDD2H and VDD2L can be used to provide different power signals to the high-speed circuit module through the first conductive metal layer 120, so as to realize more flexible and complex circuit functions. The above design is only an exemplary embodiment. In practical applications, the power pads may also include other pads providing different power supply voltages, depending on the function and requirements of the high-speed circuit module.

[0082] In addition, the first power pad 501, the second power pad 502 and the third power pad 503 may each include one or more, that is, each power pad may not be limited to one, which facilitates the layout and routing design of the circuit.

[0083] In some embodiments, the second conductive wire 512 is bent within the first conductor region 132a to form a plurality of alternating first recessed regions s1 and second recessed regions s2 extending in a first direction.

[0084] Wherein, the notch of the first recessed region s1 faces the opposite direction to the notch of the second recessed region s2;

[0085] The first conductive line 511 includes a plurality of first branches 521 extending into the first recessed region s1 along the first direction; the third conductive line 513 includes a plurality of second branches 523 extending into the second recessed region s2 along the first direction.

[0086] like Figure 5As shown, the second power pad 502 is located between the first power pad 501 and the third power pad 503. The first conductive line 511, the second conductive line 512, and the third conductive line 513 connected to the first power pad 501, the second power pad 502, and the third power pad 503 extend from each power pad to the first conductor area 132a and are bent. In order to distribute the three conductive lines as evenly as possible, the second conductive line 512, located in the middle of the three conductive lines, can adopt a serpentine structure and extend in the first direction (X direction). The bent shape of the second conductive line 512 has multiple recessed areas on both sides of the second direction. The first conductive line 511 and the third conductive line 513 can each be provided with multiple finger-shaped branches extending into the opening. The first branch 521 of the first conductive line 511 can extend to the first recessed area s1 in one direction, and the second branch 523 of the third conductive line 513 can extend to the second recessed area s2 in the opposite direction to the first recessed area s1.

[0087] In this way, on the one hand, the contact area between the three conductive lines and the first conductive metal layer 120 can be increased by bending, and on the other hand, the voltage balance of the three power sources at each position can be maintained, thereby improving the stability of the circuit.

[0088] In some embodiments, such as Figure 6 As shown, the semiconductor structure 100 further includes:

[0089] The storage cell array area 610 is located on the side of the high-speed circuit module 110 away from the power pad 131; the storage cell array area 610 includes a plurality of storage cell arrays 611; the power pad 131 and the storage cell arrays 611 are connected through the conductive lines 132 of the redistribution layer 130.

[0090] In addition to supplying power to the high-speed circuit module 110 by connecting to the first conductive metal layer 120, the aforementioned power pad 131 can also be used to provide power signals to the memory cell array 611.

[0091] The conductive line 132 connected to each power pad 131 can extend to the memory cell array area 610 and connect to each memory cell array.

[0092] In some embodiments, the conductive lines 132 of the redistribution layer 130 further include a second conductor region 132b for connecting the memory cell array 611; wherein the conductive lines 132 of the second conductor region 132b do not overlap with the projection area of ​​the high-speed circuit module 110; the conductive lines 132 of the first conductor region 132a and the second conductor region 132b are interconnected.

[0093] After the aforementioned conductive line 132 extends to the first conductor region 132a and is repeatedly bent, at least one end can continue to extend to the memory cell array region 610. The conductive line in the second conductor region 132b can be straight or may have some bends to connect to the required location in the memory cell array 611.

[0094] In some embodiments, such as Figure 7 As shown, the semiconductor structure 100 includes a first region 710 and a second region 720 arranged in parallel;

[0095] The redistribution layer 130 of the first region 710 and the redistribution layer 130 of the second region 720 each include a plurality of power pads 131; wherein, the power pads 131 of the first region 710 are connected to the memory cell array 611 of the first region 710 through the conductive lines 132 of the first region 710; the power pads 131 of the second region 720 are connected to the memory cell array 611 of the second region through the conductive lines 132 of the second region 720.

[0096] In other embodiments, the semiconductor structure 100 may also include more partitions, each of which may have the same power pads and conductive lines, and be connected to different memory cell arrays, thereby facilitating the expansion of the number of memory cell arrays.

[0097] Since the first region 710 and the second region 720 are arranged side by side in the first direction, the power wire 121 extending in the first conductive metal layer 120 along the first direction can directly pass through the first region 710 and the second region 720 and be connected to the corresponding high-speed circuit module 110.

[0098] In some embodiments, at least one power pad 131 of the first region 710 is supplied with the same power voltage as at least one power pad 131 of the second region 720.

[0099] For example, the circuit structure, pads, and conductive lines in the first region 710 and the second region 720 described above can be the same. The circuit structure, pads, and conductive lines in the first region 710 and the second region 720 can also be different, but they can have some of the same power pads to provide the same power supply voltage. Figure 7 As shown, the first region 710 and the second region 720 respectively include a first power pad VDD2H, a second power pad VSS, and a third power pad VDD2L.

[0100] In some embodiments, the difference in resistance values ​​of the conductive lines connected to the power pads in the first and second regions for providing the same power supply voltage is less than a preset threshold.

[0101] Because the structures of the first and second regions may differ, the extension paths of the conductive lines from the same power pads to the corresponding memory cell arrays may also differ. That is, the power pads and conductive lines in the first and second regions are not perfectly symmetrical, which may lead to differences in the power supply voltage provided to different memory cell arrays.

[0102] Therefore, in this embodiment, it is necessary to ensure that the resistance values ​​of the power pads used to provide the same power supply voltage in the first and second regions, and the conductive lines between different memory cell arrays, have a small difference. Here, a threshold value can be preset according to actual needs, and the difference in resistance values ​​between the two conductive lines needs to be less than this preset threshold value.

[0103] Since the aforementioned conductive wire has a first conductor region with repeated bends, the total length of the conductive wire can be adjusted by designing the shape of the bends, thereby setting the corresponding resistance value so that the resistance values ​​of the two conductive wires are as equal as possible.

[0104] In some embodiments, the resistance values ​​of the conductive lines connected to the power pads in the first and second regions for providing the same power supply voltage are the same.

[0105] In some embodiments, the first conductor region of the conductive line connected to the power pad in the first region and the first conductor region of the conductive line connected to the power pad in the second region are axially symmetrically distributed.

[0106] In other words, the corresponding conductive lines in the first and second zones are axially symmetrically distributed within the first conductor zone and have the same total length and resistance value. If the distribution of power pads in the first zone is not symmetrical with that in the second zone, the consistency of the resistance value of the conductive lines on both sides can be achieved by adjusting the length and shape of the conductive lines in areas outside the first conductor zone. Figure 7 As shown, considering that the positions of the power pads in the first region 710 and the second region 720 are not perfectly symmetrical, the distances between the same power pads 131 in the first region 710 and the respective memory cell array regions 610 to be connected are different. Therefore, the length and shape of the conductive lines can be flexibly designed, for example, Figure 7 The extra extension of the conductive line connected to the power pad VDD2H in the second zone 720 (the position circled in the figure) is used to maintain the same resistance as the conductive line connected to the power pad VDD2H in the first zone 710. Similarly, the extra bend in the power pad VSS in the second zone 720 (the position circled in the figure) is also used to maintain the same resistance as the conductive line connected to the power pad VSS in the first zone 710.

[0107] This disclosure also provides a memory, including:

[0108] Semiconductor structures as described in any of the above embodiments.

[0109] The memory can be any type of memory, and its circuit structure and the distribution of the memory cell array can be designed as described above in the semiconductor structure.

[0110] like Figure 8 As shown, this disclosure also provides a layout structure 200, including:

[0111] The high-speed circuit module layout 210 includes at least a clock signal containing a frequency greater than a first threshold.

[0112] The first conductive metal layer layout 220 includes a plurality of power wire patterns 221 extending along a first direction, used to represent electrical connections to the high-speed circuit module layout 210.

[0113] A redistribution layer layout 230 is located on the first conductive metal layer layout 220. The redistribution layer layout 230 includes: a plurality of power pad patterns 231, and conductive line patterns 232 connected to the power pad patterns 231; wherein, the power pad patterns 231 are located on one side of the high-speed circuit module layout 210, and the projection area of ​​the power pad patterns 231 does not overlap with the high-speed circuit module layout 210; the conductive line pattern 232 includes a first conductor area 232a formed by repeated bending, the first conductor area 232a at least partially covers the high-speed circuit module layout 210, and the conductive line pattern 232 connects the power conductor pattern 221 and the power pad pattern 231.

[0114] In the above layout structure, the conductive line pattern 232 is repeatedly bent within the first conductor area 232a, which can have more overlapping areas with the first conductive metal layer layout 220, thereby facilitating the setting of more through-hole patterns 240 to represent the connection relationship between the conductive line pattern 232 and the power conductor pattern 221 in the first conductive metal layer layout 220.

[0115] In some embodiments, the plurality of power pad patterns include at least: a first power pad pattern, a second power pad pattern, and a third power pad pattern arranged sequentially along a first direction; the first direction is the extension direction of the power conductor pattern;

[0116] The conductive line pattern connected to the first power pad pattern is the first conductive line pattern.

[0117] The conductive line pattern connected to the second power pad pattern is the second conductive line pattern;

[0118] The conductive line pattern connected to the third power pad pattern is the third conductive line pattern.

[0119] In some embodiments, the second conductive line pattern is bent within the first conductive area to form: a plurality of alternating first recessed regions and second recessed regions extending along a first direction;

[0120] Wherein, the notch in the first recessed region faces the opposite direction to the notch in the second recessed region;

[0121] The first conductive line pattern includes multiple first branch lines extending into the first recessed region along the first direction; the third conductive line pattern includes multiple second branch lines extending into the second recessed region along the first direction.

[0122] In some embodiments, the layout structure further includes:

[0123] The memory cell array area layout is located on the side of the high-speed circuit module layout away from the power pad pattern; the memory cell array area layout includes multiple memory cell array patterns; the power pad pattern and the memory cell array pattern are connected through the conductive line pattern of the redistribution layer layout.

[0124] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0125] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0127] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0128] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0129] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A high-speed circuit module includes a clock signal, the frequency of which is greater than a first threshold. A first conductive metal layer, comprising a plurality of power wires extending along a first direction and spaced apart, electrically connected to the high-speed circuit module; A redistribution layer, located on the first conductive metal layer, includes: a plurality of power pads and conductive lines connected to the power pads; wherein the power pads are located on one side of the high-speed circuit module, and the projected area of ​​the power pads does not overlap with the high-speed circuit module; the conductive lines include a first conductor area formed by repeated bending, the first conductor area at least partially covering the high-speed circuit module, and the conductive lines are used to electrically connect the power conductors and the power pads; The conductive line extends from the power pad to the first conductor area and is repeatedly bent to increase the overlapping area of ​​the conductive line and the power conductor in the first conductor area. The conductive line and the power conductor are electrically connected through multiple connection holes to reduce the contact resistance between the conductive line and the power conductor.

2. The semiconductor structure according to claim 1, characterized in that, Multiple power pads are used to provide different power supply voltages; Each power conductor includes multiple power lines, each power line being used to connect to different power pads; wherein, each power line is electrically connected to the conductive line of the corresponding power source through multiple connection holes.

3. The semiconductor structure according to claim 2, characterized in that, The conductive lines connected to the multiple power pads are distributed at equal intervals in the first conductor area.

4. The semiconductor structure according to claim 3, characterized in that, The plurality of power pads include at least: a first power pad, a second power pad, and a third power pad arranged sequentially along a first direction; the first direction is the extension direction of the power conductor; The conductive line connected to the first power pad is the first conductive line; The conductive line connected to the second power pad is the second conductive line; The conductive line connected to the third power pad is the third conductive line.

5. The semiconductor structure according to claim 4, characterized in that, The second conductive wire is bent within the first conductor region to form: a plurality of alternating first and second recessed regions extending along the first direction; Wherein, the notch in the first recessed region faces the opposite direction to the notch in the second recessed region; The first conductive line includes a plurality of first branches extending into the first recessed region along the first direction; the third conductive line includes a plurality of second branches extending into the second recessed region along the first direction.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, Also includes: The storage cell array area is located on the side of the high-speed circuit module away from the power pad; the storage cell array area includes multiple storage cell arrays; The power pads are connected to the memory cell array via conductive lines in the redistribution layer.

7. The semiconductor structure according to claim 6, characterized in that, The conductive lines of the redistribution layer further include a second conductive area for connecting the memory cell array; wherein the conductive lines of the second conductive area do not overlap with the projection area of ​​the high-speed circuit module; the conductive lines of the first conductive area and the second conductive area are interconnected.

8. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure includes a first region and a second region arranged in parallel. The redistribution layer of the first region and the redistribution layer of the second region each include a plurality of power pads; wherein, the power pads of the first region are connected to the memory cell array of the first region through the conductive lines of the first region; and the power pads of the second region are connected to the memory cell array of the second region through the conductive lines of the second region.

9. The semiconductor structure according to claim 8, characterized in that, At least one power pad in the first region provides the same power voltage as at least one power pad in the second region.

10. The semiconductor structure according to claim 9, characterized in that, The difference in resistance values ​​of the conductive lines connected to the power pads in the first and second regions, which are used to provide the same power supply voltage, is less than a preset threshold.

11. The semiconductor structure according to claim 10, characterized in that, The resistance values ​​of the conductive lines connected to the power pads in the first and second regions, which are used to provide the same power supply voltage, are the same.

12. The semiconductor structure according to claim 8, characterized in that, The first conductor area of ​​the conductive line connected to the power pad in the first region is axially symmetrical to the first conductor area of ​​the conductive line connected to the power pad in the second region.

13. A layout structure, characterized in that, include: The high-speed circuit module layout includes at least a clock signal containing a frequency greater than a first threshold. The first conductive metal layer layout includes multiple power wire patterns extending along a first direction, used to represent the layout of the high-speed circuit module electrically connected to the circuit. A redistribution layer layout is located on the first conductive metal layer layout. The redistribution layer layout includes: multiple power pad patterns and conductive line patterns connected to the power pad patterns; wherein, the power pad patterns are located on one side of the high-speed circuit module layout, and the projected area of ​​the power pad patterns does not overlap with the high-speed circuit module layout; the conductive line patterns include a first conductor area formed by repeated bending, the first conductor area at least partially covering the high-speed circuit module layout, and the conductive line patterns connect the power conductor patterns and the power pad patterns; The conductive line extends from the power pad to the first conductor area and is repeatedly bent to increase the overlapping area of ​​the conductive line and the power conductor in the first conductor area. The conductive line and the power conductor are electrically connected through multiple connection holes to reduce the contact resistance between the conductive line and the power conductor.

14. The layout structure according to claim 13, characterized in that, The plurality of power pad patterns include at least: a first power pad pattern, a second power pad pattern, and a third power pad pattern arranged sequentially along a first direction; the first direction is the extension direction of the power conductor pattern; The conductive line pattern connected to the first power pad pattern is the first conductive line pattern. The conductive line pattern connected to the second power pad pattern is the second conductive line pattern; The conductive line pattern connected to the third power pad pattern is the third conductive line pattern.

15. The layout structure according to claim 14, characterized in that, The second conductive line pattern is bent within the first conductive area to form: a plurality of alternating first and second recessed regions extending along the first direction; Wherein, the notch in the first recessed region faces the opposite direction to the notch in the second recessed region; The first conductive line pattern includes multiple first branch lines extending into the first recessed region along the first direction; the third conductive line pattern includes multiple second branch lines extending into the second recessed region along the first direction.

16. The layout structure according to claim 13, characterized in that, Also includes: The memory cell array area layout is located on the side of the high-speed circuit module layout away from the power pad pattern; The storage cell array layout includes multiple storage cell array patterns; The power pad pattern and the memory cell array pattern are connected through the conductive line pattern of the redistribution layer layout.

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