Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the same. The structure includes: a substrate; a first channel layer on the substrate and a second channel layer on the first channel layer, a first opening between the first channel layer and the substrate, and a third opening between the second channel layer and the first channel layer; a first isolation layer on the substrate, the first isolation layer exposing a sidewall surface of the first channel layer; a second isolation layer in the first opening, the first isolation layer also on a sidewall surface of the second isolation layer; a gate structure on the first isolation layer and in the third opening, the gate structure surrounding the second channel layer and crossing the first channel layer; a first epitaxial doped region on the first isolation layer on both sides of the gate structure and a first connection layer on the first epitaxial doped region; a second epitaxial doped region on the first connection layer and a second connection layer on the second epitaxial doped region, the second epitaxial doped region contacting a sidewall of the second channel layer. The semiconductor structure is simple to form.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] The continued development of the semiconductor industry relies on the continuous increase in device density per unit area of ​​chips, which is achieved through the reduction of device size. Reducing device size also improves turn-on current and cut-off frequency, and further reduces power consumption, resulting in chips with higher performance and lower power consumption, thus driving the information industry forward. However, the reduction in semiconductor device size will eventually reach its physical limits. To continue Moore's Law's cycle of doubling the performance of chips of the same area every eighteen months, many new types of devices have emerged, one of which is the vertically stacked complementary field-effect transistor (CFET).

[0003] Complementary field-effect transistors (CFPTs) are a promising structural design because their vertical stacking structure allows for further expansion of device size at a lower performance cost.

[0004] The complementary field-effect transistor structure can be viewed as an NMOS stacked on a PMOS. The NMOS structure is similar to the GAA (Gate-All-around) structure, while the PMOS structure is similar to the FinFET (Fin Field-Effect Transistor) structure.

[0005] The fabrication process for existing complementary field-effect transistor structures still needs improvement. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the existing forming process of complementary field-effect transistor structure.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a first channel layer on the substrate and a second channel layer on the first channel layer, wherein a first opening is formed between the first channel layer and the substrate, and a third opening is formed between the second channel layer and the first channel layer; a first isolation layer on the substrate, the first isolation layer exposing the sidewall surface of the first channel layer; a second isolation layer located within the first opening, the first isolation layer also located on the sidewall surface of the second isolation layer; a gate structure on the first isolation layer, the gate structure also located within the third opening, the gate structure surrounding the second channel layer and spanning the first channel layer; a first epitaxial doped region on the first isolation layer on both sides of the gate structure and a first interconnecting layer on the first epitaxial doped region, the first epitaxial doped region being in contact with the first channel layer; a second epitaxial doped region on the first interconnecting layer and a second interconnecting layer on the second epitaxial doped region, the second epitaxial doped region being in contact with the sidewall of the second channel layer.

[0008] Optionally, the first channel layer includes a first portion located at the bottom of the gate structure and a second portion located on both sides of the first portion; the first epitaxial doped region is located on the sidewall surface and the top surface of the second portion.

[0009] Optionally, the sidewall surfaces of the first and second channel layers are flush; the first epitaxial doped region is located on the sidewall surface of the first channel layer.

[0010] Optionally, it also includes: an inner wall located on the third opening sidewall, the inner wall being located between the first channel layer and the second channel layer, and the outer surface of the inner wall being flush with the sidewall of the second channel layer.

[0011] Optionally, it may also include: a third isolation layer located on the first interconnect layer, the third isolation layer being located on the top surface and sidewall surface of the first interconnect layer, the third isolation layer electrically isolating the second epitaxial doped region and the first interconnect layer, and electrically isolating the gate structure and the first interconnect layer.

[0012] Optionally, it further includes: a fourth isolation layer located on the second epitaxial doped region, the second connection layer being located within the fourth isolation layer, the fourth isolation layer electrically isolating the gate structure and the second connection layer.

[0013] Optionally, the material of the first epitaxial doped region includes silicon-germanium; the material of the second epitaxial doped region includes silicon-phosphorus.

[0014] Optionally, the substrate includes: a base and a bottom structure located on the base; the first isolation layer is located on the base and on the sidewall of the bottom structure.

[0015] Optionally, the material of the first isolation layer includes silicon oxide; the material of the second isolation layer includes silicon oxide.

[0016] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, including tungsten.

[0017] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial first stacked structure and an initial second stacked structure on the substrate, the initial first stacked structure including a first sacrificial layer and an initial first channel layer on the first sacrificial layer, the initial second stacked structure including an initial second sacrificial layer and an initial second channel layer on the initial second sacrificial layer; forming an initial first isolation layer on the substrate, the initial first isolation layer also being located on the sidewall of the first sacrificial layer, the initial first isolation layer exposing the sidewall surface of the initial first channel layer; forming a dummy gate structure on the initial first isolation layer, the dummy gate structure spanning the initial first stacked structure and the initial first channel layer; after forming the dummy gate structure, removing the first sacrificial layer to form a first opening between the initial first channel layer and the substrate; forming a second isolation layer within the first opening, and forming a first isolation layer on the substrate, the first isolation layer exposing the sidewall surface of the initial first channel layer, the first isolation layer also being located on the second... The isolation layer sidewall surface; using the dummy gate structure as a mask, the initial second stacked structure and the initial first channel layer are etched to form a first channel layer, a second sacrificial layer, and a second channel layer located on the second sacrificial layer; a first epitaxial doped region and a first interconnect layer located on the first epitaxial doped region are formed on the first isolation layer on both sides of the dummy gate structure, the first epitaxial doped region being in contact with the first channel layer; a second epitaxial doped region and a second interconnect layer located on the second epitaxial doped region are formed on the first interconnect layer, the second epitaxial doped region being in contact with the sidewall of the second channel layer; after forming the second interconnect layer, the dummy gate structure and the second sacrificial layer are removed, and a second opening is formed between the first epitaxial doped regions, between the first interconnect layers, between the second epitaxial doped regions, and between the second interconnect layer; a third opening is formed between the first channel layer and the second channel layer, the second opening exposing the first channel layer, the second channel layer, and the third opening; a gate structure is formed within the third opening and the second opening, the gate structure surrounding the second channel layer and spanning the first channel layer.

[0018] Optionally, the first channel layer includes a first portion located at the bottom of the second sacrificial layer and a second portion located on both sides of the first portion; the first epitaxial doped region is located on the sidewall surface and the top surface of the second portion.

[0019] Optionally, when etching the initial second stacked structure and the initial first channel layer, the first isolation layer surface is exposed to form a first channel layer, a second sacrificial layer and a second channel layer located on the second sacrificial layer, wherein the first channel layer and the sidewall surface of the second channel layer are flush; the first epitaxial doped region is located on the sidewall surface of the first channel layer.

[0020] Optionally, the method of removing the first sacrificial layer to form a first opening between the initial first channel layer and the substrate includes: removing the initial first isolation layer on both sides of the substrate of the dummy gate structure to expose the sidewall surface of the first sacrificial layer; and removing the exposed first sacrificial layer to form a first opening between the initial first channel layer and the substrate.

[0021] Optionally, before etching the initial first isolation layer, the method further includes: forming a first protective layer on the surface of the initial first stacked structure, the surface of the dummy gate structure, and the surface of the initial first channel layer; and before etching the initial second stacked structure and the initial first channel layer using the dummy gate structure as a mask, the method further includes: removing the first protective layer.

[0022] Optionally, after forming the first channel layer, the second sacrificial layer, and the second channel layer located on the second sacrificial layer, and before forming the first epitaxial doped region on the first isolation layer on both sides of the pseudo gate structure, the method further includes: forming an inner sidewall on the sidewall of the second sacrificial layer, wherein the outer surface of the inner sidewall is flush with the sidewall of the second channel layer.

[0023] Optionally, while forming an inner sidewall on the second sacrificial layer sidewall, the method further includes forming a second protective layer on the surface of the dummy gate structure, the surface of the second sacrificial layer, and the surface of the second channel layer, wherein the second protective layer exposes the surface of the first channel layer.

[0024] Optionally, before forming the second epitaxial doped region on the first interconnect layer, the method further includes: removing the second protective layer from the sidewall surface of the second channel layer.

[0025] Optionally, after forming the first epitaxial doped region and the first interconnect layer located on the first epitaxial doped region, the method further includes: forming a third isolation layer on the first epitaxial doped region, the third isolation layer being located on the top surface and sidewall surface of the first interconnect layer, the third isolation layer electrically isolating the second epitaxial doped region and the first interconnect layer, and electrically isolating the gate structure and the first interconnect layer.

[0026] Optionally, before removing the dummy gate structure and the second sacrificial layer, the method further includes: forming a fourth isolation layer located on the second epitaxial doped region, wherein the second connection layer is located within the fourth isolation layer, and the fourth isolation layer electrically isolates the gate structure and the second connection layer.

[0027] Optionally, the method for forming the second and third openings includes: removing the dummy gate structure to form a second opening between the first epitaxial doped regions, between the first interconnect layers, between the second epitaxial doped regions, and between the second interconnect layer, the second opening exposing the first channel layer, the second channel layer, and the second sacrificial layer; removing the second sacrificial layer to form a third opening between the first channel layer and the second channel layer.

[0028] Optionally, the substrate includes: a base and a bottom structure located on the base, the bottom structure extending in a direction parallel to the extending directions of the initial first stacked structure and the initial second stacked structure; the first isolation layer is located on the base and on the sidewall of the bottom structure.

[0029] Optionally, the method for forming the substrate, bottom structure, initial first stacked structure, and initial second stacked structure includes: forming an initial substrate; forming a first stacked structure material layer on the initial substrate; forming a second stacked structure material layer on the first stacked structure material layer; forming a mask structure on the stacked material layer; etching the second stacked structure material layer, the first stacked material layer, and the initial substrate using the mask structure as a mask to form a substrate and a bottom structure located on the substrate; and forming an initial first stacked structure located on the bottom structure and an initial second stacked structure located on the initial first stacked structure.

[0030] Optionally, the material of the first epitaxial doped region includes silicon-germanium; the material of the second epitaxial doped region includes silicon-phosphorus.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] The present invention employs a novel process to form a semiconductor structure. The second isolation layer isolates the device structure from the substrate, reducing leakage current. The process is simple and has a low cost.

[0033] The semiconductor structure formation method of the present invention forms a first opening by removing a first sacrificial layer, and then forms a second isolation layer in the first opening. The second isolation layer isolates the device structure from the substrate, reducing leakage current. At the same time, the process of forming the second isolation layer is simple and has low cost.

[0034] Furthermore, the first channel layer includes a first portion located at the bottom of the second sacrificial layer and a second portion located on both sides of the first portion. Thus, when the first epitaxial doped region is formed on the first isolation layer, the first epitaxial doped region can be grown on the surface of the second portion, thereby increasing the growable area of ​​the first epitaxial doped region and accelerating the growth rate of the first epitaxial doped region, which is beneficial for forming a larger volume of the first epitaxial doped region.

[0035] Furthermore, the bottom structure and substrate are formed by etching the initial substrate, which is a simple process with low cost. Attached Figure Description

[0036] Figures 1 to 23 This is a schematic diagram of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Implementation

[0037] As described in the background section, the performance of existing complementary field-effect transistor structures still needs to be improved.

[0038] Specifically, in existing complementary field-effect transistor (CPFET) structures, a bottom isolation layer is typically formed between the PMOS device structure and the substrate to reduce leakage current. Silicon-on-insulator (SOI) substrates are commonly used, which have a natural oxide isolation layer in the middle, serving as the bottom isolation between the PMOS device structure and the substrate. However, the fabrication cost of SOI substrates is relatively high, requiring a series of processes to form them. Therefore, optimization of the semiconductor structure formation process is necessary.

[0039] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. A first opening is formed by removing a first sacrificial layer, and a second isolation layer is formed within the first opening. The second isolation layer isolates the device structure from the substrate, reducing leakage current. Furthermore, the process for forming the second isolation layer is simple and has low cost.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0042] Figures 1 to 23 This is a schematic diagram of the method for forming a semiconductor structure in an embodiment of the present invention.

[0043] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0044] Please refer to Figures 1 to 3 , Figure 3 yes Figure 1 and Figure 2 Top view, Figure 1 yes Figure 3 A schematic diagram of the cross-sectional structure along section line AA1. Figure 2 yes Figure 3A schematic diagram of the cross-sectional structure along the BB1 ​​direction, providing a substrate.

[0045] The substrate includes a substrate 200 and a bottom structure 201 located on the substrate 200, wherein the extension direction of the bottom structure 201 is parallel to the extension direction of the subsequently formed initial first stacked structure and initial second stacked structure.

[0046] In this embodiment, the substrate is made of silicon.

[0047] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0048] Please continue to refer to this. Figures 1 to 3 An initial first stacked structure and an initial second stacked structure are formed on a substrate. The initial first stacked structure includes a first sacrificial layer 202 and an initial first channel layer 203 on the first sacrificial layer 202. The initial second stacked structure includes an initial second sacrificial layer 204 and an initial second channel layer 205 on the initial second sacrificial layer 204.

[0049] The method for forming the substrate 200, bottom structure 201, initial first stacked structure, and initial second stacked structure includes: forming an initial substrate (not shown); forming a first stacked structure material layer (not shown) on the initial substrate; forming a second stacked structure material layer (not shown) on the first stacked structure material layer; forming a mask structure (not shown) on the stacked material layer; etching the second stacked structure material layer, the first stacked material layer, and the initial substrate using the mask structure as a mask to form the substrate 200 and the bottom structure 201 located on the substrate 200, and forming the initial first stacked structure located on the bottom structure 201 and the initial second stacked structure located on the initial first stacked structure.

[0050] The bottom structure 201 and the substrate 200 are formed by etching the initial substrate, which is a simple process with low cost.

[0051] The first sacrificial layer 202 and the initial first channel layer 203 are made of different materials, and the initial second sacrificial layer 204 and the initial second channel layer 205 are made of different materials. Specifically, the first sacrificial layer 202 is made of monocrystalline silicon or monocrystalline germanium silicon; the initial second sacrificial layer 204 is made of monocrystalline silicon or monocrystalline germanium silicon; the initial first channel layer 203 is made of monocrystalline silicon or monocrystalline germanium silicon; and the initial second channel layer 205 is made of monocrystalline silicon or monocrystalline germanium silicon.

[0052] In this embodiment, the first sacrificial layer 202 and the initial second sacrificial layer 204 are made of silicon-germanium; the initial first channel layer 203 and the initial second channel layer 205 are made of monocrystalline silicon.

[0053] The first sacrificial layer 202 and the initial first channel layer 203 are made of different materials, and the initial second sacrificial layer 204 and the initial second channel layer 205 are made of different materials. This results in the first sacrificial layer 202 and the initial first channel layer 203 having different etching selectivity, and the initial second sacrificial layer 204 and the initial second channel layer 205 having different etching selectivity. Therefore, when the first sacrificial layer 202 and the initial second sacrificial layer 204 are removed subsequently, the damage to the initial first channel layer 203 and the initial second channel layer 205 is smaller.

[0054] Please refer to Figure 4 and Figure 5 , Figure 4 In order to be in Figure 2 A basic diagram. Figure 5 In order to be in Figure 1 The schematic diagram shows an initial first isolation layer 206 formed on a substrate. The initial first isolation layer 206 is also located on the sidewall of the first sacrificial layer 202, and the initial first isolation layer 206 exposes the sidewall surface of the initial first channel layer 203.

[0055] The material of the initial first isolation layer 206 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0056] In this embodiment, the material of the initial first isolation layer 206 includes silicon oxide.

[0057] Please continue to refer to this. Figure 4 and Figure 5 A pseudo-gate structure 207 is formed on the initial first isolation layer 206, the pseudo-gate structure 207 spanning the initial first stack structure and the initial first channel layer 203.

[0058] The dummy gate structure 207 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not labeled) located on the dummy gate dielectric layer.

[0059] In this embodiment, the material of the dummy gate dielectric layer includes silicon oxide or a low-K (K less than 3.9) material; the material of the dummy gate layer includes polysilicon.

[0060] Next, after forming the dummy gate structure, the first sacrificial layer 202 is removed, forming a first opening between the initial first channel layer 203 and the substrate. For the process of forming the first opening, please refer to [link to documentation / reference]. Figures 6 to 11 .

[0061] Please refer to Figures 6 to 9 , Figure 8 for Figure 6 , Figure 7 and Figure 9 Top view, Figure 6 for Figure 8 A schematic diagram of the structure along section line BB1. Figure 7 for Figure 8 A schematic diagram of the structure along section line AA1. Figure 9 for Figure 8 A schematic diagram along the cross-section CC1 shows that a first protective layer 208 is formed on the surface of the initial first stacked structure, the surface of the pseudo-gate structure 207, and the surface of the initial first channel layer 203.

[0062] The material of the first protective layer 208 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0063] In this embodiment, the material of the first protective layer 208 includes silicon nitride.

[0064] Please continue to refer to this. Figures 6 to 9 After forming the first protective layer 208, the initial first isolation layer 206 on the substrates on both sides of the dummy gate structure 207 is removed, exposing the sidewall surface of the first sacrificial layer 202.

[0065] The process of removing the initial first isolation layer 206 on both sides of the substrate of the dummy gate structure 207 includes an etch-back process.

[0066] The material of the first protective layer 208 is different from that of the initial first isolation layer 206, so that when the initial first isolation layer 206 is etched back, the first protective layer 208 can protect the surface of the initial first stacked structure, the surface of the dummy gate structure 207 and the initial first channel layer 203.

[0067] Please refer to Figure 10 and Figure 11 , Figure 10 In order to be in Figure 9 A structural diagram based on the basic structure. Figure 11 In order to be in Figure 6 Based on the structural schematic diagram, the exposed first sacrificial layer 202 is removed, and a first opening 209 is formed between the initial first channel layer 203 and the substrate.

[0068] The process for removing the first sacrificial layer 202 includes a wet etching process.

[0069] In this embodiment, the first opening 209 is located between the initial first channel layer 203 and the bottom structure 201.

[0070] Please refer to Figure 12 and Figure 13 , Figure 12 In order to be in Figure 10 A structural diagram based on the basic structure. Figure 13 In order to be in Figure 11 Based on the structural schematic diagram, a second isolation layer 211 is formed in the first opening 209, and a first isolation layer 210 is formed on the substrate. The first isolation layer 210 exposes the sidewall surface of the initial first channel layer 203, and the first isolation layer 210 is also located on the sidewall surface of the second isolation layer 211.

[0071] In this embodiment, the second isolation layer 211 and the first isolation layer 210 are formed simultaneously.

[0072] The materials of the second isolation layer 211 and the first isolation layer 210 include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0073] In this embodiment, the materials of the second isolation layer 211 and the first isolation layer 210 include silicon oxide.

[0074] The first opening 209 is formed by removing the first sacrificial layer 202, and then the second isolation layer 211 is formed in the first opening 209. The second isolation layer 211 isolates the device structure from the substrate, reducing the generation of leakage current. At the same time, the process of forming the second isolation layer 211 is simple and low in cost.

[0075] Please refer to Figures 14 to 16 , Figure 14 for Figure 15 and Figure 16 Top view, Figure 15 for Figure 14 A schematic diagram of the structure along section line AA1. Figure 16 for Figure 14 A structural schematic diagram along the cross-section line CC1 shows that after forming the second isolation layer 211 and the first isolation layer 210, the first protective layer 208 is removed.

[0076] Please continue to refer to this. Figures 14 to 16Using the pseudo gate structure 207 as a mask, the initial second stacked structure and part of the initial first channel layer 203 are etched to form the first channel layer 303, the second sacrificial layer 304 and the second channel layer 305 located on the second sacrificial layer 304.

[0077] In this embodiment, the initial second stacked structure and a portion of the initial first channel layer 203 are etched. The first channel layer 303 includes a first portion located at the bottom of the second sacrificial layer 304 and a second portion located on both sides of the first portion.

[0078] In other embodiments, during the etching of the initial second stack structure and the initial first channel layer, the etching continues until the surface of the first isolation layer is exposed, forming a first channel layer, a second sacrificial layer, and a second channel layer located on the second sacrificial layer, with the sidewall surfaces of the first and second channel layers flush. The subsequently formed first epitaxial doped region is located on the sidewall surface of the first channel layer.

[0079] Please continue to refer to this. Figures 14 to 16 An inner sidewall 213 is formed on the sidewall of the second sacrificial layer 304, and the outer surface of the inner sidewall 213 is flush with the sidewall of the second channel layer 305.

[0080] In this embodiment, while forming an inner sidewall 213 on the sidewall of the second sacrificial layer 304, a second protective layer 212 is also formed on the surface of the dummy gate structure 207, the surface of the inner sidewall 213, and the surface of the second channel layer 305. The second protective layer 212 exposes the surface of the first channel layer 303. The second protective layer 212 protects the dummy gate structure 207 and the surface of the first channel layer 303.

[0081] The material of the inner wall 213 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0082] In this embodiment, the material of the inner wall 213 includes silicon nitride.

[0083] Please refer to Figure 17 and Figure 18 , Figure 17 In order to be in Figure 15 A structural diagram based on the basic structure. Figure 18 In order to be in Figure 16 Based on the structural diagram, a first epitaxial doped region 214 is formed on the first isolation layer 211 on both sides of the pseudo gate structure 207, and the first epitaxial doped region 214 is in contact with the first channel layer 303.

[0084] In this embodiment, the first epitaxial doped region 214 is located on the sidewall surface and top surface of the second portion.

[0085] The first channel layer 303 includes a first portion located at the bottom of the second sacrificial layer 304 and a second portion located on both sides of the first portion. Thus, when the first epitaxial doped region 214 is formed on the first isolation layer 211, the first epitaxial doped region 214 can be grown on the surface of the second portion, thereby increasing the growable area of ​​the first epitaxial doped region 214 and accelerating the growth rate of the first epitaxial doped region 214, which is beneficial for forming a larger volume of the first epitaxial doped region 214.

[0086] In this embodiment, the material of the first epitaxial doped region 214 includes silicon and germanium.

[0087] The process of forming the first epitaxial doped region 214 includes an epitaxial growth process. In this embodiment, the first epitaxial doped region 214 is used to form a P-type device.

[0088] Please refer to Figure 19 and Figure 20 , Figure 19 In order to be in Figure 17 A structural diagram based on the basic structure. Figure 20 In order to be in Figure 18 The schematic diagram is based on the structure, with a first connecting layer 215 formed on the first epitaxial doped region 214.

[0089] The first connection layer 215 is used to electrically connect the first epitaxial doped region 213 to an external circuit.

[0090] The material of the first connecting layer 215 includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0091] Please continue to refer to this. Figure 19 and Figure 20 A third isolation layer 216 is formed on the first epitaxial doped region 214. The third isolation layer 216 is located on the top surface and sidewall surface of the first interconnect layer 215. The third isolation layer 216 electrically isolates the subsequently formed second epitaxial doped region and the first interconnect layer 215, as well as the subsequently formed gate structure and the first interconnect layer 215.

[0092] The top surface of the third isolation layer 216 is lower than the bottom surface of the second channel layer 305.

[0093] The material of the third isolation layer 216 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0094] In this embodiment, the material of the third isolation layer 216 includes silicon oxide.

[0095] Please refer to Figure 21 and Figure 22 , Figure 21 In order to be in Figure 19 A structural diagram based on the basic structure. Figure 22 In order to be in Figure 20 Based on the structural diagram, the second protective layer 212 is removed, exposing the sidewall surface of the second channel 202.

[0096] Please continue to refer to this. Figure 21 and Figure 22 A second epitaxial doped region 217 and a second connecting layer 218 located on the third isolation layer 216 are formed thereon, and the second epitaxial doped region 217 is in contact with the sidewall of the second channel layer 305.

[0097] The process of forming the second epitaxial doped region 217 includes an epitaxial growth process. In this embodiment, the second epitaxial doped region 217 is used to form an N-type device.

[0098] In this embodiment, the material of the second epitaxial doped region 217 includes phosphorus silicon.

[0099] The second connection layer 218 is used to electrically connect the second epitaxial doped region 217 to an external circuit.

[0100] The material of the second connecting layer 218 includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0101] Please continue to refer to this. Figure 21 and Figure 22 A fourth isolation layer 219 is formed on the second epitaxial doped region 217, and the second connection layer 218 is located within the fourth isolation layer 219. The fourth isolation layer 219 electrically isolates the subsequently formed gate structure and the second connection layer 218.

[0102] The material of the fourth isolation layer 219 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0103] In this embodiment, the material of the fourth isolation layer 219 includes silicon oxide.

[0104] Please refer to Figure 23 , Figure 23 In order to be in Figure 21Based on the structural diagram, the pseudo-gate structure 207 and the second sacrificial layer 304 are removed, and a second opening (not shown) is formed between the first epitaxial doped region 214, the third isolation layer 216, the second epitaxial doped region 217 and the fourth isolation layer 219. A third opening (not shown) is formed between the first channel layer 303 and the second channel layer 305. The second opening exposes the first channel layer 303, the second channel layer 305 and the third opening.

[0105] The method for forming the second and third openings includes: removing the dummy gate structure 207, forming a second opening between the first epitaxial doped regions 214, the third isolation layer 216, the second epitaxial doped regions 217, and the fourth isolation layer 219, the second opening exposing the first channel layer 303, the second channel layer 305, and the second sacrificial layer 304; removing the second sacrificial layer 304, and forming a third opening between the first channel layer 303 and the second channel layer 305.

[0106] Please continue to refer to this. Figure 23 A gate structure 220 is formed in the third opening and the second opening, the gate structure 220 surrounds the second channel layer 305, and the gate structure 220 spans the first channel layer 303.

[0107] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 23 ,include:

[0108] Substrate;

[0109] A first trench layer 303 is located on the substrate and a second trench layer 305 is located on the first trench layer 303. The first trench layer 303 and the substrate have a first opening, and the second trench layer 305 and the first trench layer have a third opening.

[0110] A first isolation layer is located on the substrate, the first isolation layer exposing the sidewall surface of the first channel layer 303;

[0111] The second isolation layer 211 is located within the first opening, and the first isolation layer is also located on the sidewall surface of the second isolation layer 211;

[0112] A gate structure 220 is located on the first isolation layer, the gate structure 220 is also located in the third opening, the gate structure 220 surrounds the second channel layer 305, and the gate structure 220 spans the first channel layer 303;

[0113] The first epitaxial doped region 214 is located on the first isolation layer on both sides of the gate structure 220 and the first interconnect layer 215 is located on the first epitaxial doped region 214. The first epitaxial doped region 214 is in contact with the first channel layer 303.

[0114] The second epitaxial doped region 217 is located on the first connecting layer 215 and the second connecting layer 218 is located on the second epitaxial doped region 217. The second epitaxial doped region 218 is in contact with the sidewall of the second channel layer 305.

[0115] In this embodiment, the first channel layer 303 includes a first portion located at the bottom of the gate structure 220 and a second portion located on both sides of the first portion; the first epitaxial doped region 214 is located on the sidewall surface and the top surface of the second portion.

[0116] In other embodiments, the sidewall surfaces of the first channel layer and the second channel layer are flush; the first epitaxial doped region is located on the sidewall surface of the first channel layer.

[0117] In this embodiment, it further includes an inner wall 213 located on the third opening sidewall, the inner wall 213 being located between the first channel layer 303 and the second channel layer 305, and the outer surface of the inner wall 213 being flush with the sidewall of the second channel layer 305.

[0118] In this embodiment, it further includes: a third isolation layer 216 located on the first connection layer 215, the third isolation layer 216 being located on the top surface and sidewall surface of the first connection layer 215, the third isolation layer 216 electrically isolating the second epitaxial doped region 217 and the first connection layer 218, and electrically isolating the gate structure 220 and the first connection layer 215.

[0119] In this embodiment, it further includes: a fourth isolation layer 219 located on the second epitaxial doped region 217, the second connection layer 218 located within the fourth isolation layer 219, and the fourth isolation layer 219 electrically isolating the gate structure 220 and the second connection layer 218.

[0120] In this embodiment, the material of the first epitaxial doped region 214 includes silicon and germanium; the material of the second epitaxial doped region 217 includes silicon phosphide.

[0121] In this embodiment, the substrate includes: a base 200 and a bottom structure 201 located on the base 200; the first isolation layer is located on the base 200 and on the sidewall of the bottom structure 201.

[0122] In this embodiment, the material of the first isolation layer includes silicon oxide; the material of the second isolation layer 211 includes silicon oxide.

[0123] In this embodiment, the gate structure 220 includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes metal, and the metal includes tungsten.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first trench layer is located on a substrate and a second trench layer is located on the first trench layer, wherein the first trench layer and the substrate have a first opening and the second trench layer and the first trench layer have a third opening; A first isolation layer is located on the substrate, the first isolation layer exposing the sidewall surface of the first channel layer; A second isolation layer is located within the first opening, and the first isolation layer is also located on the sidewall surface of the second isolation layer; A gate structure located on a first isolation layer, the gate structure also located within the third opening, the gate structure surrounding the second channel layer, and the gate structure spanning the first channel layer; A first epitaxial doped region is located on the first isolation layer on both sides of the gate structure, and a first interconnect layer is located on the first epitaxial doped region, wherein the first epitaxial doped region is in contact with the first channel layer; The second epitaxial doped region is located on the first connecting layer and the second connecting layer is located on the second epitaxial doped region, wherein the second epitaxial doped region is in contact with the sidewall of the second channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, The first channel layer includes a first portion located at the bottom of the gate structure and a second portion located on both sides of the first portion; the first epitaxial doped region is located on the sidewall surface and the top surface of the second portion.

3. The semiconductor structure as described in claim 1, characterized in that, The sidewall surfaces of the first and second channel layers are flush; the first epitaxial doped region is located on the sidewall surface of the first channel layer.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: The inner wall is located on the third opening sidewall, between the first channel layer and the second channel layer, and the outer surface of the inner wall is flush with the sidewall of the second channel layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A third isolation layer is located on the first interconnect layer, the third isolation layer being located on the top surface and sidewall surface of the first interconnect layer, the third isolation layer electrically isolating the second epitaxial doped region and the first interconnect layer, as well as electrically isolating the gate structure and the first interconnect layer.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A fourth isolation layer is located on the second epitaxial doped region, and the second interconnect layer is located within the fourth isolation layer. The fourth isolation layer electrically isolates the gate structure and the second interconnect layer.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the first epitaxial doped region includes silicon and germanium; the material of the second epitaxial doped region includes silicon phosphide.

8. The semiconductor structure as described in claim 1, characterized in that, The substrate includes: a base and a bottom structure located on the base; the first isolation layer is located on the base and on the sidewall of the bottom structure.

9. The semiconductor structure as described in claim 1, characterized in that, The material of the first isolation layer includes silicon oxide; the material of the second isolation layer includes silicon oxide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, including tungsten.

11. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; An initial first stacked structure and an initial second stacked structure are formed on a substrate, the initial first stacked structure including a first sacrificial layer and an initial first channel layer on the first sacrificial layer, and the initial second stacked structure including an initial second sacrificial layer and an initial second channel layer on the initial second sacrificial layer. An initial first isolation layer is formed on the substrate, the initial first isolation layer also being located on the sidewall of the first sacrificial layer, the initial first isolation layer exposing the sidewall surface of the initial first channel layer; A pseudo-gate structure is formed on the initial first isolation layer, the pseudo-gate structure spanning the initial first stacked structure and the initial first channel layer; After forming the dummy gate structure, the first sacrificial layer is removed, and a first opening is formed between the initial first channel layer and the substrate; A second isolation layer is formed within the first opening, and a first isolation layer is formed on the substrate, the first isolation layer exposing the sidewall surface of the initial first channel layer, and the first isolation layer is also located on the sidewall surface of the second isolation layer; Using the pseudo-gate structure as a mask, the initial second stacked structure and the initial first channel layer are etched to form a first channel layer, a second sacrificial layer and a second channel layer located on the second sacrificial layer; A first epitaxial doped region and a first interconnect layer located on the first isolation layer on both sides of the pseudo gate structure are formed, wherein the first epitaxial doped region is in contact with the first channel layer; A second epitaxial doped region and a second interconnect layer are formed on the first interconnect layer, wherein the second epitaxial doped region is in contact with the sidewall of the second channel layer; After forming the second interconnect layer, the dummy gate structure and the second sacrificial layer are removed, and a second opening is formed between the first epitaxial doped regions, between the first interconnect layers, between the second epitaxial doped regions and between the second interconnect layer. A third opening is formed between the first channel layer and the second channel layer. The second opening exposes the first channel layer, the second channel layer and the third opening. A gate structure is formed within a third opening and a second opening, the gate structure surrounding the second channel layer and spanning the first channel layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first channel layer includes a first portion located at the bottom of the second sacrificial layer and a second portion located on both sides of the first portion; the first epitaxial doped region is located on the sidewall surface and the top surface of the second portion.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, When etching the initial second stacked structure and the initial first channel layer, the first isolation layer surface is exposed to form a first channel layer, a second sacrificial layer and a second channel layer located on the second sacrificial layer. The first channel layer and the sidewall surface of the second channel layer are flush. The first epitaxial doped region is located on the sidewall surface of the first channel layer.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method of removing the first sacrificial layer to form a first opening between the initial first channel layer and the substrate includes: removing the initial first isolation layer on both sides of the substrate of the dummy gate structure to expose the sidewall surface of the first sacrificial layer; and removing the exposed first sacrificial layer to form a first opening between the initial first channel layer and the substrate.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Before etching the initial first isolation layer, the method further includes: forming a first protective layer on the surface of the initial first stacked structure, the surface of the dummy gate structure, and the surface of the initial first channel layer; and before etching the initial second stacked structure and the initial first channel layer using the dummy gate structure as a mask, the method further includes: removing the first protective layer.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first channel layer, the second sacrificial layer, and the second channel layer located on the second sacrificial layer, and before forming the first epitaxial doped region on the first isolation layer on both sides of the pseudo gate structure, the method further includes: forming an inner sidewall on the sidewall of the second sacrificial layer, wherein the outer surface of the inner sidewall is flush with the sidewall of the second channel layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, While forming an inner sidewall on the second sacrificial layer sidewall, the method also includes forming a second protective layer on the surface of the dummy gate structure, the surface of the second sacrificial layer, and the surface of the second channel layer, wherein the second protective layer exposes the surface of the first channel layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Before forming the second epitaxial doped region on the first interconnect layer, the method further includes: removing the second protective layer from the sidewall surface of the second channel layer.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first epitaxial doped region and the first interconnect layer located on the first epitaxial doped region, the method further includes: forming a third isolation layer on the first epitaxial doped region, the third isolation layer being located on the top surface and sidewall surface of the first interconnect layer, the third isolation layer electrically isolating the second epitaxial doped region and the first interconnect layer, and electrically isolating the gate structure and the first interconnect layer.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before removing the dummy gate structure and the second sacrificial layer, the method further includes: forming a fourth isolation layer located on the second epitaxial doped region, wherein the second connection layer is located within the fourth isolation layer, and the fourth isolation layer electrically isolates the gate structure and the second connection layer.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the second and third openings includes: removing the dummy gate structure to form a second opening between the first epitaxial doped regions, between the first interconnect layers, between the second epitaxial doped regions, and between the second interconnect layer, the second opening exposing the first channel layer, the second channel layer, and the second sacrificial layer; removing the second sacrificial layer to form a third opening between the first channel layer and the second channel layer.

22. The method for forming a semiconductor structure as described in claim 11, characterized in that, The substrate includes: a base and a bottom structure located on the base, the bottom structure extending in a direction parallel to the extension directions of the initial first stacked structure and the initial second stacked structure; the first isolation layer is located on the base and on the sidewall of the bottom structure.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The method for forming the substrate, bottom structure, initial first stacked structure, and initial second stacked structure includes: forming an initial substrate; forming a first stacked structure material layer on the initial substrate; forming a second stacked structure material layer on the first stacked structure material layer; forming a mask structure on the stacked material layer; etching the second stacked structure material layer, the first stacked material layer, and the initial substrate using the mask structure as a mask to form a substrate and a bottom structure located on the substrate; and forming an initial first stacked structure located on the bottom structure and an initial second stacked structure located on the initial first stacked structure.

24. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the first epitaxial doped region includes silicon and germanium; the material of the second epitaxial doped region includes silicon phosphide.

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