Super junction LDMOS device and method of manufacturing the same

Abstract

The present disclosure relates to the field of microelectronic technology. Specifically, the present disclosure provides a super junction LDMOS device, which comprises: a channel accumulation region formed in a portion of a channel adjacent to an N-type pillar region, a doping concentration of the channel accumulation region ranging from 5E17 / cm 3 to 5E18 / cm 3 , forming a passage for guiding surface electrons of the channel to flow to the substrate. When the channel surface forms an electron inversion layer, the channel accumulation region can form a very wide electron passage to guide the electrons to flow in the direction of the substrate, thus avoiding the situation that the peak electric field and the current path of the conventional device coincide when the gate is close to the edge of the drift region, thereby reducing the impact ionization intensity at static bias, and thus reducing the hot carrier injection effect. The super junction LDMOS device can also flatten the electric field strength of the pillar region by setting a field plate. In addition, the present disclosure also relates to a method for manufacturing the super junction LDMOS device.

Description

Technical Field

[0001] This disclosure relates to the field of microelectronics technology, and more specifically, to a superjunction LDMOS device and a method for manufacturing the superjunction LDMOS device. Background Technology

[0002] Lateral double-diffused MOS (LDMOS) devices are a key technology in high-voltage and power integrated circuits. They primarily achieve breakdown voltage sharing by forming a relatively long, lightly doped drift region (with the same doping type as the drain region) between the channel and drain regions. Superjunction LDMOS devices are an improved type of LDMOS device where the lightly doped drift region of the LDMOS structure is replaced by a set of alternating N-type and P-type pillars. Due to charge compensation between the N-type and P-type pillars, superjunction LDMOS devices can achieve very high breakdown voltages, while the highly doped N-type pillars achieve very low on-resistance.

[0003] In traditional superjunction LDMOS devices, the large current is concentrated in the N-type pillar region, while the current in the P-type pillar region is smaller, but the electric field strength is the same in both regions. Due to the uneven current distribution, the N-type pillar region, being in the area of ​​high current and strong electric field peaks, is more prone to hot carrier injection, leading to a decrease in device reliability.

[0004] Therefore, it is desirable to provide a superjunction LDMOS device that can suppress hot carrier injection. Summary of the Invention

[0005] According to a first aspect of this disclosure, a superjunction LDMOS device is provided, comprising: a P-type doped or undoped substrate; a P-type doped epitaxial layer covering one side surface of the substrate; a P-type doped body region formed in the epitaxial layer; a drift region formed in the epitaxial layer, the drift region comprising a P-type pillar region and an N-type pillar region, wherein at least the N-type pillar region is adjacent to the body region; an N-type doped source region formed in the body region, the source region being separated from the drift region by a portion of the body region, the portion of the body region located between the source region and the drift region forming a channel; an N-type doped drain region formed at one end of the drift region away from the body region; and a channel accumulation region formed in the region where the channel and the N-type pillar region are adjacent to each other, the doping concentration of the channel accumulation region being in the range of 5E17 / cm². 3 Up to 5E18 / cm 3 This forms a pathway that guides surface electrons from the channel to flow to the substrate; the gate faces the channel and the channel accumulation region.

[0006] According to some exemplary embodiments, in the direction from the source region to the drain region, the size of the channel accumulation region is 0.8 to 4 times the effective size of the channel, wherein the effective size of the channel refers to the size of the remaining portion of the channel after removing the channel accumulation region in the direction from the source region to the drain region.

[0007] According to some exemplary embodiments, the drift region includes a plurality of P-type pillar regions and a plurality of N-type pillar regions, each P-type pillar region and each N-type pillar region being adjacent to the body region, and the plurality of P-type pillar regions and the plurality of N-type pillar regions being arranged alternately along the extension direction of the channel.

[0008] According to some exemplary embodiments, the system further includes: a first field plate comprising a first portion and a second portion connected to each other via a connection portion, wherein the first portion faces the surface of the gate opposite to the channel, and the second portion comprises a plurality of sub-portions facing each of the plurality of N-type pillar regions; a plurality of second field plates facing each of the plurality of N-type pillar regions; and a metal layer connected to the first field plate, each of the plurality of second field plates, the source region, and the drain region via vias, and also connected to the substrate via deep vias.

[0009] According to some exemplary embodiments, in the direction from the source region to the drain region, the size of the first portion is larger than the size of the gate, in the extension direction of the channel, the size of the first portion is 1 to 2 times the size of the gate, and the orthogonal projection of the gate on the substrate falls within the range of the orthogonal projection of the first portion on the substrate.

[0010] According to some exemplary embodiments, each of the plurality of sub-parts is a rectangular plate, the size of which is 0.2 to 0.9 times the size of the N-type pillar region being faced in the extension direction of the channel, and the size of which is 0.05 to 0.6 times the size of the N-type pillar region being faced in the direction from the source region to the drain region, and the orthographic projection of each rectangular plate on the substrate falls within the range of the orthographic projection of the N-type pillar region being faced on the substrate.

[0011] According to some exemplary embodiments, all rectangular plates have the same dimensions in the direction from the source region to the drain region, and at least one rectangular plate has a different dimension in the extension direction of the channel than the other rectangular plates.

[0012] According to some exemplary embodiments, each of the plurality of second field plates is a rectangular plate, wherein the size of the rectangular plate in the direction from the source region to the drain region is 0.05 to 0.6 times the size of the facing N-type pillar region, the distance of the proximal end of the rectangular plate near the gate from the gate is 0.2 to 0.8 times the size of the facing N-type pillar region in the direction from the source region to the drain region, the width of the rectangular plate in the extension direction of the channel is 0.2 to 0.9 times the width of the facing N-type pillar region, and the orthographic projection of each rectangular plate on the substrate falls within the range of the orthographic projection of the facing N-type pillar region on the substrate.

[0013] According to some exemplary embodiments, the rectangular plates are of the same size, and the distance from the proximal end of at least one rectangular plate to the gate is different from the distance from the proximal end of the other rectangular plates to the gate.

[0014] According to some exemplary embodiments, the distance from each of the plurality of second field plates to the drift region is greater than the distance from the second portion of the first field plate to the drift region.

[0015] According to some exemplary embodiments, the system further includes an N-type doped buffer located between each of the plurality of P-type pillar regions and the drain region, wherein the doping concentration of the buffer is lower than that of the drain region.

[0016] According to some exemplary embodiments, the dimensions of the P-type column region are different from the dimensions of the N-type column region in the extension direction of the channel.

[0017] According to some exemplary embodiments, the drift region includes a plurality of P-shaped pillar regions and an N-shaped pillar region, one end of the N-shaped pillar region is adjacent to the body region and the other end is adjacent to the drain region, the plurality of P-shaped pillar regions are distributed in a scattered manner within the N-shaped pillar region, and each P-shaped pillar region is surrounded by the N-shaped pillar region.

[0018] According to some exemplary embodiments, it further includes: a field plate comprising a first portion and a second portion connected to each other by a connection portion, wherein the first portion faces the surface of the gate opposite to the channel, and the second portion faces the one N-type pillar region; a metal layer connected to the field plate, the source region, and the drain region respectively through vias, and also connected to the substrate through deep vias.

[0019] According to some exemplary embodiments, in the direction from the source region to the drain region, the size of the first portion is larger than the size of the gate, in the extension direction of the channel, the size of the first portion is 1 to 2 times the size of the gate, and the orthogonal projection of the gate on the substrate falls within the range of the orthogonal projection of the first portion on the substrate.

[0020] According to some exemplary embodiments, the orthographic projection of the second portion onto the substrate falls within the range of the orthographic projection of the N-type pillar region onto the substrate.

[0021] According to some exemplary embodiments, the second part includes a plurality of sub-parts, each of which faces the N-type column region at the adjoining point where the channel accumulation region is formed in the N-type column region.

[0022] According to some exemplary embodiments, each of the plurality of sub-parts is a rectangular plate.

[0023] According to some exemplary embodiments, it further includes an N-type doped buffer located between the one N-type pillar region and the drain region, wherein the doping concentration of the buffer is lower than the doping concentration of the drain region.

[0024] According to some exemplary embodiments, it also includes a body region contact region formed in the body region, the body region contact region being adjacent to the source region.

[0025] According to a second aspect of this disclosure, a method for manufacturing a superjunction LDMOS device according to a first aspect of this disclosure is provided, comprising: providing the substrate; forming the epitaxial layer on one side surface of the substrate; and forming the channel accumulation region in the epitaxial layer, wherein the doping energy of the channel accumulation region ranges from 10 kEV to 100 kEV, and the doping concentration ranges from 5E17 / cm². 3 Up to 5E18 / cm 3 The gate is formed based on the location of the channel accumulation region; the body region and the drift region are formed in the epitaxial layer based on the location of the gate; the source region is formed in the body region, and the drain region is formed in the drift region. Attached Figure Description

[0026] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so as to provide a fuller understanding of the further details, features, and advantages of this disclosure; in the accompanying drawings: Figure 1 The structure of a superjunction LDMOS device according to an exemplary embodiment of the present disclosure is schematically shown in cross-sectional view. Figure 2 Schematally shown in top view form Figure 1 The structure of the superjunction LDMOS device shown is in which the gate and field plate have been removed; Figure 3 Schematally shown in top view form Figure 1 The structure of the superjunction LDMOS device shown is illustrated, with the field plate shown. Figure 4 yes Figure 3 The sectional view obtained by cutting along line AA in the view; Figure 5 The structure of another superjunction LDMOS device according to an exemplary embodiment of the present disclosure is schematically shown in cross-sectional view. Figure 6 Schematally shown in top view form Figure 5 The structure of the superjunction LDMOS device shown is in which the gate and field plate have been removed; Figure 7 Schematally shown in top view form Figure 5 The structure of the superjunction LDMOS device shown is illustrated, with the field plate shown. Figure 8 yes Figure 7 The sectional view obtained by cutting along line BB in the view; Figure 9 A method for manufacturing a superjunction LDMOS device according to an exemplary embodiment of the present disclosure is illustrated schematically in the form of a flowchart.

[0027] It should be understood that the contents shown in the accompanying drawings are merely illustrative and therefore need not be drawn to scale. Furthermore, throughout all the accompanying drawings, identical or similar features are indicated by identical or similar reference numerals. Detailed Implementation

[0028] The following description provides specific details of various exemplary embodiments of the present disclosure so that those skilled in the art can fully understand and implement the technical solutions described according to the various exemplary embodiments of the present disclosure.

[0029] See Figures 1 to 4 Together they schematically illustrate the structure of a superjunction LDMOS device according to an exemplary embodiment of the present disclosure.

[0030] like Figure 1 As shown, the structure of the superjunction LDMOS device 100 along the first direction D1 includes, in sequence: a substrate 20, an epitaxial layer 21, various functional regions formed in the epitaxial layer 21, a gate oxide layer 23, a gate 22, a first field plate 211 and a second field plate 212, and a metal layer 214. In this disclosure, the first direction D1 refers to the direction perpendicular to the surface of the substrate 20 and upward, or in other words, the normal direction of the surface of the substrate 20.

[0031] The substrate 20 supports the entire film structure of the superjunction LDMOS device 100 and also provides a reference potential, such as a ground potential. The substrate 20 can be made of any suitable semiconductor material, including but not limited to bulk silicon substrates, silicon-on-insulator substrates, etc. This disclosure does not limit the material used to form the substrate. The substrate 20 can be p-type doped; however, it should be understood that in some exemplary embodiments of this disclosure, the substrate 20 can also be undoped.

[0032] The epitaxial layer 21 covers one side of the substrate 20, thereby allowing the formation of various functional regions of the superjunction LDMOS device 100 through doping in different regions of the epitaxial layer. The epitaxial layer 21 can be made of any suitable material, such as a silicon-germanium epitaxial layer. In the superjunction LDMOS device 100 of this disclosure, the epitaxial layer 21 is P-type doped.

[0033] The functional regions formed in the epitaxial layer 21 include the body region 28, the drift region 26, the body region contact region 29, the source region 24, the drain region 25, the drain region buffer zone 27, and the channel accumulation region 210.

[0034] Body region 28 is formed in epitaxial layer 21 through P-type doping; therefore, superjunction LDMOS device 100 is an N-type superjunction LDMOS device. Drift region 26 is also formed in epitaxial layer 21, adjacent to body region 28 and jointly covering epitaxial layer 21. In the first direction D1, the depth of body region 28 is greater than the depth of drift region 26. However, in some exemplary embodiments of this disclosure, the depth of body region 28 in the first direction D1 may be less than or equal to the depth of drift region 26. (See also...) Figure 2 The drift region 26 of the superjunction LDMOS device 100 includes a plurality of N-type pillar regions 26_1 and a plurality of P-type pillar regions 26_2. Each N-type pillar region 26_1 and each P-type pillar region 26_2 extends along a second direction D2 perpendicular to a first direction D1 and is adjacent to the body region 28. The plurality of N-type pillar regions 26_1 and the plurality of P-type pillar regions 26_2 are alternately arranged along a third direction D3 perpendicular to both the first direction D1 and the second direction D2. The width of each N-type pillar region 26_1 in the third direction D3 is the same, and the width of each P-type pillar region 26_2 in the third direction D3 is also the same, and the width of the N-type pillar region 26_1 is greater than the width of the P-type pillar region 26_2. However, according to some exemplary embodiments of the present disclosure, the width of the N-type pillar region 26_1 in the third direction D3 may also be less than or equal to the width of the P-type pillar region 26_2. It should be understood that in this disclosure, the second direction D2 refers to the direction from the source area 24 to the drain area 25, and the third direction D3 can refer to the direction of channel extension. The third direction D3 is perpendicular to the screen outwards and is therefore represented by circles and dots. If a direction is perpendicular to the screen inwards, it is represented by circles and crosses.

[0035] See also Figure 1 In body region 28, source region 24 is formed by N-type doping, and body contact region 29 is formed by P-type doping. Body contact region 29 is adjacent to source region 24, and both have approximately the same depth in the first direction D1. Source region 24 and drift region 26 are separated by a portion of body region 28; therefore, the portion of body region 28 between source region 24 and drift region 26 forms a channel. Figure 2 As shown, the body contact region 29, source region 24, and channel all extend along the third direction D3 over the entire size range of the superjunction LDMOS device 100. At the end of the drift region 26 furthest from the body region 28, a drain region 25 is formed by N-type doping. A buffer zone 27 with a lower N-type doping concentration than that of the drain region 25 can be formed between the drain region 25 and the drift region 28. Figure 2 As shown, the buffer 27 includes a first portion 27_1 located between the drain region 25 and the N-type pillar region 26_1, and a second portion 27_2 located between the drain region 25 and the P-type pillar region 26_2. However, according to some exemplary embodiments of this disclosure, the buffer 27 may not be formed between the drain region 25 and the drift region 28.

[0036] In the region adjacent to the channel and the N-type pillar region 26_1, a channel accumulation region 210 is formed by high-concentration N-type doping. The N-type doping concentration of the channel accumulation region 210 ranges from 5E17 / cm². 3 Up to 5E18 / cm 3 In the superjunction LDMOS device 100, for each N-type pillar region 26_1, there exists a corresponding channel accumulation region 210. The dimension of the channel accumulation region 210 in the third direction D3 is approximately the same as the width of the corresponding N-type pillar region 26_1. In the second direction D2, the dimension W2 of the channel accumulation region 210 can be 0.8 to 4 times the effective dimension W1 of the channel, where the effective dimension W1 refers to the dimension of the remaining portion of the channel after removing the channel accumulation region 210 in the second direction D2. Furthermore, in the first direction D1, the depth of the channel accumulation region 210 is less than the depth of the source region 24. Therefore, the channel accumulation region 210 forms a pathway guiding surface electrons from the channel to flow in the direction of the substrate 20 (i.e., along the direction opposite to the first direction D1). Therefore, when an electron inversion layer is formed on the channel surface, the channel accumulation region 210 can form a wide electron path to guide electrons to flow in the direction of the substrate 20 (or to flow into the device). Thus, the peak electric field and current path of the gate near the drift region edge of the conventional superjunction LDMOS device are avoided, thereby reducing the impact ionization intensity under static bias and thus reducing the hot carrier injection effect.

[0037] See also Figure 1 The superjunction LDMOS device 100 also includes a gate 22 facing the channel and the channel accumulation region 210, and the orthogonal projection of the gate 22 in the substrate 20 covers the orthogonal projection of the channel and the channel accumulation region 210 in the substrate 20. A gate oxide layer 23 is provided between the gate 23 and the channel and the channel accumulation region 210. As a non-limiting example, the gate oxide layer 23 may be formed of silicon dioxide.

[0038] The superjunction LDMOS device 100 also includes a first field plate 211 and multiple second field plates 212, which can make the electric field of the entire drift region flatter, thereby further increasing the doping concentration of the pillar region in order to improve the breakdown voltage.

[0039] See also Figure 3 and Figure 4 The first field plate 211 includes a first portion 211_1 facing the surface of the gate 22 away from the channel, a second portion facing a plurality of N-type pillar regions 26_1, and a connection portion connecting the first portion and the second portion. In the second direction D2, the width of the first portion 211_1 of the first field plate 211 is greater than the width of the gate 22, and in the third direction D3, the length of the first portion 211_1 of the first field plate 211 is greater than or equal to the length of the gate 22. As a non-limiting example, the length of the first portion 211_1 of the first field plate 211 can be 1 to 2 times the length of the gate 22. Therefore, in combination with... Figure 1 and Figure 3 As can be understood from the displayed content, the orthogonal projection of the gate 22 onto the substrate 20 falls within the range of the orthogonal projection of the first portion 211_1 of the first field plate 211 onto the substrate 20. The second portion of the first field plate 211 includes multiple sub-portions 211_2, each sub-portion 211_2 being opposite to an N-type pillar region 26_1 in the drift region 26. Figure 3 As shown, each sub-part 211_2 can be a rectangular plate, with each rectangular plate having approximately the same length in the second direction D2 and different widths in the third direction D3. However, it should be understood that the lengths of each rectangular plate in the second direction D2 can also be different, and / or the widths of each rectangular plate in the third direction D3 can also be the same. In some exemplary embodiments of this disclosure, the length of each rectangular plate can be 0.05 to 0.6 times the length of the facing N-type pillar region 26_1, and the width of each rectangular plate can be 0.2 to 0.9 times the width of the facing N-type pillar region 26_1. Therefore, the orthographic projection of each sub-part 211_2 onto the substrate 20 falls within the range of the orthographic projection of the opposing N-type pillar region 26_1 onto the substrate 20. It should be understood that the sub-part 211_2 can have any other suitable shape, such as an oblong shape, a semicircle, etc. Therefore, this disclosure does not impose any limitations on the size and shape of the sub-parts.

[0040] Multiple second field plates 212 face each of multiple N-type pillar regions 26_1 in the drift region 26, wherein each second field plate 212 is a rectangular plate. However, it should be understood that the second field plates 212 can have any other suitable shape, such as oblong, circular, elliptical, etc. In some exemplary embodiments of this disclosure, in the second direction D2, the length of each rectangular plate serving as the second field plate 212 can be 0.05 to 0.6 times the length of the facing N-type pillar region 26_1; the distance from the proximal end of each rectangular plate near the gate 22 to the gate 22 can be 0.2 to 0.8 times the length of the facing N-type pillar region 26_1; in the third direction D3, the width of each rectangular plate is 0.2 to 0.9 times the width of the facing N-type pillar region 26_1. Figure 3 In the illustrated scenario, the distances from the proximal ends of each second field plate 212 near the gate 22 to the gate 22 are different. However, in some exemplary embodiments of this disclosure, the distances from the proximal ends of each second field plate 212 near the gate 22 to the gate 22 may also be the same. Furthermore, on the third direction D3, each second field plate 212 is located approximately at the center of the facing N-type pillar region 26_1. Therefore, the orthographic projection of each second field plate 212 onto the substrate 20 falls within the range of the orthographic projection of the facing N-type pillar region 26_1 onto the substrate 20. Figure 1 As shown, in the first direction D1, the distance from each second field plate 212 to the drift region 26 is greater than the distance from the second portion of the first field plate 211 to the drift region 26. Furthermore, see... Figure 4 , it is Figure 3 The sectional view obtained by cutting along line AA in the view. For example... Figure 4 As shown, the distances of each second field plate 212 from the surface of the drift region 26 are approximately the same.

[0041] The superjunction LDMOS device 100 also includes a metal layer 214. For example... Figure 1 and Figure 3 As shown, the metal layer 214 is connected to the first field plate 211, each of the second field plates 212, the source region 24, the body contact region 29, and the drain region 25 through through-holes 213. Figure 3As shown, the metal layer 214 is connected to the source region 24 and the body region contact region 29 through a set of vias 213 formed at the junction of the source region 24 and the body region contact region 29. However, in some exemplary embodiments of this disclosure, the metal layer 214 can also be connected to the source region 24 and the body region contact region 29 through different vias respectively; that is, the metal layer 214 can be connected to the source region 24 through one or a set of vias, and simultaneously connected to the body region contact region 29 through another or another set of vias. Furthermore, the metal layer 214 is also connected to the substrate 20 through a deep via 215, thereby achieving grounding. It should be understood that, in this disclosure, the term "deep via" refers to a via connecting the metal layer to the substrate, the length of which along the first direction D1 is much greater than the length of the via 213.

[0042] In the superjunction LDMOS device 100 according to this disclosure, the first field plate 211 and the second field plate 212 not only assist in the depletion of the middle portion of each pillar region in the drift region 26, but also raise the peak value of the electric field in the middle portion of the pillar region, further balancing the electric field of the pillar region and making the electric field of the entire drift region flatter. This allows for a further increase in the doping concentration of the pillar region and an increase in the breakdown voltage. Furthermore, the first field plate 211 and the second field plate 212 are connected to the metal layer 214 via the via 213 to ground, which is equivalent to introducing an isolation layer between the drain and the gate, reducing the coupling between the drain and the gate and lowering parasitic capacitance. Therefore, the first field plate 211 and the second field plate 212, together with the P-type pillar region 26_2, assist in the depletion of the N-type pillar region 26_1 in the drift region 26, achieving overall charge balance and obtaining a flat electric field distribution in the drift region 26, thereby increasing the breakdown voltage and reducing the on-resistance (even by 12%), making it particularly suitable for high-voltage applications.

[0043] See Figures 5 to 8 Together, they schematically illustrate the structure of another superjunction LDMOS device according to exemplary embodiments of this disclosure. It should be understood that... Figures 5 to 8 The structure of the superjunction LDMOS device 200 shown in the figure is similar to Figures 1 to 4 The structure of the superjunction LDMOS device 100 shown is similar to that of the superjunction LDMOS device 200. The only difference is that in the superjunction LDMOS device 200, the multiple P-type pillar regions 26_2 in the drift region 26 are distributed in a scattered manner within an N-type pillar region 26_1, and each P-type pillar region 26_2 is surrounded by an N-type pillar region 26_1. In addition, the superjunction LDMOS device 200 does not have a second field plate 212. Therefore, the following description will only focus on the differences between the superjunction LDMOS device 200 and the superjunction LDMOS device 100, and the similarities between the two will not be repeated.

[0044] See Figure 5 See also Figures 6 to 8The drift region 26 of the superjunction LDMOS device 200 includes an N-type pillar region 26_1 and a plurality of P-type pillar regions 26_2, wherein the plurality of P-type pillar regions 26_2 are distributed in a scattered manner in an N-type pillar region 26_1 and are surrounded by it. Figure 8 yes Figure 7 The view is a sectional view obtained by cutting along line BB in the view, showing multiple P-type column areas 26_2 distributed in a scattered manner in an N-type column area 26_1 at the cutting position, wherein each P-type column area 26_2 is surrounded by an N-type column area 26_1. Figure 6 As shown, the orthographic projections of the plurality of P-type pillar regions 26_2 onto the substrate 20 each have a rectangular shape. However, in some exemplary embodiments of this disclosure, the orthographic projections of the plurality of P-type pillar regions 26_2 onto the substrate 20 may also have any other suitable shape, such as oblong, elliptical, etc., and this disclosure is not limited thereto. Furthermore, in the superjunction LDMOS device 200, the distribution of the plurality of P-type pillar regions 26_2 in an N-type pillar region 26_1 may take the following form: a larger number of P-type pillar regions 26_2 are arranged in a row along the second direction D2, and a smaller number of P-type pillar regions 26_2 are arranged in a row adjacent to it on the third direction D3. Since the P-type pillar regions 26_2 are farther from the channel in the row with a smaller number of P-type pillar regions 26_2, a channel accumulation region 210 may be correspondingly formed in the region where the channel and the N-type pillar regions 26_1 are adjacent to each other in the row including the smaller number of P-type pillar regions 26_2 arranged along the second direction D2. In this case, the superjunction LDMOS device 200 may have more than one channel accumulation region 210. Furthermore, in some other exemplary embodiments of this disclosure, only one channel accumulation region 210 may be formed in the portion of the channel adjacent to the N-type pillar region 26_1.

[0045] See Figure 5 See also Figure 7 The superjunction LDMOS device 200 only includes a first field plate 211. Similarly, the first field plate 211 includes a first portion 211_1 facing the surface of the gate 22 away from the channel, a second portion facing the N-type pillar region 26_1, and a connection portion connecting the first portion and the second portion. In the second direction D2, the width of the first portion 211_1 of the first field plate 211 is greater than the width of the gate 22, and in the third direction D3, the length of the first portion of the first field plate 211 is greater than or equal to the length of the gate 22. As a non-limiting example, the length of the first portion 211_1 of the first field plate 211 can be 1 to 2 times the length of the gate 22. Therefore, combined with... Figure 5 and Figure 7As can be understood from the displayed content, the orthographic projection of the gate 22 onto the substrate 20 falls within the range of the orthographic projection of the first portion 211_1 of the first field plate 211 onto the substrate 20. Similarly, the second portion of the first field plate 211 may include a plurality of sub-portions 211_2, each sub-portion 211_2 being located approximately corresponding to the corresponding channel accumulation region 210, opposite to an N-type pillar region 26_1 in the drift region 26. Figure 7 As shown, sub-parts 211_2 can be rectangular plates, each with a substantially the same length in the second direction D2, but different widths in the third direction D3. However, it should be understood that the lengths of the rectangular plates in the second direction D2 can also be different, and / or the widths of the rectangular plates in the third direction D3 can be the same. In some exemplary embodiments of this disclosure, the length of each rectangular plate in the second direction D2 can be 0.05 to 0.6 times the length of the N-type pillar region 26_1, and the width of each rectangular plate in the third direction D3 can be the width of the corresponding channel accumulation region 210. The orthographic projection of each sub-part 211_2 onto the substrate 20 falls within the range of the orthographic projection of the N-type pillar region 26_1 onto the substrate 20. It should be understood that sub-parts 211_2 can have any other suitable shape, such as an oblong shape, a semicircle, etc. Therefore, this disclosure does not impose any limitations on the size and shape of the sub-parts. Furthermore, it should be understood that, in the case of a single channel accumulation zone 210, the second part of the first field plate 211 can also correspond to the terrain as a separate part, such as a separate rectangular plate.

[0046] The superjunction LDMOS device 200 also includes a metal layer 214. For example... Figure 5 and Figure 7 As shown, the metal layer 214 is connected to the first field plate 211, the source region 24, the body region contact region 29, and the drain region 25 through vias 213. Furthermore, the metal layer 214 is also connected to the substrate 20 through a deep via 215 to achieve grounding.

[0047] Figures 5 to 8 The superjunction LDMOS device 200 shown in the figure does not have a second field plate. Instead, a P-type pillar region is formed at the corresponding position to assist the depletion of the N-type pillar region. As a result, a lower parasitic capacitance can be obtained, making it particularly suitable for low-voltage applications.

[0048] See Figure 9 The flowchart illustrates a method for manufacturing a superjunction LDMOS device according to this disclosure. Figure 9 As shown, method 300 includes steps 310, 320, 330, 340, 350, and 360.

[0049] In step 310, the substrate is provided; In step 320, the epitaxial layer is formed on one side surface of the substrate; In step 330, the channel accumulation region is formed in the epitaxial layer, wherein the doping energy of the channel accumulation region ranges from 10 kEV to 100 kEV, and the doping concentration ranges from 5E17 / cm. 3 Up to 5E18 / cm 3 ; In step 340, the gate is formed based on the location of the channel accumulation region; In step 350, based on the location of the gate, the body region and the drift region are formed in the epitaxial layer; and In step 360, a source region is formed in the body region and a drain region is formed in the drift region.

[0050] As described above, the substrate can be any suitable semiconductor material, including but not limited to bulk silicon substrates, silicon-on-insulator substrates, etc. The substrate can be p-type doped, but in some exemplary embodiments, it can also be undoped. A p-type doped epitaxial layer covers one side of the substrate, thereby allowing different functional regions of the superjunction LDMOS device to be formed in different regions of the epitaxial layer through different doping. Furthermore, it should be understood that in method 300 according to this disclosure, the channel accumulation region needs to be formed first because the spacing between the gate and the channel and the channel accumulation region is very small; if the gate is formed first, it will be difficult to form the channel accumulation region at the location opposite the gate. After the gate is formed, it is used to provide a reference location for self-alignment so that the body region, drift region, source region, and body contact region can be formed in subsequent steps.

[0051] The terminology used in this disclosure is for the purpose of describing the exemplary embodiments herein and is not intended to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and “including,” as used herein, refer to the presence of the mentioned feature but do not exclude the presence of one or more other features or the addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various features, these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0052] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It shall also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in this disclosure.

[0053] In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example that is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0054] It should be understood that the steps of the methods illustrated in the flowcharts or otherwise described herein are merely exemplary and do not imply that the steps of the illustrated or described methods must be performed in accordance with the shown or stated steps. Rather, the steps of the methods illustrated in the flowcharts or otherwise described herein may be performed in a different order than that shown in this disclosure, or may be performed simultaneously. Furthermore, the methods illustrated in the flowcharts or otherwise described herein may include additional steps as needed.

[0055] Although this disclosure has been described in detail with reference to some exemplary embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of this disclosure is defined only by the appended claims.

Claims

1. A superjunction LDMOS device, characterized in that, include: P-type doped or undoped substrates; A P-type doped epitaxial layer covering one side surface of the substrate; A P-type doped bulk region is formed in the epitaxial layer; A drift region is formed in the epitaxial layer, the drift region including a P-type pillar region and an N-type pillar region, wherein at least the N-type pillar region is adjacent to the body region; An N-type doped source region is formed in the body region, the source region and the drift region are separated by a portion of the body region, and the portion of the body region located between the source region and the drift region forms a channel; An N-type doped drain region is formed at one end of the drift region away from the body region; An N-type doped channel accumulation region is formed in the region adjacent to the channel and the N-type pillar region, wherein the doping concentration of the channel accumulation region ranges from 5E17 / cm². 3 Up to 5E18 / cm 3 This forms a pathway that guides the surface electrons of the channel to flow to the substrate; The gate facing the channel and the channel accumulation region.

2. The superjunction LDMOS device according to claim 1, characterized in that, In the direction from the source region to the drain region, the size of the channel accumulation region is 0.8 to 4 times the effective size of the channel, wherein the effective size of the channel refers to the size of the remaining portion of the channel after removing the channel accumulation region in the direction from the source region to the drain region.

3. The superjunction LDMOS device according to claim 1, characterized in that, The drift region includes multiple P-type pillar regions and multiple N-type pillar regions, each P-type pillar region and each N-type pillar region is adjacent to the body region, and the multiple P-type pillar regions and the multiple N-type pillar regions are arranged alternately along the extension direction of the channel.

4. The superjunction LDMOS device according to claim 3, characterized in that, Also includes: The first field plate includes a first part and a second part connected to each other by a connecting portion, wherein the first part faces the surface of the gate opposite to the channel, and the second part includes a plurality of sub-parts, each of which faces the plurality of N-type pillar regions. Multiple second field plates, each of which faces one of the multiple N-type column regions; and A metal layer is connected to the first field plate, each of the plurality of second field plates, the source region, and the drain region respectively through vias, and is also connected to the substrate through deep vias.

5. The superjunction LDMOS device according to claim 4, characterized in that, In the direction from the source region to the drain region, the size of the first portion is larger than the size of the gate. In the extension direction of the channel, the size of the first portion is 1 to 2 times the size of the gate, and the orthogonal projection of the gate onto the substrate falls within the range of the orthogonal projection of the first portion onto the substrate.

6. The superjunction LDMOS device according to claim 4, characterized in that, Each of the plurality of sub-parts is a rectangular plate, the size of which is 0.2 to 0.9 times the size of the N-type pillar region it faces in the direction of extension of the channel, and 0.05 to 0.6 times the size of the N-type pillar region it faces in the direction from the source region to the drain region, and the orthographic projection of each rectangular plate on the substrate falls within the range of the orthographic projection of the N-type pillar region it faces on the substrate.

7. The superjunction LDMOS device according to claim 6, characterized in that, All rectangular plates have the same dimensions in the direction from the source region to the drain region, and at least one rectangular plate has a different dimension in the extension direction of the channel than the other rectangular plates.

8. The superjunction LDMOS device according to claim 4, characterized in that, Each of the plurality of second field plates is a rectangular plate, wherein the size of the rectangular plate in the direction from the source region to the drain region is 0.05 to 0.6 times the size of the facing N-type pillar region, the distance from the gate near the proximal end of the rectangular plate to the gate is 0.2 to 0.8 times the size of the facing N-type pillar region in the direction from the source region to the drain region, the width of the rectangular plate in the extension direction of the channel is 0.2 to 0.9 times the width of the facing N-type pillar region, and the orthographic projection of each rectangular plate on the substrate falls within the range of the orthographic projection of the facing N-type pillar region on the substrate.

9. The superjunction LDMOS device according to claim 8, characterized in that, The rectangular plates are all the same size, and the distance from the proximal end of at least one rectangular plate to the gate is different from the distance from the proximal end of the other rectangular plates to the gate.

10. The superjunction LDMOS device according to claim 4, characterized in that, The distance from each of the plurality of second field plates to the drift region is greater than the distance from the second portion of the first field plate to the drift region.

11. The superjunction LDMOS device according to claim 3, characterized in that, It also includes an N-type doped buffer located between each of the plurality of P-type pillar regions and the drain region, wherein the doping concentration of the buffer is lower than that of the drain region.

12. The superjunction LDMOS device according to claim 3, characterized in that, In the direction of extension of the channel, the size of the P-type column area is different from the size of the N-type column area.

13. The superjunction LDMOS device according to claim 1, characterized in that, The drift region includes multiple P-type pillar regions and one N-type pillar region. One end of the N-type pillar region is adjacent to the body region, and the other end is adjacent to the drain region. The multiple P-type pillar regions are distributed in a scattered manner within the N-type pillar region, and each P-type pillar region is surrounded by the N-type pillar region.

14. The superjunction LDMOS device according to claim 13, characterized in that, Also includes: A field plate comprising a first portion and a second portion connected to each other by a connecting portion, wherein the first portion faces the surface of the gate opposite to the channel, and the second portion faces the one N-type pillar region; The metal layer is connected to the field plate, the source region, and the drain region through vias, and is also connected to the substrate through deep vias.

15. The superjunction LDMOS device according to claim 14, characterized in that, In the direction from the source region to the drain region, the size of the first portion is larger than the size of the gate. In the extension direction of the channel, the size of the first portion is 1 to 2 times the size of the gate, and the orthogonal projection of the gate onto the substrate falls within the range of the orthogonal projection of the first portion onto the substrate.

16. The superjunction LDMOS device according to claim 15, characterized in that, The orthographic projection of the second portion onto the substrate falls within the range of the orthographic projection of the N-type pillar region onto the substrate.

17. The superjunction LDMOS device according to claim 16, characterized in that, The second part includes a plurality of sub-parts, each of which faces the N-type column region at the adjoining point of forming the channel accumulation region in the N-type column region.

18. The superjunction LDMOS device according to claim 17, characterized in that, Each of the plurality of sub-parts is a rectangular plate.

19. The superjunction LDMOS device according to claim 13, characterized in that, It also includes an N-type doped buffer located between the N-type pillar region and the drain region, wherein the doping concentration of the buffer is lower than that of the drain region.

20. The superjunction LDMOS device according to claim 1, characterized in that, It also includes a body region contact region formed in the body region, the body region contact region being adjacent to the source region.

21. A method for manufacturing a superjunction LDMOS device according to claim 1, characterized in that, include: Provide the substrate; The epitaxial layer is formed on one side surface of the substrate; The channel accumulation region is formed in the epitaxial layer, wherein the doping energy of the channel accumulation region ranges from 10 kEV to 100 kEV, and the doping concentration ranges from 5E17 / cm. 3 Up to 5E18 / cm 3 ; The gate is formed based on the location of the channel accumulation region; Based on the location of the gate, the body region and the drift region are formed in the epitaxial layer; The source region is formed in the body region, and the drain region is formed in the drift region.

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