Method for manufacturing vertical chips

Abstract

The application relates to a vertical chip manufacturing method, which comprises the following steps: sequentially forming a buffer layer, a first doped gallium nitride layer, a multi-quantum well layer, a second doped gallium nitride layer and a metal bonding layer on a growth substrate; adhering a substrate substrate to the metal bonding layer, and stripping the growth substrate to expose the buffer layer; covering a layer of glue on the surface of the buffer layer; etching the buffer layer and the glue layer until the first doped gallium nitride layer is exposed, and removing the remaining glue layer; and manufacturing a metal layer on the first doped gallium nitride layer. The vertical chip manufacturing method utilizes the glue layer to buffer the etching of the buffer layer, so that the flatness of the surface of the first doped gallium nitride layer after the buffer layer is removed is ensured, and then the voltage of the vertical chip is stabilized, and the light output efficiency of the vertical chip is increased. Meanwhile, compared with the etching method for eliminating the buffer layer in the prior art, the elimination of the buffer layer is more rapid, and the production efficiency of the vertical chip can be further improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a method for manufacturing a vertical chip. Background Technology

[0002] In the manufacturing process of vertical chips, after the growth substrate is stripped, the exposed buffer layer is usually removed to expose the first gallium nitride (GaN) layer, so that a metal layer can be set on the first GaN layer.

[0003] However, due to factors such as lattice mismatch between the growth substrate and the buffer layer and poor crystal quality of the nucleation layer, the surface of the buffer layer becomes rough and has some deep holes after the growth substrate is peeled off. If the buffer layer is directly etched, it will affect the surface flatness of the first gallium nitride doped layer, thereby reducing the light extraction efficiency of the vertical chip and reducing the production efficiency of the vertical chip. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a method for manufacturing a vertical chip to increase the light extraction efficiency and production efficiency of the vertical chip, specifically including the following technical solution:

[0005] This application provides a method for manufacturing a vertical chip, including the following steps:

[0006] A buffer layer, a first gallium nitride doped layer, a multiple quantum well layer, a second gallium nitride doped layer, and a metal bonding layer are sequentially formed on the growth substrate.

[0007] The substrate is bonded to the metal bonding layer, and the growth substrate is peeled off to expose the buffer layer;

[0008] A layer of adhesive is applied to the surface of the buffer layer.

[0009] The buffer layer and adhesive layer are etched until the first doped gallium nitride layer is exposed, and the remaining adhesive layer is removed.

[0010] A metal layer is fabricated on the first gallium nitride doped layer.

[0011] The method for manufacturing a vertical chip in this application involves sequentially fabricating a buffer layer, a first gallium nitride doped layer, a multiple quantum well layer, a second gallium nitride doped layer, and a metal bonding layer on a growth substrate to form most of the structure of the vertical chip. This majority of the structure is then transferred to a substrate, and the substrate is bonded to the metal bonding layer. Simultaneously, the growth substrate is peeled off to expose the buffer layer structure, facilitating etching and removal of the buffer layer.

[0012] Because the buffer layer has a rough surface and the etching rates of the buffer layer and the first gallium nitride (GaN) doped layer are similar, directly etching away the buffer layer would result in the exposed surface roughness of the first GaN doped layer being similar to that of the buffer layer. By covering the surface of the buffer layer with an adhesive layer, the adhesive layer can buffer the etching of the buffer layer during the etching process. This buffering effect alleviates the impact of the rough surface of the buffer layer on the first GaN doped layer during etching, thereby allowing the first GaN doped layer to be relatively flat compared to the buffer layer.

[0013] Furthermore, the adhesive layer and buffer layer are etched until the first gallium nitride-doped layer is exposed, and the remaining adhesive layer is removed to facilitate the establishment of the metal layer. A metal layer is then fabricated on the first gallium nitride-doped layer to form a complete vertical chip structure.

[0014] In one embodiment, when covering the surface of the buffer layer with an adhesive layer, the following steps are included:

[0015] The substrate is kept at the first rotation speed while applying adhesive, so that the adhesive covers the buffer layer;

[0016] The substrate is kept at a second rotation speed to perform homogenization in order to form an adhesive layer. The second rotation speed is greater than the first rotation speed.

[0017] In this embodiment, the substrate is rotated at a first rotational speed to coat it with adhesive. This allows the adhesive, through its own fluidity and the combined effect of the first rotational speed, to extend from the substrate to and cover the buffer layer. Based on the premise that the first rotational speed covers the buffer layer with adhesive, a second rotational speed is used to homogenize the adhesive layer, thereby improving the surface smoothness of the adhesive layer and ensuring the surface smoothness of the first gallium nitride-doped layer at the end of etching. Simultaneously, by setting a second rotational speed greater than the first, the adhesive layer, combined with the greater centrifugal force provided by the second rotational speed and its own fluidity, can better ensure homogenization efficiency, thus ensuring the uniformity of the adhesive layer and improving surface smoothness.

[0018] In one embodiment, the first rotational speed is 30-60 rpm, and the second rotational speed is 1000-2000 rpm.

[0019] In one embodiment, before the substrate is kept at a second rotation speed for spin coating, the method further includes:

[0020] The substrate is kept at a third rotation speed for homogenization to eliminate the thickness difference between the center and edge regions of the adhesive layer. The third rotation speed is greater than the second rotation speed.

[0021] In this embodiment, before the adhesive layer is homogenized at the second rotation speed, a third rotation speed is set to eliminate the thickness difference between the center and edge regions of the adhesive layer. This ensures that the adhesive layer thickness at the edges is not excessive, thus preventing it from affecting the overall thickness and surface smoothness of the adhesive layer. Simultaneously, by setting a third rotation speed greater than the second, centrifugal force can be used more effectively to eliminate thicker adhesive layers at the edges, further ensuring the thickness and surface smoothness of the adhesive layer. This improves the surface smoothness of the first gallium nitride doped layer and increases the light extraction efficiency of the vertical chip.

[0022] In one embodiment, the third rotational speed is 3000 rpm and the duration is 2-5 seconds.

[0023] In one embodiment, when covering the surface of the buffer layer with an adhesive layer, the following steps are included:

[0024] A layer of adhesive is applied to the surface of the buffer layer, and the thickness of the adhesive layer is 1-4 μm greater than the thickness of the buffer layer.

[0025] In this embodiment, due to the surface roughness of the buffer layer, there is a certain error in the measurement of the buffer layer thickness, making it impossible to guarantee whether the adhesive layer set according to the measured buffer layer thickness fully covers the buffer layer. By setting the adhesive layer to be 1-4 μm higher than the buffer layer, it is possible to ensure that the adhesive layer fully covers the buffer layer, thereby enabling the adhesive layer to buffer the buffer layer during the etching process, thus reducing the surface roughness of the first gallium nitride doped layer.

[0026] In one embodiment, when a layer of adhesive is applied to the surface of the buffer layer, the method further includes:

[0027] A layer of adhesive is coated on the surface of the buffer layer and baked so that the ratio of the etching rate of the adhesive layer to the etching rate of the buffer layer is 0.9 to 1.1.

[0028] In this embodiment, the etching rate of the adhesive layer is altered by baking, ensuring that the ratio of the etching rate of the adhesive layer to that of the buffer layer is 0.9 to 1.1. This results in similar etching rates for the adhesive layer and the buffer layer during the etching process. Based on the premise of a smooth adhesive layer surface, by setting adhesive and buffer layers with similar etching rates, the surface of the first gallium nitride-doped layer can be ensured to be smooth at the end of etching, thereby improving the light extraction efficiency of the vertical chip and ensuring its voltage stability.

[0029] In one embodiment, the ratio of the etching rate of the adhesive layer to the etching rate of the buffer layer is 1.

[0030] In this embodiment, by setting the etching rate ratio of the adhesive layer and the buffer layer to 1, the etching rates are consistent when etching the adhesive layer and the buffer layer, thereby making the surface flatness of the finally exposed first gallium nitride layer consistent with the surface flatness of the adhesive layer.

[0031] In one embodiment, the photoresist used in the adhesive layer is model 567, and the corresponding baking temperature is 120-130°C.

[0032] In this embodiment, the etching rate of the photoresist is temperature-dependent, and the same temperature change does not affect the etching rate of different photoresists. By setting the photoresist type to 567 and its baking temperature to 120-130°C, the etching rate of the photoresist layer is reduced to a level similar to that of the buffer layer at the baking temperature of 120-130°C, thereby ensuring the etching effect.

[0033] In one embodiment, etching the buffer layer and the adhesive layer includes:

[0034] The buffer layer and adhesive layer are etched based on multiple preset time periods, with an interval time period between two adjacent preset time periods.

[0035] In this embodiment, by setting multiple preset time periods for etching the buffer layer and the adhesive layer, the etching time for each etching step can be shortened, reducing the heat generated during the etching process. Simultaneously, an interval time is set between two adjacent preset time periods, and this interval is used to cool the etching environment, preventing the adhesive layer from being carbonized by the high temperatures generated during the etching process, thus avoiding impact on the appearance yield.

[0036] In one embodiment, etching the buffer layer and the adhesive layer further includes:

[0037] Argon gas is used to cool the adhesive layer during intervals to prevent carbonization.

[0038] In this embodiment, argon gas is introduced during the interval to cool the adhesive layer, thereby accelerating the cooling effect during the interval and reducing the impact of the high temperature generated during etching on the adhesive layer, preventing carbonization of the adhesive layer and thus avoiding affecting the appearance yield of the vertical chip. Simultaneously, the introduction of inert argon gas does not interfere with the etching environment, nor does it cause the argon gas to react with the adhesive layer and buffer layer, thus preventing any impact on the etching process and etching effect.

[0039] In one embodiment, the argon gas flow rate is 150-250 sccm.

[0040] In one embodiment, etching the buffer layer and the adhesive layer includes:

[0041] The duration of each preset time period is equal.

[0042] In this embodiment, by setting preset time periods of equal duration, it is convenient to set etching parameters for each preset time period, thus simplifying the etching operation process. It also facilitates the adjustment of etching parameters.

[0043] In one embodiment, the total etching time is 25-45 minutes.

[0044] In one embodiment, the number of preset time periods can be 3 or 4.

[0045] In one embodiment, etching the buffer layer and the adhesive layer includes:

[0046] The buffer layer and adhesive layer are etched by introducing gas, which includes chlorine, boron trichloride, and helium.

[0047] In this embodiment, the buffer layer and adhesive layer are etched by introducing chlorine, boron trichloride, and helium. Chlorine and boron trichloride ionize to produce chloride ions, which react chemically with the adhesive and buffer layers, thereby etching them. Helium, as an inert gas, does not react with chlorine and boron trichloride, nor with the structure of the adhesive and buffer layers. Introducing helium reduces the high temperature generated during etching, thus preventing high-temperature carbonization of the adhesive layer and other adverse effects of high temperature on the chemical reaction process. Simultaneously, helium dilutes the reactant gases, increasing the uniformity of etching and preventing uneven distribution of reactant gases from causing the etching process to not occur simultaneously, further ensuring the surface flatness of the first doped gallium nitride layer.

[0048] In one embodiment, the chlorine gas flow rate is 50-90 sccm, the boron trichloride gas flow rate is 8-15 sccm, and the helium gas pressure is 2000 Pa.

[0049] In one embodiment, the cavity environment pressure is 0.3-0.5 Pa.

[0050] In this embodiment, the gas pressure affects the gas uniformity, with lower pressure resulting in better gas uniformity. By setting the chamber ambient pressure to 0.3-0.5 Pa, the etching process occurs in a low-pressure environment, thereby ensuring gas uniformity during the etching process.

[0051] In one embodiment, etching the buffer layer and the adhesive layer includes:

[0052] The upper power during the etching process is 250-300W, and the lower power is 100-150W.

[0053] In this embodiment, by setting an upper power of 250-300W and a lower power of 100-150W, chlorine gas and boron trichloride can ionize into chloride ions under the action of the upper power during the etching process, and the ionized chloride ions can meet the etching requirements; at the same time, the chloride ions can more effectively bombard the adhesive layer and buffer layer based on the acceleration of the lower power, thereby achieving the etching of the adhesive layer and buffer layer and ensuring the etching efficiency of the adhesive layer and buffer layer.

[0054] In one embodiment, etching the buffer layer and the adhesive layer includes:

[0055] Inductively coupled plasma etching was used to etch the buffer layer and the adhesive layer.

[0056] In this embodiment, the metal bonding layer is encapsulated by the adhesive layer, and the substrate does not chemically react with the gas used in inductively coupled plasma etching. By using inductively coupled plasma etching to etch the buffer layer and the adhesive layer, the structural integrity of the metal bonding layer and the substrate can be maintained while ensuring that the adhesive layer and the buffer layer are etched to expose the first doped gallium nitride layer. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of the vertical chip required to be fabricated according to the method of this application.

[0058] Figure 2 This is a schematic diagram of the process steps of the vertical chip manufacturing method of this application;

[0059] Figure 3 This is a schematic diagram of the chip structure formed after step S100 in the vertical chip manufacturing method of this application.

[0060] Figure 4 This is a schematic diagram of the structure formed during step S200 of the vertical chip manufacturing method of this application.

[0061] Figure 5 This is a schematic diagram of the structure formed after step S200 in the vertical chip manufacturing method of this application.

[0062] Figure 6 This is a schematic diagram of the structure formed after step S300 in the vertical chip manufacturing method of this application.

[0063] Figure 7 This is a schematic diagram of the structure formed in step S400 of the vertical chip manufacturing method of this application.

[0064] Figure 8 This is a schematic diagram of the structure formed after step S400 in the vertical chip manufacturing method of this application.

[0065] Figure 9 This is a schematic diagram of the structure formed after step S500 in the vertical chip manufacturing method of this application.

[0066] Figure 10 This is a schematic diagram of an undesirable structure shown in step S301 of the vertical chip manufacturing method of this application;

[0067] Figure 11This is a schematic diagram of another defective structure shown in step S301 of the vertical chip method of this application;

[0068] Figure 12 This is a schematic diagram of the structure formed after step S303 in the vertical chip manufacturing method of this application.

[0069] Figure 13 This is a schematic diagram of an undesirable structure shown in step S300a of the vertical chip manufacturing method of this application.

[0070] The attached figures are labeled as follows:

[0071] 100 - Vertical chip; 100a - Chip section structure; 10 - Growth substrate; 20 - Buffer layer; 30 - First doped gallium nitride layer; 40 - Multiple quantum well layer; 50 - Second doped gallium nitride layer; 61 - Metal layer; 62 - Metal bonding layer; 70 - Substrate; 80 - Adhesive layer. Detailed Implementation

[0072] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0073] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0074] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding disclosed function, operation, element, etc., and do not limit one or more other functions, operations, elements, etc. Moreover, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0076] Please see Figure 1 The diagram shows the structure of the vertical chip 100 of this application.

[0077] like Figure 1 As shown, the vertical chip 100 provided in this application includes a metal layer 61, a first gallium nitride (GaN) doped layer 30, a second GaN doped layer 50, and a metal bonding layer 62 stacked sequentially. The metal layer 61 is located on one side of the first GaN doped layer 30 and is opposite to the second GaN doped layer 50; the metal bonding layer 62 is located on one side of the second GaN doped layer 50 and is opposite to the first GaN doped layer 30. The metal layer 61 is electrically connected to the first GaN doped layer 30, and correspondingly, the metal bonding layer 62 is electrically connected to the second GaN doped layer 50.

[0078] Understandably, the metal layer 61 and the metal bonding layer 62 are located on both sides of the vertical chip 100 structure to facilitate connection to external circuits (not shown in the figure), thereby providing electrical signals to the first gallium nitride layer 30 and the second gallium nitride layer 50.

[0079] In one embodiment, the metal layer 61 is a pad.

[0080] The first gallium nitride (GaN) doped layer 30 provides holes or electrons to the vertical chip 100, and correspondingly, the second GaN doped layer 50 provides electrons or holes to the vertical chip 100. When current flows into the vertical chip 100 through the external circuit, causing the vertical chip 100 to be forward-biased, the current acting on the first GaN doped layer 30 causes the holes or electrons in the first GaN doped layer 30 to move towards the second GaN doped layer 50, and correspondingly, the current acting on the second GaN doped layer 50 causes the electrons or holes in the second GaN doped layer 50 to move towards the first GaN doped layer 30. At the same time, when the aforementioned holes and electrons meet and combine, they radiate light outward, thereby achieving the purpose of emitting light.

[0081] The vertical chip 100 also includes a multi-quantum-well layer 40, which is located between the first gallium nitride-doped layer 30 and the second gallium nitride-doped layer 50. The multi-quantum-well layer 40 carries holes or electrons emitted from the first gallium nitride-doped layer 30 and electrons or holes emitted from the second gallium nitride-doped layer 50. Simultaneously, the multi-quantum-well layer 40 increases the overlap rate of electrons and holes, improving the recombination luminescence efficiency of the vertical chip 100.

[0082] For ease of description, in this application specification, the first doped gallium nitride layer 30 is defined as an N-type gallium nitride layer, and the second doped gallium nitride layer 50 is defined as a P-type gallium nitride layer. Subsequent embodiments are based on this structure. It is understood that in some other embodiments, the first doped gallium nitride layer 30 may also be a P-type gallium nitride layer, and the second doped gallium nitride layer 50 may be an N-type gallium nitride layer, without departing from the fabrication steps defined by the method of this application.

[0083] Please see Figure 2 The diagram shows a workflow of the vertical chip 100 manufacturing method of this application.

[0084] The manufacturing method of the vertical chip 100 in this application specifically includes the following steps:

[0085] S100: A buffer layer 20, a first gallium nitride doped layer 30, a multiple quantum well layer 40, a second gallium nitride doped layer 50, and a metal bonding layer 62 are sequentially formed on the growth substrate 10.

[0086] For details, please refer to Figure 3 The diagram shows a portion of the structure formed during the manufacturing process of the vertical chip 100 of this application (hereinafter referred to as the chip portion structure 100a). In manufacturing the vertical chip 100 of this application, a buffer layer 20 is first formed on the growth substrate 10 to improve the quality of the subsequently grown first doped gallium nitride layer 30. Subsequently, the first doped gallium nitride layer 30, a multiple quantum well layer 40, a second doped gallium nitride layer 50, and a metal bonding layer 62 are formed sequentially, thereby forming the chip portion structure 100a of the vertical chip 100 of this application.

[0087] S200: The substrate 70 is bonded to the metal bonding layer 62, and the growth substrate 10 is peeled off to expose the buffer layer 20.

[0088] For details, please refer to Figure 4 The diagram shows a schematic of the transfer of the chip portion structure 100a to the substrate 70. The chip portion structure 100a is transferred to the substrate 70, that is, the substrate 70 is used to support and fix the chip portion structure 100a and to attach it to the metal bonding layer 62, so that the growth substrate 10 is located on the side of the chip portion structure 100a away from the substrate 70.

[0089] Please see Figure 5 The diagram shows the structure after the growth substrate 10 is removed. The buffer layer 20 is separated from the chip structure 100a by laser lift-off. During laser lift-off, due to lattice mismatch and poor nucleation layer crystal quality between the growth substrate 10 and the buffer layer 20, some of the buffer layer 20 is decomposed into gallium and nitrogen gas. This results in a relatively rough surface of the buffer layer 20 after the growth substrate 10 is removed, with numerous deep pores. The surface roughness of the buffer layer 20 is greater than Ra0.8.

[0090] based on Figure 1 As shown, the vertical chip 100 of this application requires the removal of the buffer layer 20 before fabricating the remaining structure on the first gallium nitride doped layer 30. Since the surface of the buffer layer 20 is relatively rough and contains a certain number of deep holes after the growth substrate 10 is removed in step S200, during the subsequent removal of the buffer layer 20, based on the similar or identical etching rates of the buffer layer 20 and the first gallium nitride doped layer 30, the surface of the first gallium nitride doped layer 30 will also be relatively rough and contain several deep holes after the buffer layer 20 is removed. That is, the rough surface of the buffer layer 20 will be transferred to the first gallium nitride doped layer 30. It is understandable that the rough surface of the first gallium nitride doped layer 30 will lead to a lower light extraction efficiency of the vertical chip 100 and cause voltage instability in the vertical chip 100.

[0091] S300: A layer of adhesive 80 is covered on the surface of the buffer layer 20;

[0092] For details, please refer to Figure 6The diagram shows a structure with adhesive layer 80. Adhesive layer 80 is applied to the surface of buffer layer 20, allowing it to cover the buffer layer 20. Adhesive layer 80 has relatively good flowability, allowing it to fill the rough surface of buffer layer 20. The surface flatness of adhesive layer 80 is controllable; under appropriate process parameters, the surface of adhesive layer 80 can be made relatively flat, with a surface roughness less than Ra0.1. This means that the outer surface of the chip structure 100a obtained after this step is relatively flat, eliminating the roughness caused by peeling off buffer layer 20, which is beneficial for subsequent processes.

[0093] S400: Etch buffer layer 20 and adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and remove the remaining adhesive layer 80;

[0094] For details, please refer to Figure 7 The diagram shows the structure of the etchant layer 80 and the buffer layer 20. In this step, the buffer layer 20 and the etchant layer 80 formed in step S300 are etched together until the first doped gallium nitride layer 30 is exposed. The surface of the etchant layer 80 obtained in step S300 is relatively flat, and the etchant layer 80 covers the buffer layer 20. Therefore, in the initial etching stage, the relatively flat etchant layer 80 is etched. The thickness of the etchant layer 80 gradually decreases as the etching process progresses until some areas of the etchant layer 80 are completely etched, thereby exposing part of the structure of the buffer layer 20.

[0095] It is understandable that the surface of the buffer layer 20 is relatively rough, resulting in inconsistent thicknesses in different areas. In step S300, due to the filling of the buffer layer 20 by the adhesive layer 80, when etching reaches a portion of the buffer layer 20's structure, some areas have already begun etching the buffer layer 20, while other areas are still being etched by the adhesive layer 80. Compared to the approach of directly etching the buffer layer 20 without the adhesive layer 80, the method of this application can utilize the etching of the buffer layer 20 by the adhesive layer 80 in this step to create a certain buffering effect. That is, compared to directly etching the rough surface of the buffer layer 20 and transferring the rough surface of the buffer layer 20 directly to the first gallium nitride doped layer 30, the method of this application, due to the filling of the buffer layer 20 by the adhesive layer 80, results in a relatively smooth surface of the first gallium nitride doped layer 30.

[0096] In this step, under the buffering effect of the adhesive layer 80, the etching completion times of the unevenly thick regions in the buffer layer 20 are relatively close, resulting in a relatively high surface flatness of the first gallium nitride doped layer 30. For example, the surface roughness of the first gallium nitride doped layer 30 can be less than Ra0.1. The relatively flat first gallium nitride doped layer 30 can improve the light extraction efficiency of the vertical chip 100 and stabilize the voltage of the vertical chip 100.

[0097] On the other hand, combining Figure 6 As shown, the side of the adhesive layer 80 furthest from the buffer layer 20 is directly bonded to the substrate 70. The adhesive layer 80 also covers and encapsulates the structure of the first gallium nitride doped layer 30, the multiple quantum well layer 40, the second gallium nitride doped layer 50, and the metal bonding layer 62. The adhesive layer 80 provides a certain degree of protection to the structure it covers. During the etching process, the adhesive layer 80 can protect this part of the structure from accidental etching, thus ensuring the integrity of the chip structure 100a.

[0098] After removing the remaining adhesive layer 80, as Figure 8 As shown, in the chip structure 100a, the metal bonding layer 62, the second gallium nitride layer 50, the multiple quantum well layer 40 and the first gallium nitride layer 30 are sequentially stacked on the substrate 70, so that the relatively flat surface of the first gallium nitride layer 30 formed in step S400 is exposed, which facilitates the subsequent process.

[0099] S500: A metal layer 61 is fabricated on the first gallium nitride doped layer 30.

[0100] For details, please refer to Figure 9 The diagram shows a structure with metal layer 61. Metal layer 61 is bonded to the first doped gallium nitride layer 30 to form a complete vertical chip 100 structure.

[0101] In existing technologies, a common approach to processing the buffer layer 20 involves pre-treating its rough surface to reduce its roughness, followed by etching until the first gallium nitride-doped layer 30 is exposed. However, because the surface of the buffer layer 20 contains a certain number of deep holes, pre-treatment alone cannot remove all of them, resulting in deep holes remaining on the surface of the first gallium nitride-doped layer 30, which affects the luminous efficiency of the vertical chip 100. Furthermore, the pre-treatment followed by etching method used in existing technologies requires a considerable amount of time to completely etch the surface of the buffer layer 20.

[0102] Therefore, compared with the pre-processing and etching method used in the prior art, the method for removing the buffer layer 20 in the manufacturing method of the vertical chip 100 of this application can better solve the problems of rough surface and deep holes of the buffer layer 20. Moreover, this method is relatively simple and takes relatively little time, and can remove the buffer layer 20 more effectively and quickly, while ensuring the flatness of the first gallium nitride doped layer 30, thereby improving the production efficiency of the vertical chip 100.

[0103] In one embodiment, step S300, "covering the surface of the buffer layer 20 with an adhesive layer 80", includes the following sub-steps:

[0104] S301. The substrate 70 is kept at a first rotation speed V1 to apply adhesive, so that the adhesive covers the buffer layer 20.

[0105] S303. The substrate 70 is kept at a second rotation speed V2 to perform homogenization to form an adhesive layer 80. The second rotation speed V2 is greater than the first rotation speed V1.

[0106] Specifically, when making the adhesive layer 80, the adhesive is pushed from the central area outwards, and a scraper can be used in conjunction with this process. Due to the fluidity of the adhesive itself, it can fill the rough surface of the buffer layer 20 during diffusion. Using a relatively small first rotation speed V1 in step 301 to control the diffusion of the adhesive allows it to flow fully, thereby creating a better filling effect on the rough surface of the buffer layer 20 and reducing air bubbles within the adhesive layer 80.

[0107] In one embodiment, the first rotational speed V1 can be set to 30-60 rpm. Please refer to the following reference. Figure 10 The schematic diagram shown in one embodiment illustrates the surface of the adhesive layer 80 based on a relatively small first rotation speed V1. It is understood that the adhesive material has adhesive properties and gradually evaporates its internal solvent over time, leading to surface hardening. When the first rotation speed V1 is too low, the adhesive material's diffusion rate decreases due to its adhesiveness, resulting in an increased time for the adhesive layer 80 to cover the buffer layer 20. This increased coating time may cause the adhesive layer 80 to harden, reducing its fluidity and surface adhesion. It is understood that during the process of coating the rough surface of the buffer layer 20 with the adhesive layer 80, some adhesive material that should be coated on the edge areas of the buffer layer 20 cannot contact and bond with the rough surface of the buffer layer 20 in the edge areas due to reduced fluidity and surface adhesion. This results in some edge areas of the buffer layer 20 not being covered by the adhesive layer 80. This leads to unevenness on the outer surface of the chip structure 100a in the edge areas. Furthermore, this affects the overall surface flatness of the first gallium nitride doped layer 30, reducing the light extraction efficiency of the vertical chip 100.

[0108] On the other hand, please refer to the following: Figure 11The diagram illustrates air bubbles inside the adhesive layer 80 based on a relatively large first rotational speed V1 in one embodiment. When the first rotational speed V1 is too large, the contact time between the adhesive layer 80 and the buffer layer 20 is reduced. Due to the fluidity and adhesion of the adhesive material, a large first rotational speed V1 results in insufficient flow of the adhesive material on the buffer layer 20, thus forming air bubbles between the adhesive material and the buffer layer 20. It is understandable that a larger first rotational speed V1 will lead to more air bubbles entering the adhesive layer 80 and / or between the adhesive layer 80 and the buffer layer, resulting in a large number of air bubbles in a portion of the area between the adhesive layer 80 and the buffer layer 20 and / or within the adhesive layer 80 after molding.

[0109] Since bubbles do not buffer the buffer layer 20, when etching areas where bubbles exist, the bubbles are not etched; instead, the adhesive layer 80 or buffer layer 20 beneath the bubbles is etched directly. That is, during the etching process, assuming the thickness of each region of the adhesive layer 80 is consistent, the region of the adhesive layer 80 containing bubbles is etched. The actual etching depth along the thickness direction of the adhesive layer 80 in this region is smaller than the actual etching depth along the thickness direction of the adhesive layer 80 in other regions of the adhesive layer 80 without bubbles. Because the total etching time for each region of the adhesive layer 80 remains constant, the etching time for the first gallium nitride layer 30 corresponding to the region of the adhesive layer 80 containing bubbles is increased, thereby reducing the thickness of the first gallium nitride layer 30 in this region and affecting the overall surface flatness of the first gallium nitride layer 30 after etching.

[0110] Therefore, selecting a first rotation speed V1 of 30-60 rpm ensures that the adhesive layer 80 better covers the entire surface of the buffer layer 20, while preventing the formation of a large number of air bubbles within the adhesive layer 80 and between the adhesive layer 80 and the buffer layer 20. Furthermore, this ensures the surface flatness of the first gallium nitride doped layer 30, improves the light extraction efficiency of the vertical chip 100, and guarantees voltage stability.

[0111] Because the adhesive material flows at the first rotational speed V1, its rotational speed is relatively slow, resulting in a relatively high surface roughness of the formed adhesive layer 80. Therefore, in step S302, by setting a relatively high second rotational speed V2 for homogenization, the surface of the adhesive material can be made smoother, and the surface roughness of the formed adhesive layer 80 is correspondingly reduced, where the surface roughness of the formed adhesive layer 80 can be less than Ra0.1. Subsequently, etching is performed on the adhesive layer 80 and the buffer layer 20 on the relatively low-roughness adhesive layer 80, resulting in a relatively smooth surface of the first gallium nitride-doped layer 30 (e.g., ...). Figure 12 (As shown).

[0112] In one embodiment, the second rotational speed V2 is 1000-2000 rpm.

[0113] In one embodiment, before step S303, "maintaining the substrate 70 at a second rotational speed V2 to perform homogenization to form the adhesive layer 80, wherein the second rotational speed V2 is greater than the first rotational speed V1", the following step is further included:

[0114] S302. The substrate 70 is kept at a third rotation speed V3 to perform homogenization, so as to eliminate the thickness difference between the center and edge regions of the adhesive layer 80. The third rotation speed V3 is greater than the second rotation speed V2.

[0115] Specifically, in the spin coating process, the adhesive flows from the center towards the edge, resulting in a possible thickness difference between the central and edge regions of the adhesive layer 80. In this step, by setting a relatively large third rotational speed V3 in the spin coating process, a greater centrifugal force can be applied to the adhesive. Understandably, the adhesive material relatively close to the buffer layer 20 in the edge region is relatively stable in position due to the holding effect of the buffer layer 20; while the portion of the adhesive material relatively far from the buffer layer 20 in the edge region (i.e., the adhesive material in a relatively thicker position) flows further towards the outside of the substrate 70 under the action of a greater centrifugal force, extending beyond the substrate 70 or detaching directly.

[0116] Therefore, in this step, by maintaining a relatively large third rotation speed V3 on the substrate 70 for homogenization, the defect of relatively thick edge areas of the adhesive material can be partially or completely eliminated, ensuring that the overall thickness of the adhesive layer 80 after molding is relatively uniform.

[0117] In one embodiment, the third rotational speed V3 is 3000 rpm and the duration is 2-5 seconds.

[0118] In one embodiment, step S300, "covering the surface of the buffer layer 20 with an adhesive layer 80", further includes the following method:

[0119] S300a, A layer of adhesive 80 is covered on the surface of the buffer layer 20, and the thickness of the adhesive layer 80 is 1-4 μm greater than the thickness of the buffer layer 20.

[0120] Specifically, the adhesive layer 80 is 1-4 μm thicker than the buffer layer 20. Due to the rough surface of the buffer layer 20, there is a certain measurement error when measuring its thickness. Therefore, the adhesive layer 80 needs to cover the buffer layer 20. This is understandable; please refer to [link / reference]. Figure 13 The diagram shows a defective surface of the adhesive layer 80 in one embodiment. If the thickness of the adhesive layer 80 is directly set using the measured thickness of the buffer layer 20, due to measurement errors, it cannot be guaranteed that the adhesive layer 80 will cover the buffer layer 20, and part of the structure of the buffer layer 20 may be exposed. Therefore, by setting the adhesive layer 80 to be higher than the buffer layer 20, it is possible to ensure that the adhesive layer 80 covers the buffer layer 20.

[0121] On the other hand, when the adhesive layer 80 is too thick, it will increase the amount of material in the adhesive layer 80, and at the same time increase the etching time and etching material, thereby increasing the manufacturing cost.

[0122] Therefore, ensuring that the adhesive layer 80 is 1-4 μm thicker than the buffer layer 20 can, on the one hand, ensure that the adhesive layer 80 covers the buffer layer 20, thereby enabling the adhesive layer 80 to buffer the buffer layer 20 during the etching process, thus reducing the surface roughness of the first gallium nitride layer 30; on the other hand, it can also save manufacturing costs to a certain extent.

[0123] In one embodiment, step S300, "covering the surface of the buffer layer 20 with an adhesive layer 80", further includes the following method:

[0124] S300b, A layer of adhesive 80 is covered on the surface of the buffer layer 20, and the adhesive layer 80 is baked so that the ratio of the etching rate of the adhesive layer 80 to the etching rate of the buffer layer 20 is 0.9 to 1.1.

[0125] Specifically, the etching rate of the adhesive layer 80 is altered by baking, so that the ratio of the etching rate of the adhesive layer 80 to the etching rate of the buffer layer 20 is 0.9 to 1.1, thereby ensuring that the etching rates of the adhesive layer 80 and the buffer layer 20 are similar during the etching process. Since some areas of the buffer layer 20 are etched while other areas of the adhesive layer 80 are etched during the etching process, the height difference between the two areas can be reduced by ensuring that the etching rates of the adhesive layer 80 and the buffer layer 20 are similar, further improving the surface flatness of the first gallium nitride doped layer 30.

[0126] It is understandable that the buffering effect of the adhesive layer 80 on the buffer layer 20 is related to the etching rate of the adhesive layer 80. When the ratio of the etching rate of the adhesive layer 80 to the etching rate of the buffer layer 20 is too large, that is, when the etching rate of the adhesive layer 80 is greater than the etching rate of the buffer layer 20, the buffering effect of the adhesive layer 80 on the buffer layer 20 decreases as the etching rate of the adhesive layer 80 increases.

[0127] Correspondingly, when the etching rate of the adhesive layer 80 is less than the etching rate of the buffer layer 20, the buffering effect of the adhesive layer 80 on the buffer layer 20 increases as the etching rate of the adhesive layer 80 decreases. However, an excessively large buffering effect may lead to a situation where the buffer layer 20 is etched in one area while the adhesive layer 80 is still being etched in another area. In this case, the area where the buffer layer 20 is etched will have already been etched, but the area where the adhesive layer 80 is etched will not have been etched to the buffer layer 20, thus affecting the surface flatness of the final first doped gallium nitride layer 30.

[0128] Since the etching rate of the adhesive layer 80 is greater than that of the buffer layer 20, the etching rate of the adhesive layer 80 is reduced by baking it, so that the etching rate of the adhesive layer 80 is similar to that of the buffer layer 20. This allows the adhesive layer 80 to provide a good buffering effect on the buffer layer 20. Based on the flatness of the adhesive layer 80 surface, the surface flatness of the first gallium nitride doped layer 30 can be further optimized, thereby improving the light extraction efficiency of the vertical chip 100 and ensuring the voltage stability of the vertical chip 100.

[0129] In one embodiment, the ratio of the etching rate of the adhesive layer 80 to the etching rate of the buffer layer 20 is 1. That is, the etching rate of the adhesive layer 80 and the etching rate of the buffer layer 20 are the same. Under the premise of the flatness of the adhesive layer 80, the surface of the adhesive layer 80 can be directly transferred to the surface of the first gallium nitride doped layer 30. Since the surface flatness of the adhesive layer 80 is controllable, the surface flatness of the first gallium nitride doped layer 30 is indirectly controllable. Furthermore, the light extraction efficiency of the vertical chip 100 can be higher and the voltage more stable.

[0130] In one embodiment, the photoresist used in the adhesive layer 80 is type 567, and the corresponding baking temperature is 120-130°C. Since the etching rate of the photoresist is temperature-dependent, and the same temperature change results in different etching rates for different photoresists, setting the photoresist type to 567 and its baking temperature to 120-130°C ensures that the etching rate of the adhesive layer 80 decreases to a level similar to that of the buffer layer 20 at this baking temperature. This results in a smooth surface for the first gallium nitride doped layer 30, thereby improving the light extraction efficiency of the vertical chip 100 and ensuring the voltage stability of the vertical chip 100.

[0131] In one embodiment, step S400, "etching the buffer layer 20 and the adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and removing the remaining adhesive layer 80," includes the following:

[0132] S400a: The buffer layer 20 and the adhesive layer 80 are etched based on multiple preset time periods T1, with an interval time period T2 between two adjacent preset time periods T1, until the first doped gallium nitride layer 30 is exposed, and the remaining adhesive layer 80 is removed.

[0133] Specifically, heat is generated during the etching process, and this heat accumulates as the etching time increases. When the temperature in the etching environment reaches a certain value, the adhesive layer 80 will carbonize. The carbonized adhesive layer 80 will affect the appearance yield of the chip structure 100a, and thus affect the appearance yield of the final vertical chip 100.

[0134] Therefore, designing multiple preset time periods T1 to etch the buffer layer 20 and the adhesive layer 80 can reduce the heat generated during the etching process. At the same time, setting an interval time period T2 between two adjacent preset time periods T1 and using this interval time to cool the etching environment can reduce the heat accumulation in each preset time period T1, avoid the high-temperature carbonization of the adhesive layer 80 generated during the etching process, and thus avoid affecting the appearance yield of the vertical chip 100.

[0135] In one embodiment, step S400, "etching the buffer layer 20 and the adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and removing the remaining adhesive layer 80", further includes the following:

[0136] S400b: Based on multiple preset time periods T1, the buffer layer 20 and the adhesive layer 80 are etched, and an interval time period T2 is left between two adjacent preset time periods T1. Argon gas is used to cool the adhesive layer 80 during the interval time period T2 to prevent the adhesive layer 80 from carbonizing until the first doped gallium nitride layer 30 is exposed, and the remaining adhesive layer 80 is removed.

[0137] Specifically, if natural cooling is used during interval T2, it will increase the time cost required for etching. By introducing argon gas during interval T2, the temperature of the adhesive layer 80 can be better reduced, thus reducing the impact of the high temperature generated during etching on the adhesive layer 80 and preventing carbonization of the adhesive layer 80, which would affect the appearance yield of the vertical chip 100. At the same time, the duration of interval T2 can be reduced, shortening the overall etching time.

[0138] As is understandable, argon is an inert gas. Under the etching conditions provided by the manufacturing method of the vertical chip 100 in this application, it will not react with the substances involved in the etching process in the etching environment, nor will it react with the adhesive layer 80, the buffer layer 20, and the structure of the remaining chip structure 100a, thereby ensuring the etching process and etching effect.

[0139] In one embodiment, the argon gas flow rate is 150-250 sccm.

[0140] In one embodiment, step S400, "etching the buffer layer 20 and the adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and removing the remaining adhesive layer 80", further includes the following:

[0141] S400c, based on multiple preset time periods T1, the buffer layer 20 and the adhesive layer 80 are etched, and an interval time period T2 is left between two adjacent preset time periods T1. The duration of each preset time period T1 is equal until the first doped gallium nitride layer 30 is exposed, and the remaining adhesive layer 80 is removed.

[0142] Specifically, setting a preset time period T1 of equal duration facilitates the setting of etching parameters within each preset time period T1, simplifying the etching operation process. It also facilitates the adjustment of etching parameters.

[0143] In one embodiment, the total etching time is 25-45 minutes. During the etching process, it is necessary to ensure complete etching of the buffer layer 20. It is understood that if the total etching time is too short, the buffer layer 20 and / or adhesive layer 80 will remain on the outer surface of the chip structure 100a, resulting in the first gallium nitride layer 30 not being exposed or only partially exposed, thus leading to poor etching effect. Since the etching rate of the first gallium nitride layer 30 is similar to that of the buffer layer 20, if the total etching time is too long, the first gallium nitride layer 30 will be etched, even to the multi-quantum well layer 40 or the remaining structure of the chip structure 100a, destroying the structural integrity of the vertical chip 100.

[0144] Therefore, the total etching time is set at 25-45 minutes. This ensures the removal of the buffer layer 20 and also ensures that the etching process can reach the maximum boundary that allows the first doped gallium nitride layer 30 to be etched at the end of the etching process.

[0145] In one embodiment, the number of preset time periods T1 can be 3 or 4. Given that the duration of each preset time period T1 is equal, it is understandable that setting too many preset time periods T1 would increase the number of operation steps, making the operation more cumbersome; setting too few preset time periods T1 would result in an excessively long duration for each individual preset time period T1, leading to excessive heat accumulation and excessively high temperatures within each preset time period T1. This could potentially cause the adhesive layer 80 to carbonize before the preset time period T1 ends, affecting the appearance yield of the vertical chip 100. Selecting 3 or 4 preset time periods T1 can avoid the above-mentioned situations.

[0146] In one embodiment, step S400, "etching the buffer layer 20 and the adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and removing the remaining adhesive layer 80", further includes the following:

[0147] S400d, the buffer layer 20 and the adhesive layer 80 are etched by introducing gas until the first doped gallium nitride layer 30 is exposed, and the remaining adhesive layer 80 is removed. The gas includes chlorine, boron trichloride and helium.

[0148] Specifically, chlorine and boron trichloride ionize to produce chloride ions, which then react chemically with the adhesive layer 80 and the buffer layer 20, thereby etching the buffer layer 20 and the adhesive layer 80. Understandably, helium, as an inert gas, does not react with chlorine and boron trichloride, nor with the adhesive layer 80, the buffer layer 20, or the remaining chip structure 100a. Helium reduces the high temperatures generated during etching, thus preventing high-temperature carbonization of the adhesive layer 80. Simultaneously, since high temperatures can affect the chemical reaction process to some extent, helium also prevents other adverse effects of high temperatures on the chemical reaction process.

[0149] On the other hand, helium can dilute the reactive gas, thereby increasing the uniformity of etching and avoiding the inability of the etching process to occur simultaneously due to uneven distribution of reactive gas, thus further ensuring the surface flatness of the first doped gallium nitride layer 30.

[0150] In one embodiment, the chlorine gas flow rate is 50-90 sccm, the boron trichloride gas flow rate is 8-15 sccm, and the helium gas pressure is 2000 Pa.

[0151] In one embodiment, the cavity environment pressure is 0.3-0.5 Pa. Since the cavity environment pressure can affect the gas uniformity, and the lower the cavity environment pressure, the better the gas uniformity, setting a low-pressure environment of 0.3-0.5 Pa can ensure the gas uniformity during the etching process.

[0152] In one embodiment, step S400, "etching the buffer layer 20 and the adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and removing the remaining adhesive layer 80," further includes the following method:

[0153] S400e, etching buffer layer 20 and adhesive layer 80 until the first doped gallium nitride layer 30 is exposed, and the remaining adhesive layer 80 is removed, wherein the upper power during the etching process is 250-300W and the lower power is 100-150W.

[0154] Specifically, higher up-power can increase the flux of ionized ions and increase the etching rate, but excessively high up-power can lead to decreased etching uniformity and increased heat generation. During the etching process, given that the etching gases are chlorine and boron trichloride, the chloride ions ionized from chlorine and boron trichloride under an up-power of 250-300W can meet the etching requirements of this application.

[0155] Understandably, higher downpower would increase the rate at which ions bombard the adhesive layer 80 and buffer layer 20, thereby increasing the energy of the ions and thus the etching rate. However, excessively high downpower would increase damage to the substrate 70. Therefore, chloride ions accelerated at a downpower of 100-150W can more effectively bombard the adhesive layer 80 and buffer layer 20, thereby achieving etching of the adhesive layer 80 and buffer layer 20 and ensuring etching efficiency.

[0156] In one embodiment, inductively coupled plasma etching (ICP-E) is used to etch the buffer layer 20 and the adhesive layer 80. Specifically, based on the structure of the adhesive layer 80 covering and encapsulating the first gallium nitride (GaN) layer 30, the multiple quantum well layer 40, the second GaN layer 50, and the metal bonding layer 62, the etching gas used in ICP-E etching of the buffer layer 20 and the adhesive layer 80 cannot directly etch the structure encapsulated by the adhesive layer 80, especially the metal bonding layer 62, which is most likely to react with the etching gas. Simultaneously, since the substrate 70 does not react with the gas used in ICP-E etching, etching the buffer layer 20 and the adhesive layer 80 with ICP-E can ensure the structural integrity of the chip portion structure 100a while ensuring that the adhesive layer 80 and the buffer layer 20 are etched to expose the first GaN layer 30, thereby ensuring the structural integrity of the entire vertical chip 100.

[0157] It should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0158] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0159] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this invention, still falls within the scope of this invention.

Claims

1. A method for manufacturing a vertical chip, characterized in that, Includes the following steps: A buffer layer, a first gallium nitride doped layer, a multiple quantum well layer, a second gallium nitride doped layer, and a metal bonding layer are sequentially formed on the growth substrate. The substrate is attached to the metal bonding layer, and the growth substrate is peeled off to expose the buffer layer; A layer of adhesive is coated on the surface of the buffer layer and baked so that the etching rate of the adhesive layer is 0.9 to 1.1 compared with the etching rate of the buffer layer. The substrate is coated with adhesive at a first rotation speed of 30-60 rpm to cover the buffer layer. The substrate is then uniformly coated with adhesive at a second rotation speed of 1000-2000 rpm to form the adhesive layer. The buffer layer and the adhesive layer are etched until the first doped gallium nitride layer is exposed, and the remaining adhesive layer is removed. A metal layer is fabricated on the first gallium nitride doped layer.

2. The method for manufacturing a vertical chip according to claim 1, characterized in that, Before maintaining the substrate at the second rotation speed for spin coating, the process further includes: The substrate is kept at a third rotation speed for homogenization to eliminate the thickness difference between the center and edge regions of the adhesive layer. The third rotation speed is greater than the second rotation speed.

3. The method for manufacturing a vertical chip according to claim 1, characterized in that, When covering the surface of the buffer layer with an adhesive layer, the following is included: A layer of adhesive is applied to the surface of the buffer layer, and the thickness of the adhesive layer is 1-4 μm greater than the thickness of the buffer layer.

4. The method for manufacturing a vertical chip according to any one of claims 1-3, characterized in that, The etching of the buffer layer and the adhesive layer includes: The buffer layer and the adhesive layer are etched based on multiple preset time periods, with an interval between two adjacent preset time periods.

5. The method for manufacturing a vertical chip according to claim 4, characterized in that, The etching process further includes: Argon gas is used to cool the adhesive layer during the interval period to prevent the adhesive layer from carbonizing.

6. The method for manufacturing a vertical chip according to claim 4, characterized in that, The etching of the buffer layer and the adhesive layer includes: The duration of each of the preset time periods is equal.

7. The method for manufacturing a vertical chip according to any one of claims 1-3, characterized in that, The etching of the buffer layer and the adhesive layer includes: The buffer layer and the adhesive layer are etched by introducing a gas, wherein the gas includes chlorine, boron trichloride, and helium.

8. The method for manufacturing a vertical chip according to any one of claims 1-3, characterized in that, The etching of the buffer layer and the adhesive layer includes: The upper power during the etching process is 250-300W, and the lower power is 100-150W.

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