Micro LED chip and manufacturing method thereof

Abstract

This invention provides a micro LED chip and its fabrication method. The fabrication method of the micro LED chip provided in this application, on the one hand, involves preparing an ITO composite layer with different etching rates on an epitaxial structure by controlling growth conditions. The ITO composite layer includes stacked ITO conductive layers and ITO masking layers. The ITO composite layer is etched to form a suspended structure, such that the lateral etching depth of the ITO masking layer is greater than that of the ITO conductive layer. By controlling the lateral etching depth of the ITO masking layer, the ITO conductive layer is not affected by photoresist adhesion, allowing the lateral etching depth of the ITO conductive layer to reach a preset length. After etching, the inclined sidewall has a certain distance from the ITO conductive layer, avoiding leakage problems caused by overlap. On the other hand, the MESA / ITO process is combined with photolithography, avoiding the problem of different areas being easily misaligned during separate processes, requiring a large over-etching amount, resulting in loss of the light-emitting area and affecting the brightness of the micro LED chip. This simplifies the process, increases yield, reduces costs, and improves brightness.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and more specifically, relates to a micro LED chip and its manufacturing method. Background Technology

[0002] In the current fabrication process of LED chips, the commonly used process consists of four photolithography steps: MESA, ITO, PAD, and PV. These include the Mesa step (a dry etching process to create the exposed N-type layer on the epitaxial wafer surface), the ITO step (the transparent conductive film patterning process), the Pad step (the electrode patterning process), and the PV step (the passivation layer patterning process).

[0003] However, these methods for fabricating LED chips are complex and costly. On the other hand, the MESA and ITO processes are performed separately on the micro LED chip. Due to the inability to release the high-temperature growth stress during epitaxy, the epitaxial edges warp, and the photomask cannot be parallel and aligned with the substrate. This causes misalignment in different areas, requiring a large amount of over-etching, resulting in loss of the light-emitting area and affecting the brightness of the LED chip. However, if the MESA / ITO processes are combined, the existing coating process often uses a constant coating rate, constant coating temperature, and constant oxygen flow to prepare ITO films on the epitaxial layer. The etching rate difference of the ITO film is small. After the MESA / ITO processes are combined, the ITO film is first wet-etched using photoresist as a mask. Due to the adhesion between the ITO film and the photoresist, the lateral etching of the ITO film cannot reach the budgeted size, resulting in insufficient clearance. After etching, the MESA and ITO edges are prone to overlap, causing leakage. Summary of the Invention

[0004] In view of this, the present invention provides a micro LED chip and its fabrication method to solve the problem that in the prior art, the MESA process and the ITO process are performed separately on the micro LED chip. Due to the warping of the epitaxial edge, different areas are prone to misalignment, which requires a large amount of over-etching, resulting in the loss of the light-emitting area and affecting the brightness of the LED chip. However, if the MESA / ITO process is combined, the etching rate difference of the ITO thin film prepared by the existing coating process is small, and after etching, the MESA and ITO are prone to overlap, causing leakage.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for fabricating a micro LED chip, comprising:

[0007] Step S100: Provide a substrate;

[0008] Step S200: An epitaxial structure is grown on one side surface of the substrate. The epitaxial structure includes, in sequence along the growth direction, a stacked N-type semiconductor layer, an active region, and a P-type semiconductor layer.

[0009] Step S300: An ITO composite layer is prepared on the upper surface of the epitaxial structure. The ITO composite layer includes a stacked ITO conductive layer and an ITO masking layer along the growth direction, and the etching rate of the ITO masking layer is greater than the etching rate of the ITO conductive layer.

[0010] Step S300 specifically includes the following procedures:

[0011] Step S301: Set the vacuum level inside the reaction chamber, adopt the first coating temperature and the first coating rate, and introduce the first oxygen flow rate to grow the ITO conductive layer;

[0012] Step S302: Maintain the vacuum inside the reaction chamber, stop the oxygen supply, lower the temperature to the second coating temperature, and increase the coating rate to the second coating rate to grow the ITO masking layer.

[0013] Step S400: Prepare a MESA / ITO lithographic pattern on a portion of the upper surface of the ITO composite layer, and etch the ITO composite layer to form a suspended structure, so that the lateral etching depth of the ITO masking layer is greater than the lateral etching depth of the ITO conductive layer, soften the MESA / ITO lithographic pattern, so that it has a structure that is narrow at the top and wide at the bottom and covers the exposed surface of the etched ITO composite layer and a portion of the surface of the P-type semiconductor layer.

[0014] Step S500: Using the MESA / ITO lithography pattern as a mask, N-type mesa and P-type mesa are formed simultaneously through a single dry etching process, and the ITO conductive layer is exposed. The etching surface between the P-type mesa and the N-type mesa is an inclined sidewall.

[0015] Step S600: Alloy the ITO conductive layer using the RTA process to form a good ohmic contact between it and the P-type semiconductor layer;

[0016] Step S700: An N-type electrode and a P-type electrode are formed on the N-type region mesa and the upper surface of the ITO conductive layer, respectively;

[0017] Step S800: Deposit an insulating protective layer over the entire surface, and form N-type pad openings and P-type pad openings at the positions corresponding to the N-type electrode and P-type electrode, respectively. The insulating protective layer covers the exposed surface of the ITO conductive layer and the epitaxial structure.

[0018] Preferably, in step S300, the etching selectivity ratio of the ITO masking layer to the ITO conductive layer is in the range of 10:1 to 100:1.

[0019] Preferably, in step S301, the vacuum level inside the reaction chamber is in the range of 1.0 × 10⁻⁶. -5 Torr-1.0×10 -4 Torr, excluding endpoint values; the first coating temperature ranges from 200°C to 350°C, including endpoint values; the first coating rate ranges from 0.5 Å / s to 1.5 Å / s, including endpoint values; the first oxygen flow rate ranges from 5 sccm to 30 sccm, including endpoint values.

[0020] In step S302, the second coating temperature ranges from 20°C to 100°C, including the endpoint values; the second coating rate ranges from 2.5 Å / s to 5 Å / s, including the endpoint values.

[0021] Preferably, step S400 specifically includes the following steps:

[0022] Step S401: Deposit a full layer of photoresist on the upper surface of the ITO composite layer, and pattern the photoresist to form a MESA / ITO photolithography pattern. The edge position of the contact surface between the MESA / ITO photolithography pattern and the ITO composite layer is the first end.

[0023] Step S402: The ITO composite layer is etched in one step using a wet etching process to form a suspended structure and expose part of the P-type semiconductor layer;

[0024] Specifically, ITO etching solution is used to etch along the exposed ITO composite layer and to etch the sidewalls of the ITO composite layer laterally, so that the peripheral area of ​​the MESA / ITO lithographic pattern and the contact surface of the ITO composite layer is suspended to form a suspended structure.

[0025] Step S403: Soften the MESA / ITO photolithography pattern by heating so that it has a narrow top and wide bottom structure and covers the exposed surface of the etched ITO composite layer and part of the surface of the P-type semiconductor layer. The edge of the contact surface between the MESA / ITO photolithography pattern and the P-type semiconductor layer is the second end.

[0026] Wherein, the lateral etching depth of the ITO masking layer is the horizontal distance between the edge of the etched ITO masking layer and the first end; the lateral etching depth of the ITO conductive layer is the horizontal distance between the edge of the etched ITO conductive layer and the first end.

[0027] Preferably, the horizontal distance between the edge of the etched ITO masking layer and the first end is equal to the horizontal distance between the edge of the etched ITO masking layer and the second end, and both are the first preset length;

[0028] The horizontal distance between the edge of the etched ITO conductive layer and the first end is equal to the horizontal distance between the edge of the etched ITO conductive layer and the second end, and both are the second preset length;

[0029] The length of the inclined sidewall is a third preset length; the distance between the ITO conductive layer and the inclined sidewall is a fourth preset length; the acute angle between the inclined sidewall and the plane containing the N-type region platform is θ;

[0030] If the first preset length is L1, the second preset length is L2, the third preset length is L3, and the fourth preset length is L4, then L4 = L2 - L3cosθ.

[0031] Preferably, L1 is greater than 3.5 micrometers, L2 is greater than 2.5 micrometers, the length of L3 is in the range of 1.0 micrometer to 2.5 micrometers, and the length of L4 is in the range of 0.5 micrometers to 2 micrometers.

[0032] Preferably, in step S401, forming the MESA / ITO lithographic pattern includes: exposing a portion of the ITO composite layer on the upper surface of the ITO composite layer through a spin coating, exposure, and development process, and forming the MESA / ITO lithographic pattern using a first hardening temperature;

[0033] In step S403, softening the MESA / ITO lithographic pattern by heating includes: softening the MESA / ITO lithographic pattern by using a second hard film temperature;

[0034] Wherein, the first hardening film temperature is T1, the second hardening film temperature is T2, then T2-T1≥5℃.

[0035] Preferably, the temperature range of T1 is 80℃-110℃, and the temperature range of T2 is 110℃-150℃.

[0036] Preferably, step S500 specifically includes the following steps:

[0037] Step S501: Etch along the MESA / ITO lithography pattern and the exposed P-type semiconductor layer using ICP etching process to expose a portion of the N-type semiconductor layer and form an N-type mesa.

[0038] Step S502: Use 5% low-concentration oxalic acid to rinse and etch away the ITO masking layer and the remaining MESA / ITO photolithography pattern, exposing the ITO conductive layer and a portion of the P-type semiconductor layer, forming a P-type mesa.

[0039] Preferably, in step S800, the distance between the etching lines on both sides of the N-type pad opening and the edge of the upper surface of the N-type electrode, and the distance between the etching lines on both sides of the P-type pad opening and the edge of the upper surface of the P-type electrode, are both a fifth preset length, the fifth preset length being L5, and the length range of L5 being 2 micrometers to 4 micrometers.

[0040] Preferably, the thickness of the ITO composite layer ranges from 1100 Å to 6000 Å, including the endpoint values; and the thickness of the ITO masking layer ranges from 300 Å to 5000 Å, including the endpoint values.

[0041] Preferably, the ITO composite layer is a transparent conductive indium tin oxide material.

[0042] A micro LED chip, comprising:

[0043] The micro LED chip is manufactured using any one of the micro LED chip manufacturing methods described above.

[0044] The above technical solution achieves the following results:

[0045] The method for fabricating a micro LED chip provided by this invention, on one hand, involves preparing an ITO composite layer with different etching rates on an epitaxial structure by controlling growth conditions. The ITO composite layer includes, along the growth direction, a stacked ITO conductive layer and an ITO masking layer, and the density of the ITO masking layer is less than that of the ITO conductive layer, that is, the etching rate of the ITO masking layer is greater than that of the ITO conductive layer. The specific steps include: setting the vacuum level inside the reaction chamber, using a first coating temperature and a first coating rate, and introducing a first oxygen flow rate to grow the ITO conductive layer; maintaining the vacuum level inside the reaction chamber, stopping the oxygen supply, lowering the temperature to a second coating temperature, and increasing the coating rate to a second coating rate to grow the ITO masking layer. Then, a MESA / ITO photolithographic pattern is prepared on the upper surface of the ITO composite layer, and the ITO composite layer is etched to form a suspended structure. The lateral etching depth of the ITO masking layer is greater than that of the ITO conductive layer. By controlling the lateral etching depth of the ITO masking layer, the ITO conductive layer is not affected by the adhesion of the photoresist, so that the lateral etching depth of the ITO conductive layer reaches the preset length. The etched inclined sidewall has a certain distance from the ITO conductive layer to avoid leakage problems caused by overlap.

[0046] On the other hand, combining the MESA / ITO process with photolithography avoids the problem of different areas being easily misaligned when MESA / ITO is done separately, which requires a large amount of over-etching, resulting in loss of the light-emitting area and affecting the brightness of the micro LED chip. This simplifies the process, increases production, reduces costs, and also improves brightness.

[0047] Furthermore, by setting the horizontal distance between the edge of the etched ITO conductive layer and the first end to be equal to the horizontal distance between the edge of the etched ITO conductive layer and the second end, and both being the second preset length L2; the length of the inclined sidewall is the third preset length L3; the distance between the ITO conductive layer and the inclined sidewall is the fourth preset length L4; and the acute angle between the inclined sidewall and the plane containing the N-type area is θ; then, L4 = L2 - L3cosθ, and the distance between the ITO conductive layer and the inclined sidewall can be set according to actual needs.

[0048] Furthermore, in existing technologies where MESA / ITO processes are performed separately, two photomasks are used, with a certain distance reserved between them to ensure that the ITO conductive layer and the inclined sidewall do not overlap after MESA etching, causing leakage. Also, the warping of the epitaxial edge can easily cause misalignment in different areas, requiring a larger amount of over-etching and resulting in loss of the light-emitting area. To avoid leakage caused by the ITO conductive layer overlapping with the inclined sidewall after MESA etching, the distance between the ITO conductive layer and the inclined sidewall should be controlled to be as small as possible. By setting the length of the ITO conductive layer and the inclined sidewall L4 to be in the range of 0.5 micrometers to 2 micrometers, the effective light-emitting area of ​​the micro LED chip can be increased by 10%-20% in brightness.

[0049] Furthermore, after the MESA / ITO lithographic pattern is etched by the ICP etching process, the photoresist is deformed and easily leaves residue after removal. By using 5% low-concentration oxalic acid to rinse and etch away the ITO masking layer and the remaining MESA / ITO lithographic pattern, the surface of the ITO conductive layer can be kept flat, clean and free of contamination, thereby ensuring the ITO current spreading capability. Moreover, 5% low-concentration oxalic acid will not damage the ITO conductive layer.

[0050] The LED chip provided by this invention is manufactured using the aforementioned method for manufacturing micro LED chips, which can effectively improve the luminous brightness and reliability of LED chips. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0052] Figure 1 A flowchart illustrating a method for fabricating a micro LED chip according to an embodiment of the present invention;

[0053] Figures 2 to 13 for Figure 1 The process cross-sectional diagrams and corresponding top views for each step of the manufacturing method shown are provided.

[0054] Explanation of symbols in the diagram:

[0055] 1. Substrate; 2. Epitaxial structure; 21. N-type semiconductor layer; 22. Active region; 23. P-type semiconductor layer; 3. ITO composite layer; 31. ITO conductive layer; 32. ITO masking layer; 4. MESA / ITO lithography pattern; 5. N-type electrode; 51. N-type electrode fabrication area; 52. N-type pad opening; 6. P-type electrode; 61. P-type electrode fabrication area; 62. P-type pad opening; 7. Negative photoresist; 8. Insulating protective layer; A. First end; B. Second end; C. N-type mesa; D. P-type mesa; E. Inclined sidewall; T1. First hardening temperature; T2. Second hardening temperature; L1. First preset length; L2. Second preset length; L3. Third preset length; L4. Fourth preset length; L5. Fifth preset length; θ. Acute angle between the inclined sidewall and the plane containing the N-type mesa. Detailed Implementation

[0056] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0057] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0058] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0059] A method for fabricating a micro LED chip, such as Figure 1 As shown, it includes the following steps:

[0060] Step S100, as follows Figure 2 As shown, a substrate 1 is provided;

[0061] In this embodiment, there is no restriction on the specific type of substrate. Optionally, the substrate can be a semiconductor substrate such as a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The specific material of the substrate can be selected and used according to the requirements.

[0062] Step S200, as follows Figure 3 As shown, an epitaxial structure 2 is grown on one side surface of the substrate 1. The epitaxial structure 2 includes, along the growth direction, a stacked N-type semiconductor layer 21, an active region 22, and a P-type semiconductor layer 23.

[0063] In this embodiment, the specific materials of the N-type semiconductor layer and the P-type semiconductor layer are not limited. Optionally, the N-type semiconductor layer is an N-type GaN layer and the P-type semiconductor layer is a P-type GaN layer.

[0064] In this embodiment, the specific number of layers and structure of the epitaxial structure are not limited. The epitaxial structure includes at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer. In other embodiments, in order to improve lattice matching, the epitaxial structure of the LED chip may also include a superlattice structure, etc.

[0065] Step S300, as follows Figure 4 As shown, an ITO composite layer 3 is prepared on the upper surface of the epitaxial structure 2. The ITO composite layer 3 includes a stacked ITO conductive layer 31 and an ITO masking layer 32 along the growth direction, and the etching rate of the ITO masking layer 32 is greater than the etching rate of the ITO conductive layer 31.

[0066] Step S300 specifically includes the following processes:

[0067] Step S301: Set the vacuum level inside the reaction chamber, adopt the first coating temperature and the first coating rate, and introduce the first oxygen flow rate to grow the ITO conductive layer 31;

[0068] Step S302: Maintain the vacuum inside the reaction chamber, stop the oxygen supply, lower the temperature to the second coating temperature, and increase the coating rate to the second coating rate to grow the ITO masking layer 32.

[0069] Optionally, in this embodiment, an ITO composite layer 3 is prepared on the upper surface of the epitaxial structure 2 using an electron beam evaporation deposition process.

[0070] Optionally, in this embodiment, the ITO composite layer 3 is a transparent conductive indium tin oxide material.

[0071] Optionally, in this embodiment, the thickness of the ITO composite layer 3 ranges from 1100 Å to 6000 Å, including the endpoint values; the thickness of the ITO masking layer 32 ranges from 300 Å to 5000 Å, including the endpoint values.

[0072] Optionally, in this embodiment, in step S300, the etching selection ratio of the ITO masking layer 32 to the ITO conductive layer 31 ranges from 10:1 to 100:1.

[0073] Optionally, in this embodiment, in step S301, the vacuum level inside the reaction chamber ranges from 1.0×10⁻⁵ Torr to 1.0×10⁻⁴ Torr, excluding endpoint values; the first coating temperature ranges from 200℃ to 350℃, including endpoint values; the first coating rate ranges from 0.5 Å / S to 1.5 Å / S, including endpoint values; and the first oxygen flow rate ranges from 5 sccm to 30 sccm, including endpoint values.

[0074] In step S302, the second coating temperature ranges from 20℃ to 100℃, including the endpoint values; the second coating rate ranges from 2.5 Å / S to 5 Å / S, including the endpoint values.

[0075] Step S400: Prepare a MESA / ITO lithographic pattern 4 on a portion of the upper surface of the ITO composite layer 3, and etch the ITO composite layer 3 to form a suspended structure, so that the lateral etching depth of the ITO masking layer 32 is greater than the lateral etching depth of the ITO conductive layer 31, soften the MESA / ITO lithographic pattern 4, so that it has a structure that is narrow at the top and wide at the bottom and covers the exposed surface of the etched ITO composite layer 3 and a portion of the surface of the P-type semiconductor layer 23.

[0076] Optionally, in one embodiment of this application, step S400 specifically includes the following steps:

[0077] Step S401, as follows Figure 5 As shown, a whole layer of photoresist is deposited on the upper surface of the ITO composite layer 3, and the patterned photoresist forms a MESA / ITO photolithographic pattern 4. The edge position of the contact surface between the MESA / ITO photolithographic pattern 4 and the ITO composite layer 3 is the first end A.

[0078] Step S402, as follows Figure 6 As shown, the ITO composite layer 3 is etched in one step using a wet etching process to form a suspended structure and expose part of the P-type semiconductor layer 23;

[0079] Specifically, ITO etching solution is used to etch along the exposed ITO composite layer 3 and to etch the sidewalls of the ITO composite layer 3 laterally, so that the peripheral area of ​​the contact surface between the MESA / ITO lithography pattern 4 and the ITO composite layer 3 is suspended to form a suspended structure.

[0080] Step S403, as Figure 7 As shown, the MESA / ITO lithographic pattern 4 is softened by heating, so that it has a narrow top and wide bottom structure and covers the exposed surface of the etched ITO composite layer 3 and part of the surface of the P-type semiconductor layer 23. The edge position of the contact surface between the MESA / ITO lithographic pattern 4 and the P-type semiconductor layer 23 is the second end B.

[0081] The lateral etching depth of the ITO masking layer 32 is the horizontal distance between the edge of the etched ITO masking layer and the first end A; the lateral etching depth of the ITO conductive layer 31 is the horizontal distance between the edge of the etched ITO conductive layer and the first end A.

[0082] It should be noted that in this embodiment, because wet etching has isotropic properties, the ITO etching solution will also etch laterally while etching the ITO composite layer downwards.

[0083] It should also be noted that in this embodiment, the peripheral area of ​​the contact surface between the MESA / ITO lithographic pattern and the ITO composite layer is suspended. The MESA / ITO lithographic pattern is softened by heating, and then the surface tension and gravity of the photoresist are used to control the flow and deformation of the photoresist so that it covers the etched ITO composite layer.

[0084] Optionally, in this embodiment, in step S401, forming the MESA / ITO lithographic pattern 4 includes: exposing part of the ITO composite layer 3 on the upper surface of the ITO composite layer 3 through a spin coating, exposure, and development process, and forming the MESA / ITO lithographic pattern 4 by using a first hard film temperature.

[0085] In step S403, softening the MESA / ITO lithographic pattern 4 by heating includes: softening the MESA / ITO lithographic pattern 4 by using a second hard film temperature;

[0086] Where the first hardening temperature is T1 and the second hardening temperature is T2, then T2-T1≥5℃.

[0087] Optionally, in this embodiment, the temperature range of T1 is 80℃-110℃, and the temperature range of T2 is 110℃-150℃.

[0088] Optionally, in this embodiment, the MESA / ITO lithography pattern 4 is a positive photoresist.

[0089] Optionally, in one embodiment of this application, the vertical projection of the etched ITO composite layer 3 onto the plane of the substrate 1 is located within the vertical projection of the MESA / ITO lithographic pattern 4 onto the plane of the substrate 1, and the vertical projection of the ITO masking layer 32 onto the plane of the substrate 1 is located within the vertical projection of the ITO conductive layer 31 onto the plane of the substrate 1.

[0090] Step S500: Using MESA / ITO lithography pattern 4 as a mask, N-type mesa C and P-type mesa D are formed simultaneously through a single dry etching process, and the ITO conductive layer 31 is exposed. The etching surface between the P-type mesa D and the N-type mesa C is an inclined sidewall E.

[0091] Optionally, in one embodiment of this application, step S500 specifically includes the following steps:

[0092] Step S501, as follows Figure 8 As shown, the N-type semiconductor layer 23 is etched along the MESA / ITO lithography pattern 4 and exposed by ICP etching process, exposing part of the N-type semiconductor layer 21 to form an N-type mesa C.

[0093] Step S502, as follows Figure 9 As shown, the ITO masking layer 32 and the residual MESA / ITO lithographic pattern 4 are removed by rinsing and etching with 5% low-concentration oxalic acid, exposing the ITO conductive layer 31 and a portion of the P-type semiconductor layer 23, forming a P-type mesa D.

[0094] In this embodiment, ICP etching process refers to inductively coupled plasma (ICP) etching process.

[0095] In this embodiment, the etching gas in the ICP etching process in step S501 is not limited. Optionally, in step S501, the etching gas in the ICP etching process is a mixture of Cl2, Ar and O2, with a gas ratio of Cl2:Ar:O2=5:1:2.

[0096] Optionally, in this embodiment, the depth from the upper surface of the epitaxial structure 2 to the N-type mesa C is 1 micrometer to 1.4 micrometers, excluding the endpoint value.

[0097] Optionally, in this embodiment, the P-type mesa D surrounds the ITO conductive layer 31, and the N-type mesa C surrounds the P-type mesa D.

[0098] Optionally, in one embodiment of this application, the horizontal distance between the edge of the etched ITO masking layer and the first end A is equal to the horizontal distance between the edge of the etched ITO masking layer and the second end B, and both are the first preset length;

[0099] The horizontal distance between the edge of the etched ITO conductive layer and the first end A is equal to the horizontal distance between the edge of the etched ITO conductive layer and the second end B, and both are the second preset length.

[0100] The length of the inclined sidewall E is the third preset length; the distance between the ITO conductive layer 31 and the inclined sidewall E is the fourth preset length; the acute angle between the inclined sidewall and the plane containing the N-type region platform is θ.

[0101] If the first preset length is L1, the second preset length is L2, the third preset length is L3, and the fourth preset length is L4, then L4 = L2 - L3cosθ.

[0102] Optionally, in this embodiment, L1 > 3.5 micrometers, L2 > 2.5 micrometers, the length range of L3 is 1.0 micrometer to 2.5 micrometers, and the length range of L4 is 0.5 micrometers to 2 micrometers.

[0103] Optionally, in this embodiment, the horizontal distance between the intersection of the inclined sidewall E and the N-type region mesa C and the edge of the etched ITO conductive layer is a second preset length.

[0104] Step S600: Alloy the ITO conductive layer 31 using the RTA process to form a good ohmic contact between it and the P-type semiconductor layer 23.

[0105] Optionally, in this embodiment, the alloying of the ITO conductive layer 31 by the RTA process in step S600 includes:

[0106] The ITO conductive layer 31 is annealed in an O2 / N2 atmosphere using the RTA process, with an annealing temperature range of 400℃-600℃, including the endpoint values.

[0107] In this embodiment, RTA process refers to rapid thermal annealing process.

[0108] Step S700: An N-type electrode 5 and a P-type electrode 6 are formed on the N-type mesa C and the upper surface of the ITO conductive layer 31, respectively.

[0109] Optionally, in one embodiment of this application, step S700 specifically includes the following steps:

[0110] Step S701, as follows Figure 10 As shown, negative photoresist 7 is deposited across the entire surface, and an N-type electrode fabrication area 51 is formed on the N-type mesa C through a process of spin coating, exposure, post-baking, and development. A P-type electrode fabrication area 61 is formed on the upper surface of the ITO conductive layer 31.

[0111] Step S702, as follows Figure 11 As shown, an N-type electrode 5 is deposited in the N-type electrode fabrication area 51, and a P-type electrode 6 is deposited in the P-type electrode fabrication area 61.

[0112] Step S703, as follows Figure 12 As shown, the negative photoresist 7 is removed.

[0113] In step S800, an insulating protective layer 8 is deposited on the entire surface, and N-type pad openings 52 and P-type pad openings 62 are formed at the positions of the insulating protective layer 8 corresponding to the N-type electrode 5 and the P-type electrode 6, respectively. The insulating protective layer 8 covers the exposed surface of the ITO conductive layer 31 and the epitaxial structure 2.

[0114] Optionally, in this embodiment, step S800 specifically includes:

[0115] like Figure 13 As shown, an insulating protective layer 8 is deposited on the entire surface. After the processes of spin coating, exposure, development and hardening, the insulating protective layer 8 is etched by ICP to expose part of the upper surface of the N-type electrode 5 to form an N-type pad opening 52, and to expose part of the upper surface of the P-type electrode 6 to form a P-type pad opening 62.

[0116] Optionally, in this embodiment, in step S800, the distance between the etching lines on both sides of the N-type pad opening 52 and the edge of the upper surface of the N-type electrode, and the distance between the etching lines on both sides of the P-type pad opening 62 and the edge of the upper surface of the P-type electrode are both a fifth preset length, which is L5. The length of L5 is 2 micrometers to 4 micrometers, so as to ensure that the sidewalls of the N-type electrode 5 and the P-type electrode 6 are covered by the insulating protective layer 8, preventing open circuits or short circuits and improving reliability.

[0117] This embodiment provides a micro LED chip, which is fabricated using the method described above. (Refer to...) Figure 13 As shown, the micro LED chip includes:

[0118] Substrate 1;

[0119] In this embodiment, there is no limitation on the specific type of substrate. Optionally, the substrate can be a semiconductor substrate such as a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The specific material of the substrate can be selected and used according to the requirements, and this embodiment does not limit it.

[0120] An epitaxial structure 2 is disposed on one side surface of substrate 1. The epitaxial structure 2 includes: an N-type semiconductor layer 21, an active region 22 and a P-type semiconductor layer 23, which are sequentially stacked on substrate 1 from bottom to top.

[0121] In this embodiment, the specific materials of the N-type semiconductor layer and the P-type semiconductor layer are not limited. Optionally, the N-type semiconductor layer is an N-type GaN layer and the P-type semiconductor layer is a P-type GaN layer.

[0122] In this embodiment, the specific number of layers and structure of the epitaxial structure are not limited. The epitaxial structure includes at least an N-type semiconductor layer, an active region, and a P-type semiconductor layer. In other embodiments, in order to improve lattice matching, the epitaxial structure of the LED chip may also include a superlattice structure, etc.

[0123] refer to Figure 9 As shown, the upper surface of the P-type semiconductor layer 23 has a groove extending toward the N-type semiconductor layer 21, exposing the N-type semiconductor layer 21 and forming an N-type mesa C.

[0124] ITO conductive layer 31 is disposed on the side surface of P-type semiconductor layer 23 away from active region 22 and exposes part of P-type semiconductor layer 23 to form P-type region mesa D. There is an inclined sidewall E between P-type region mesa D and N-type region mesa C.

[0125] An N-type electrode 5 and a P-type electrode 6 are formed on the N-type mesa C and the upper surface of the ITO conductive layer 31, respectively.

[0126] The insulating protective layer 8 covers the exposed surfaces of the ITO conductive layer 31 and the epitaxial structure 2, and the insulating protective layer 8 has an N-type pad opening 51 that exposes the upper surface of the N-type electrode 5 and a P-type pad opening 52 that exposes the upper surface of the P-type electrode 5.

[0127] Optionally, in this embodiment, the ITO conductive layer 31 is a transparent conductive indium tin oxide material.

[0128] Optionally, in this embodiment, the depth from the upper surface of the epitaxial structure 2 to the N-type mesa C is 1 micrometer to 1.4 micrometers, excluding the endpoint value.

[0129] Optionally, in this embodiment, the P-type mesa D surrounds the ITO conductive layer 31, and the N-type mesa C surrounds the P-type mesa D.

[0130] Optionally, in this embodiment, the horizontal distance between the intersection of the inclined sidewall E and the N-type region platform C and the edge of the ITO conductive layer is a second preset length; the length of the inclined sidewall E is a third preset length; the distance between the ITO conductive layer 31 and the inclined sidewall E is a fourth preset length; and the acute angle between the inclined sidewall and the plane containing the N-type region platform is θ.

[0131] If the second preset length is L2, the third preset length is L3, and the fourth preset length is L4, then L4 = L2 - L3cosθ.

[0132] Optionally, in this embodiment, L2 > 2.5 micrometers, the length range of L3 is 1.0 micrometer to 2.5 micrometers, and the length range of L4 is 0.5 micrometers to 2 micrometers.

[0133] Optionally, in this embodiment, the distance between the etching lines on both sides of the N-type pad opening 52 and the edge of the upper surface of the N-type electrode, and the distance between the etching lines on both sides of the P-type pad opening 62 and the edge of the upper surface of the P-type electrode are both a fifth preset length, which is L5. The length of L5 is in the range of 2 micrometers to 4 micrometers, so as to ensure that the sidewalls of the N-type electrode 5 and the P-type electrode 6 are covered by the insulating protective layer 8, to prevent open circuits or short circuits and improve reliability.

[0134] In summary, the above technical solution achieves the following results:

[0135] The method for fabricating a micro LED chip provided in this embodiment involves, on one hand, preparing an ITO composite layer with different etching rates on an epitaxial structure by controlling growth conditions. The ITO composite layer includes, along the growth direction, a stacked ITO conductive layer and an ITO masking layer, and the density of the ITO masking layer is less than that of the ITO conductive layer, i.e., the etching rate of the ITO masking layer is greater than that of the ITO conductive layer. The specific steps include: setting the vacuum level inside the reaction chamber, using a first coating temperature and a first coating rate, and introducing a first oxygen flow rate to grow the ITO conductive layer; maintaining the vacuum level inside the reaction chamber, stopping the oxygen supply, lowering the temperature to a second coating temperature, and increasing the coating rate to a second coating rate to grow the ITO masking layer. Then, a MESA / ITO photolithographic pattern is prepared on the upper surface of the ITO composite layer, and the ITO composite layer is etched to form a suspended structure. The lateral etching depth of the ITO masking layer is greater than that of the ITO conductive layer. By controlling the lateral etching depth of the ITO masking layer, the ITO conductive layer is not affected by the adhesion of the photoresist, so that the lateral etching depth of the ITO conductive layer reaches the preset length. The etched inclined sidewall has a certain distance from the ITO conductive layer to avoid leakage problems caused by overlap.

[0136] On the other hand, combining the MESA / ITO process with photolithography avoids the problem of different areas being easily misaligned when MESA / ITO is done separately, which requires a large amount of over-etching, resulting in loss of the light-emitting area and affecting the brightness of the micro LED chip. This simplifies the process, increases production, reduces costs, and also improves brightness.

[0137] Furthermore, by setting the horizontal distance between the edge of the etched ITO conductive layer and the first end to be equal to the horizontal distance between the edge of the etched ITO conductive layer and the second end, and both being the second preset length L2; the length of the inclined sidewall is the third preset length L3; the distance between the ITO conductive layer and the inclined sidewall is the fourth preset length L4; and the acute angle between the inclined sidewall and the plane containing the N-type area is θ; then, L4 = L2 - L3cosθ, and the distance between the ITO conductive layer and the inclined sidewall can be set according to actual needs.

[0138] Furthermore, in existing technologies where MESA / ITO processes are performed separately, two photomasks are used, with a certain distance reserved between them to ensure that the ITO conductive layer and the inclined sidewall do not overlap after MESA etching, causing leakage. Also, the warping of the epitaxial edge can easily cause misalignment in different areas, requiring a larger amount of over-etching and resulting in loss of the light-emitting area. To avoid leakage caused by the ITO conductive layer overlapping with the inclined sidewall after MESA etching, the distance between the ITO conductive layer and the inclined sidewall should be controlled to be as small as possible. By setting the length of the ITO conductive layer and the inclined sidewall L4 to be in the range of 0.5 micrometers to 2 micrometers, the effective light-emitting area of ​​the micro LED chip can be increased by 10%-20% in brightness.

[0139] Furthermore, after the MESA / ITO lithographic pattern is etched by the ICP etching process, the photoresist is deformed and easily leaves residue after removal. By using 5% low-concentration oxalic acid to rinse and etch away the ITO masking layer and the remaining MESA / ITO lithographic pattern, the surface of the ITO conductive layer can be kept flat, clean and free of contamination, thereby ensuring the ITO current spreading capability. Moreover, 5% low-concentration oxalic acid will not damage the ITO conductive layer.

[0140] The LED chip provided in this embodiment is manufactured using the aforementioned method for manufacturing micro LED chips, which can effectively improve the luminous brightness and reliability of the LED chip.

[0141] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0142] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0143] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a micro LED chip, characterized in that, include: Step S100: Provide a substrate; Step S200: An epitaxial structure is grown on one side surface of the substrate. The epitaxial structure includes, in sequence along the growth direction, a stacked N-type semiconductor layer, an active region, and a P-type semiconductor layer. Step S300: An ITO composite layer is prepared on the upper surface of the epitaxial structure. The ITO composite layer includes a stacked ITO conductive layer and an ITO masking layer along the growth direction. The etching rate of the ITO masking layer is greater than that of the ITO conductive layer. The etching selectivity ratio of the ITO masking layer to the ITO conductive layer is in the range of 10:1 to 100:

1. Step S300 specifically includes the following procedures: Step S301: Set the vacuum level inside the reaction chamber, adopt the first coating temperature and the first coating rate, and introduce the first oxygen flow rate to grow the ITO conductive layer; In the step S301, the vacuum degree inside the reaction cavity ranges from 1.0x10 -5 Torr to 1.0x10 -4 Torr, inclusive; the first coating temperature ranges from 200℃ to 350℃, inclusive; the first coating rate ranges from 0.5Å / S to 1.5Å / S, inclusive; and the first oxygen flow ranges from 5sccm to 30sccm, inclusive. Step S302: Maintain the vacuum inside the reaction chamber, stop the oxygen supply, lower the temperature to the second coating temperature, and increase the coating rate to the second coating rate to grow the ITO masking layer. In step S302, the temperature range of the second coating temperature is 20℃-100℃, including the endpoint values; the range of the second coating rate is 2.5Å / S-5Å / S, including the endpoint values. Step S400: Prepare a MESA / ITO lithographic pattern on a portion of the upper surface of the ITO composite layer, and etch the ITO composite layer to form a suspended structure, so that the lateral etching depth of the ITO masking layer is greater than the lateral etching depth of the ITO conductive layer, soften the MESA / ITO lithographic pattern, so that it has a structure that is narrow at the top and wide at the bottom and covers the exposed surface of the etched ITO composite layer and a portion of the surface of the P-type semiconductor layer. Step S500: Using the MESA / ITO lithography pattern as a mask, N-type mesa and P-type mesa are formed simultaneously through a single dry etching process, and the ITO conductive layer is exposed. The etching surface between the P-type mesa and the N-type mesa is an inclined sidewall. Step S600: Alloy the ITO conductive layer using the RTA process to form a good ohmic contact between it and the P-type semiconductor layer; Step S700: An N-type electrode and a P-type electrode are formed on the N-type region mesa and the upper surface of the ITO conductive layer, respectively; Step S800: Deposit an insulating protective layer over the entire surface, and form N-type pad openings and P-type pad openings at the positions of the insulating protective layer corresponding to the N-type electrode and the P-type electrode, respectively. The insulating protective layer covers the ITO conductive layer and the exposed surface of the epitaxial structure. Wherein, the edge of the contact surface between the MESA / ITO lithographic pattern and the ITO composite layer is the first end; the edge of the contact surface between the MESA / ITO lithographic pattern and the P-type semiconductor layer is the second end; The horizontal distance between the edge of the etched ITO masking layer and the first end is equal to the horizontal distance between the edge of the etched ITO masking layer and the second end, and both are the first preset length; The horizontal distance between the edge of the etched ITO conductive layer and the first end is equal to the horizontal distance between the edge of the etched ITO conductive layer and the second end, and both are the second preset length; The length of the inclined sidewall is a third preset length; the distance between the ITO conductive layer and the inclined sidewall is a fourth preset length; the acute angle between the inclined sidewall and the plane containing the N-type region platform is θ; The first preset length is L1, the second preset length is L2, the third preset length is L3, and the fourth preset length is L4. Then, L4 = L2 - L3cosθ. The length of L1 is greater than 3.5 micrometers, the length of L2 is greater than 2.5 micrometers, the length of L3 is between 1.0 micrometer and 2.5 micrometers, and the length of L4 is between 0.5 micrometer and 2 micrometers.

2. The method for manufacturing a micro LED chip according to claim 1, characterized in that: Step S400 specifically includes the following procedures: Step S401: Deposit a full layer of photoresist on the upper surface of the ITO composite layer, and pattern the photoresist to form a MESA / ITO photolithography pattern; Step S402: The ITO composite layer is etched in one step using a wet etching process to form a suspended structure and expose part of the P-type semiconductor layer; Specifically, ITO etching solution is used to etch along the exposed ITO composite layer and to etch the sidewalls of the ITO composite layer laterally, so that the peripheral area of ​​the MESA / ITO lithographic pattern and the contact surface of the ITO composite layer is suspended to form a suspended structure. Step S403: Soften the MESA / ITO photolithography pattern by heating, so that it has a narrow top and wide bottom structure and covers the exposed surface of the etched ITO composite layer and part of the surface of the P-type semiconductor layer; Wherein, the lateral etching depth of the ITO masking layer is the horizontal distance between the edge of the etched ITO masking layer and the first end; the lateral etching depth of the ITO conductive layer is the horizontal distance between the edge of the etched ITO conductive layer and the first end.

3. The method for manufacturing a micro LED chip according to claim 2, characterized in that: In step S401, forming the MESA / ITO lithographic pattern includes: exposing a portion of the ITO composite layer on the upper surface of the ITO composite layer through a spin coating, exposure, and development process, and forming the MESA / ITO lithographic pattern using a first hardening temperature; In step S403, softening the MESA / ITO lithographic pattern by heating includes: softening the MESA / ITO lithographic pattern by using a second hard film temperature; Wherein, the first hardening film temperature is T1, the second hardening film temperature is T2, then T2-T1≥5℃.

4. The method of claim 3, wherein: The temperature range of T1 is 80℃-110℃, and the temperature range of T2 is 110℃-150℃.

5. The method for fabricating a micro LED chip according to claim 1, characterized in that: Step S500 specifically includes the following procedures: Step S501: Etch along the MESA / ITO lithography pattern and the exposed P-type semiconductor layer using ICP etching process to expose a portion of the N-type semiconductor layer and form an N-type mesa. Step S502: Use 5% low-concentration oxalic acid to rinse and etch away the ITO masking layer and the remaining MESA / ITO photolithography pattern, exposing the ITO conductive layer and a portion of the P-type semiconductor layer, forming a P-type mesa.

6. The method of claim 1, wherein: In step S800, the distance between the etching lines on both sides of the N-type pad opening and the edge of the upper surface of the N-type electrode, and the distance between the etching lines on both sides of the P-type pad opening and the edge of the upper surface of the P-type electrode, are both a fifth preset length, which is L5, and the length range of L5 is 2 micrometers to 4 micrometers.

7. The method of claim 1, wherein: The thickness of the ITO composite layer ranges from 1100 Å to 6000 Å, including the endpoint values; the thickness of the ITO masking layer ranges from 300 Å to 5000 Å, including the endpoint values.

8. The method of claim 1, wherein: The ITO composite layer is a transparent conductive indium tin oxide material.

9. A micro-LED chip, characterized in that, The micro LED chip is manufactured using the micro LED chip manufacturing method described in any one of claims 1 to 8.

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