Aurora 64 / 66B encoding-based gigabit image transmission module

Abstract

The application provides a kind of based on Aurora 64 / 66B encoding's 10G image transmission module, including data alignment module, image encoding module, image decoding module and transceiver control module;Data alignment module is used to find the data head of a frame of image data, ensure that the input to image encoding module is a complete frame of image;Image encoding module encodes multiple images according to priority;Image decoding module can recover the received fiber data into 16bit standard image and image control row field signal;Transceiver control module completes the configuration of xilinx's GTX module, controls the data transceiving work of GTX module simultaneously.The application parses the received encoded data in the fiber into the row valid signal, field valid signal and image data of image, so as to realize 10G fiber image transmission.Compared with the traditional 10G Ethernet, the transmission protocol used in this scheme is more concise, and the bandwidth utilization is higher.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding. Background Technology

[0002] As image sensors are upgraded, images are becoming clearer and the resolution of individual images is increasing. This brings the problem of ever-growing image data sizes. Traditional methods of transmitting images using CameraLink and gigabit networks are no longer sufficient.

[0003] The use of Cameralink and gigabit networks for image transmission in existing technologies has the following disadvantages and limitations:

[0004] (1) Using traditional Cameralink and Gigabit Ethernet to transmit images does not provide sufficient bandwidth to meet the requirements of high-definition image transmission. This technology can achieve a bandwidth of 10Gbps, which can meet the bandwidth requirements of high-definition images.

[0005] (2) Traditional 10 Gigabit Ethernet technology uses TCP or UDP protocols, which have low bandwidth utilization efficiency due to the additional overhead of the protocols.

[0006] (3) Using one optical fiber can ensure the simultaneous transmission of multiple images, reducing the number of transmission lines in the system and improving the system's stability. Summary of the Invention

[0007] Specifically, the present invention provides a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, the 10 Gigabit image transmission module based on Aurora 64 / 66B encoding includes a data alignment module, an image encoding module, an image decoding module and a transceiver control module;

[0008] The data alignment module is used to find the data header of a frame of image data to ensure that the image encoding module inputs a complete frame of image;

[0009] The image encoding module encodes multiple images according to priority;

[0010] The image decoding module can recover the received fiber optic data into a 16-bit standard image and image control line and field signals.

[0011] The transceiver control module completes the configuration of the Xilinx GTX module and controls the data transmission and reception of the GTX module.

[0012] Furthermore, the data alignment module includes an image clock signal, 16-bit YUV or RGB format image data, a line valid signal, and a field valid signal;

[0013] The image alignment unit uses the image clock signal as the module clock. First, it delays the input image data, line valid signal, and field valid signal by two clock cycles of the image clock signal. The aligned image data and field valid signal are the delayed data. The line valid signal is generated separately by the state machine. The state machine continuously captures the rising edge of the line valid signal. After capturing the rising edge, it sets the output aligned field valid signal to a high level and then enters the next state. This continues until it captures the falling edge of the input line valid signal. After capturing the falling edge, it sets the processed output line valid signal to a low level, and the state machine enters the original rising edge capture state. This process is repeated to process the input line valid signal. The field valid signal and image data are directly output after a two-clock-cycle delay.

[0014] Furthermore, the image encoding module includes an image buffer unit, a FIFO polling encoding unit, an image data reading unit, and an image data encoding unit;

[0015] The image buffer unit ANDs the row valid signal and the field valid signal as the write signal for the image buffer unit; the image data is the data input for the image buffer unit;

[0016] The FIFO polling encoding unit monitors the number of data in multiple image buffer units in real time. When any channel image buffer unit has a row of image data buffered, the transmission flag of that channel is set to 1.

[0017] The state machine of the image data reading unit continuously queries the transmission flags of each channel of the image buffer unit. If a transmission flag of a certain channel is found to be set to 1, the transmission of data through that channel is started: the read signal required by the image data reading unit is set to a high level for a preset period using the clock of the transceiver control module, and the image data in the buffer image data reading unit is read in the same number of preset periods.

[0018] The image data encoding unit first writes a 64-bit data to the transceiver control module when the write valid signal is valid. This data includes the image's line count, frame count, and channel identification code. Then, it writes the corresponding number of 64-bit image data for each line of image data to the transceiver control module.

[0019] Furthermore, the image buffer unit is configured with 16-bit input and 64-bit output.

[0020] Furthermore, the image encoding module comprises an image channel identification polling unit, an image data extraction unit, an image data caching unit, an image cache data polling and caching unit, an image data reading unit, and a line and field signal recovery unit;

[0021] The channel code identification polling buffer unit is responsible for identifying the channel identification code in the optical fiber data. When a certain channel data is identified in the optical fiber data, the line count and field frame count are stored in the buffer, and the original 64-bit image data is stored in the 64-bit in and 16-bit out FIFO of that channel. When the receiving FIFO of that channel receives a line of image data, the receiving completion flag is set to 1.

[0022] After the image data extraction unit finds that the reception completion flag is set to 1, it starts reading the 16-bit data corresponding to one row of image data buffered in the FIFO. During the data reading, the row valid signal HS is set to 1; the field valid signal is set to 1 when the row count is 0 and the row signal is high, and VS is set to 0 on the falling edge of the row signal when the row count is the row of image data.

[0023] Furthermore, the transceiver control module includes a reset control unit, a clock management unit, a scrambling code encoding unit, a descrambling code unit, and a GTX unit;

[0024] The reset control unit uses the user clock output by the GTX unit as the clock count. If the count value is within 1000, the reset signal is set to 0; if the count value is within 1000 to 4000, the reset signal is set to 1; and if the count value is greater than 4000, the reset signal is set to 0.

[0025] The clock management unit then uses the external crystal oscillator input main clock through the Xilinx clk_wiz IP core to generate the running clock required by each module in the program;

[0026] The scrambling and descrambling units implement Aurora 64 / 66B encoding and decoding functions;

[0027] The GTX unit can automatically perform serial-to-parallel conversion of 10Gbps bandwidth data and clock recovery.

[0028] The beneficial effects achieved by this invention are:

[0029] The image transmission module provided by this invention is developed in Verilog language, and only two IPs are used in the entire program: FIFO (First In First Out) and GTX. When porting to different Xilinx 7 series FPGA platforms, only the GTX instantiation program needs to be modified, making it highly versatile and easy to port.

[0030] This invention provides a 10 Gigabit fiber optic image transmission technology. Based on Aurora 64 / 66B encoding, this method supports simultaneous transmission of up to six image streams with a bandwidth of up to 10 Gbps. The IP can encode the line and field signals, as well as the image data, into the optical fiber for transmission. Simultaneously, the IP can parse the received encoded data from the optical fiber back into the line and field signals, and the image data, thus achieving 10 Gigabit fiber optic image transmission. Compared to traditional 10 Gigabit Ethernet, this solution uses a simpler transmission protocol and achieves higher bandwidth utilization. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding is provided for an embodiment of the present invention;

[0032] Figure 2 A flowchart illustrating the image data alignment module in a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, provided for an embodiment of the present invention;

[0033] Figure 3 A flowchart illustrating the image encoding module in a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, provided for an embodiment of the present invention;

[0034] Figure 4 A flowchart illustrating the image decoding module in a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, provided for an embodiment of the present invention;

[0035] Figure 5 This is a flowchart illustrating the transceiver control module in a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, provided as an embodiment of the present invention. Detailed Implementation

[0036] The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings. The present invention includes, but is not limited to, the following embodiments.

[0037] This invention provides a 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, comprising a data alignment module, an image encoding module, an image decoding module, and a Gigabit Transceiver (GTX) module. It supports simultaneous transmission of up to six image channels, with each channel having identical processing logic. Each channel defaults to a 1920x1080 resolution image, but the supported image resolution for each channel can be modified by changing macro definitions.

[0038] The image data alignment module primarily locates the header of an image frame to ensure that the input to the image encoding module is a complete image frame. The image encoding module encodes multiple images according to priority, while the image decoding module reconstructs the received fiber optic data into a 16-bit standard image and image control horizontal and vertical field signals. The transceiver control module configures the Xilinx GTX module and controls its data transmission and reception.

[0039] The image alignment module is primarily responsible for finding the start of a line of image data, ensuring that the image input to the encoding module is a complete line. This module resolves the image misalignment problem caused when the image data from CameraLink is not a single line.

[0040] Image data includes the image clock signal Image_Clk, 16-bit YUV or RGB format image data Image_Data, the line valid signal HS, and the field valid signal VS.

[0041] like Figure 2 As shown, the image alignment unit uses Image_Clk as its module clock. The image alignment unit first delays the input Image_Data, HS, and VS by two Image_Clk clock cycles. The aligned image data and field signal are the delayed data. The line valid signal HS needs to be generated separately by the state machine. The state machine continuously captures the rising edge of the line valid signal HS. After capturing the rising edge, it sets the aligned field valid signal VS high and then enters the next state. This process continues until the falling edge of the input line valid signal HS is captured. After capturing the falling edge, the processed output line valid signal HS is set low, and the state machine returns to the original rising edge capture state. This process of cyclically processing the input line signal HS is repeated. VS and Image_Data are output directly after a two-clock-cycle delay.

[0042] like Figure 3 As shown, the image encoding module mainly encodes multiple images and transmits them through a single optical fiber. The image encoding module includes an image buffer unit, a FIFO polling encoding unit, an image data reading unit, and an image data encoding unit.

[0043] Since Image_Data is 16-bit data, while the GTX module requires 64-bit input data, and the Image clock (Image_Clk) and GTX clock are asynchronous, the image buffer unit primarily handles cross-clock data exchange and bit width conversion. Xilinx's official FIFO IP can achieve this functionality. Therefore, all six image buffers use FIFOs for data buffering. Because Image_Data is valid when both HS and VS are high, HS and VS are ANDed together as the FIFO's write signal. Image_Data is the FIFO's data input. Buffering the image before sending ensures data transmission continuity and enables bit width conversion. The FIFO is configured as 16-in, 64-out, converting the input 16-bit Image_Data into the 64-bit data required by the GTX module. The FIFO polling encoding unit monitors the number of data entries in the six buffer FIFOs in real time. For example, for an input image with a resolution of 1920x1080, when one line of image data is buffered in the image FIFO (i.e., the FIFO read count is greater than or equal to 1920 / 4 = 480), the transmit flag for that channel is set to 1. The image data reading unit state machine continuously queries the channel transmit flag. If a channel transmit flag is found to be set to 1, the data transmission logic for that channel is initiated. The required read signal rd_en for the FIFO is set high for 480 cycles using the GTX clock, and 480 64-bit image data entries are read from the buffer FIFOs. The image data encoding unit first writes a 64-bit data entry to the GTX module when the write valid signal s_axi_tx_tready is valid. This data includes the image's line count, frame count, and channel identification code. Then, it writes the 480 64-bit image data entries to the GTX module.

[0044] like Figure 4 As shown, the image decoding module mainly recovers image data from the data in the optical fiber. The image encoding module consists of an image channel identification polling unit, an image data extraction unit, an image data buffering unit, an image buffer data polling and buffering unit, an image data reading unit, and a line and field signal recovery unit.

[0045] The channel code identification polling buffer unit is responsible for identifying the channel identification code in the fiber optic data. When a channel data is detected, the line count and field frame count are stored in the buffer, and the original 64-bit image data is stored in the 64-bit in, 16-bit out FIFO of that channel. When the receive FIFO of that channel receives a line of image data, i.e., the FIFO read count is greater than or equal to 1920, the receive completion flag recv_end is set to 1.

[0046] After the image data extraction unit detects that recv_end is set to 1, it begins reading 1920 16-bit data entries buffered in the FIFO. During data reading, the row valid signal HS is set to 1, indicating that the image data is valid. The field valid signal VS is set to 1 when the row count is 0 and the row signal HS is high, and is set to 0 on the falling edge of the row signal when the row count reaches 1080. This method extracts the image data from the raw data received from the channel polling module according to the protocol, and aligns HS, VS, and Image_Data.

[0047] like Figure 5 As shown, the transmit / receive control module mainly implements GTX transmit / receive control, Aurora64 / 66B encoding, and parallel-to-serial conversion functions. The GTX control module includes a reset control unit, a clock management unit, a scrambling encoding unit, a descrambling unit, and a GTX unit.

[0048] The reset control unit controls the entire GTX reset function. This module uses the user clock UserClk output from the GTX IP as the clock counter. Since the GTX module reset is a high reset, the reset signal is set to 0 when the count value is in the range of 1000, set to 1 when the count value is in the range of 1000 to 4000, and set to 0 when the count value is greater than 4000, thus completing the GTX module reset logic.

[0049] The clock management unit takes the external crystal oscillator input as the master clock and uses the Xilinx official clk_wiz IP core to generate the operating clocks required by various modules in the program. These mainly include the 100MHz reference clock required by the GTX IP core and the 74.25MHz clock required for image restoration.

[0050] The scrambling and descrambling units implement Aurora 64 / 66B encoding and decoding functions, using X58+X39+1 scrambling units for both encoding and decoding. The GTX unit uses Xilinx's official IP, with its bandwidth set to 10Gbps. This IP can automatically perform serial-to-parallel conversion of 10Gbps bandwidth data, as well as clock recovery and other functions.

[0051] This invention is not limited to the specific embodiments described above. Those skilled in the art can implement this invention using various other specific embodiments based on the disclosed content of the embodiments and accompanying drawings. Therefore, any design that adopts the design structure and concept of this invention and makes some simple changes or modifications falls within the protection scope of this invention.

Claims

1. A 10 Gigabit image transmission module based on Aurora 64 / 66B encoding, characterized in that, The 10 Gigabit image transmission module based on Aurora64 / 66B encoding includes a data alignment module, an image encoding module, an image decoding module, and a transceiver control module. The data alignment module is used to find the data header of a frame of image data to ensure that the input to the image encoding module is a complete frame of image; the output of the data alignment module is connected to the image encoding module. The image encoding module encodes multiple images according to priority; the output of the image encoding module is connected to the transceiver control module. The image decoding module can recover the received fiber optic data into a 16-bit standard image and image control line and field signals; the input end of the image decoding module is connected to the transceiver control module. The transceiver control module completes the configuration of the Xilinx GTX module and controls the data transmission and reception of the GTX module. The data alignment module includes an image clock signal, 16-bit YUV or RGB format image data, a line valid signal, and a field valid signal. The data alignment module uses the image clock signal as its module clock. First, the input image data, line valid signal, and field valid signal are all delayed by two clock cycles of the image clock signal. After alignment, the image data and field valid signal are the delayed data. The line valid signal is generated separately by a state machine. The state machine continuously captures the rising edge of the line valid signal. After capturing the rising edge, it sets the output aligned field valid signal to a high level and then enters the next state. This continues until the falling edge of the input line valid signal is captured. After capturing the falling edge, the processed output line valid signal is set low, and the state machine returns to the original rising edge capture state. This process is repeated to process the input line valid signal. The field valid signal and image data are directly output after a two-clock-cycle delay. The image encoding module includes an image buffer unit, a FIFO polling encoding unit, an image data reading unit, and an image data encoding unit; The image buffer unit ANDs the row valid signal and the field valid signal as the write signal for the image buffer unit; the image data is the data input for the image buffer unit; The FIFO polling encoding unit monitors the number of data in multiple image buffer units in real time. When any channel image buffer unit has a row of image data buffered, the transmission flag of that channel is set to 1. The state machine of the image data reading unit continuously queries the transmission flags of each channel of the image buffer unit. If a transmission flag of a certain channel is found to be set to 1, the transmission of data through that channel is started: the read signal required by the image data reading unit is set to a high level for a preset period using the clock of the transceiver control module, and the image data in the buffer image data reading unit is read in the same number of preset periods. The image data encoding unit first writes a 64-bit data to the transceiver control module when the write valid signal is valid. This data includes the image's line count, frame count, and channel identification code. Then, it writes the corresponding number of 64-bit image data for each line of image data to the transceiver control module.

2. The 10 Gigabit image transmission module based on Aurora 64 / 66B encoding according to claim 1, characterized in that, The image buffer unit is configured with 16-bit input and 64-bit output.

3. The 10 Gigabit image transmission module based on Aurora 64 / 66B encoding according to claim 1, characterized in that, The image decoding module comprises an image channel identification polling unit, an image data extraction unit, an image data caching unit, an image cache data polling and caching unit, an image data reading unit, and a line and field signal recovery unit; The image channel identification polling unit is responsible for identifying the channel identification code in the optical fiber data. When a certain channel data is identified in the optical fiber data, the line count and field frame count are stored in the buffer, and the original 64-bit image data is stored in the 64-bit input and 16-bit output FIFO of that channel. When the receiving FIFO of that channel receives a line of image data, the receiving completion flag is set to 1. After the image data extraction unit finds that the reception completion flag is set to 1, it starts reading the 16-bit data corresponding to one row of image data buffered in the FIFO. During the data reading, the row valid signal HS is set to 1; the field valid signal is set to 1 when the row count is 0 and the row signal is high, and VS is set to 0 on the falling edge of the row signal when the row count is the row of image data.

4. The 10 Gigabit image transmission module based on Aurora 64 / 66B encoding according to claim 3, characterized in that, The transceiver control module includes a reset control unit, a clock management unit, a scrambling code encoding unit, a descrambling code unit, and a GTX unit; The reset control unit uses the user clock output by the GTX unit as the clock count. If the count value is within 1000, the reset signal is set to 0; if it is within 1000 to 4000, the reset signal is set to 1; and if it is greater than 4000, the reset signal is set to 0. The clock management unit then uses the external crystal oscillator input main clock through the Xilinx clk_wiz IP core to generate the running clock required by each module in the program; The scrambling and descrambling units implement Aurora 64 / 66B encoding and decoding functions; The GTX unit can automatically perform serial-to-parallel conversion of 10Gbps bandwidth data and clock recovery.

Images