Semiconductor structure and method of manufacturing the same

Abstract

This application provides a semiconductor structure and its fabrication method to solve the technical problem of reliable electrical performance of semiconductor structures. The fabrication method includes: providing a substrate, the substrate including a transistor structure; forming a stacked structure on the substrate, the stacked structure including a dielectric layer and an insulating layer sequentially stacked along the thickness direction of the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate; forming a through-hole in the stacked structure to expose the source / drain of the transistor structure; etching at least a portion of the sidewalls of the through-hole in the dielectric layer, and forming conductive holes in the insulating layer and the dielectric layer; wherein the diameter of the middle portion of the conductive hole is larger than the diameter of the two ends. This application can reduce the resistance of the conductive plugs formed in the conductive holes, thereby improving the reliability of the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device that consists of many repeating memory cells. Each memory cell typically includes a transistor and a capacitor. The gate of the transistor is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the capacitor.

[0003] As semiconductor chips continue to develop and their critical dimensions continue to shrink, when fabricating conductive plugs in the peripheral circuit area, a mask layer is usually first set on the stacked structure on the substrate. Using the patterned mask layer as a mask, conductive holes are formed on the stacked structure through a dry etching process. The conductive holes expose the source or drain of the transistor structure on the substrate. Conductive material is deposited in the conductive holes to form conductive plugs, so as to electrically connect with the source / drain of the transistor structure through the conductive plugs.

[0004] However, due to limitations in transistor size and process technology, the conductive holes produced in related technologies have small aperture sizes, resulting in high resistance of the conductive plugs formed within the conductive holes, which in turn leads to poor electrical performance reliability of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which can reduce the resistance of the conductive plug formed in the conductive hole, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] The first aspect of this application provides a method for fabricating a semiconductor structure, including:

[0008] A substrate is provided, the substrate comprising a transistor structure;

[0009] A stacked structure is formed on the substrate, the stacked structure including a dielectric layer and an insulating layer sequentially stacked along the thickness direction of the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate;

[0010] Through-holes are formed in the stacked structure to expose the source / drain of the transistor structure;

[0011] The via is etched to form at least a portion of the sidewalls in the dielectric layer, thereby forming a conductive via in the insulating layer and the dielectric layer; wherein the diameter of the conductive via is larger in the middle portion than that at both ends.

[0012] In some alternative embodiments, etching at least a portion of the sidewalls of the via located in the dielectric layer, the step of forming a conductive via in the insulating layer and the dielectric layer includes:

[0013] The through-hole is etched by a dry etching gas at least a portion of its sidewalls located in the dielectric layer, wherein the gas flow rate of the dry etching gas in the middle of the through-hole is greater than the gas flow rate at both ends of the through-hole.

[0014] In some optional embodiments, the dry etching gas includes a main etching gas, ammonia, and an inert gas, wherein the flow rate ratio of the main etching gas, ammonia, and inert gas is 4:4:1 to 2:2:1.

[0015] In some alternative embodiments, the main etching gas is a fluorine-containing gas.

[0016] In some alternative embodiments, when the sidewalls of the via are etched by the dry etching gas, the etching selectivity ratio of the dielectric layer to the insulating layer is greater than 10:1.

[0017] In some alternative embodiments, the etching time of at least a portion of the sidewalls of the via located in the dielectric layer by the dry etching gas is 20s to 30s.

[0018] In some alternative embodiments, prior to etching at least a portion of the sidewalls of the via located in the dielectric layer using the dry etching gas, the method further includes:

[0019] Oxygen is introduced into the through hole to remove the adhesive layer formed on the sidewall of the through hole;

[0020] The byproducts of the reaction between oxygen and the adhesive layer, as well as the remaining adhesive layer, are removed by acid washing solution.

[0021] In some alternative embodiments, etching the via is located at least a portion of the sidewalls in the dielectric layer, and after forming the conductive via in the insulating layer and the dielectric layer, the method further includes:

[0022] A conductive plug is formed inside the conductive hole.

[0023] In some alternative embodiments, before forming a conductive plug within the conductive hole, the method further includes:

[0024] A barrier layer is formed on the wall of the conductive hole.

[0025] In some alternative embodiments, the step of forming a barrier layer on the wall of the conductive hole includes:

[0026] A metal layer is formed on the wall of the conductive hole, and the conductive hole is heat-treated to form an ohmic contact layer on the wall of the conductive hole.

[0027] A barrier layer is formed on the ohmic contact layer.

[0028] A second aspect of this application also provides a semiconductor structure, including:

[0029] Substrate, the substrate including a transistor structure;

[0030] A stacked structure is located on the substrate, the stacked structure comprising a dielectric layer and an insulating layer sequentially stacked along a direction perpendicular to the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate;

[0031] A conductive via penetrates the stacked structure to expose the source / drain of the transistor structure, wherein the space dimension of the middle portion of the conductive via is larger than the aperture dimensions at both ends.

[0032] In some optional embodiments, the difference between the aperture size of the middle portion of the conductive hole and the aperture size of the two ends of the conductive hole is 6nm to 7nm.

[0033] In some alternative embodiments, the middle portion of the conductive hole is close to the bottom surface of the insulating layer, and the distance between the widest part of the middle portion of the conductive hole and the bottom surface of the insulating layer is 1 / 2 to 1 / 3 of the height of the conductive hole.

[0034] In some alternative embodiments, a conductive plug is disposed within the conductive hole, and the conductive plug is connected to the source / drain of the transistor.

[0035] In some alternative embodiments, a barrier layer is further provided between the conductive plug and the wall of the conductive hole.

[0036] In some alternative embodiments, an ohmic contact layer is further provided between the barrier layer and the wall of the conductive hole.

[0037] In some alternative embodiments, the barrier layer is titanium nitride; and / or, the ohmic contact layer is a metal silicide layer.

[0038] Compared with related technologies, the semiconductor structure fabrication method provided in this application has at least the following advantages:

[0039] The method for fabricating a semiconductor structure provided in this application includes: providing a substrate, the substrate including a transistor structure; forming a stacked structure on the substrate, the stacked structure including a dielectric layer and an insulating layer sequentially stacked along the thickness direction of the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate; forming a through-hole in the stacked structure to expose the source / drain of the transistor structure; etching at least a portion of the sidewalls of the through-hole in the dielectric layer to form conductive holes in the insulating layer and the dielectric layer; wherein the diameter of the conductive hole in the middle portion is larger than the diameter of the holes at both ends. In the above scheme, by etching at least a portion of the sidewalls of the through-hole in the dielectric layer, the diameter of the conductive hole in the middle portion formed in the insulating layer and the dielectric layer is made larger than the diameter of the holes at both ends, thereby increasing the size of the conductive plug formed in the conductive hole, thereby reducing the resistance of the conductive plug, and thus improving the reliability of the electrical performance of the semiconductor structure.

[0040] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0043] Figures 2 to 7 This is a cross-sectional schematic diagram of the fabrication process of the semiconductor structure provided in the embodiments of this application.

[0044] Figure label:

[0045] 100 - Semiconductor structure; 110 - Substrate; 120 - Stacked structure; 121 - Dielectric layer; 122 - Insulating layer;

[0046] 123 - Through hole; 124 - Conductive hole; 130 - Conductive plug; 140 - Barrier layer; 150 - Ohmic contact layer;

[0047] 200 - Transistor structure; 210 - Gate; 211 - Gate sidewall insulating layer; 220 - Source / drain;

[0048] 300 - Mask layer; 400 - Initial mask layer; 410 - Initial mask base layer;

[0049] 420 - Initial mask pattern layer. Detailed Implementation

[0050] The inventors of this application discovered in their practical work that, with the continuous development of semiconductor chips, their critical dimensions are constantly decreasing. When fabricating conductive plugs in the peripheral circuit area, a mask layer is usually first set on a stacked structure on the substrate. The stacked structure includes a dielectric layer and an insulating layer (e.g., a silicon nitride layer) set on the dielectric layer. A patterned mask layer is then used as a mask, and a dry etching process is used to remove part of the stacked structure to form vias on the stacked structure. The vias expose the source or drain of the transistor structure on the substrate. The diameter of the prepared vias is small. A pickling solution is usually injected into the vias to remove byproducts in the vias and simultaneously expand the via area to form conductive holes. Then, conductive material is deposited in the conductive holes to form conductive plugs, which are then electrically connected to the source / drain of the transistor structure.

[0051] However, the pickling solution has a relatively low selectivity for etching the dielectric layer and the gate sidewall insulating layer located around the transistor gate. Etching the dielectric layer will also etch the gate sidewall insulating layer, resulting in a thinner gate sidewall insulating layer and a poorer isolation effect. Therefore, the pickling time should not be too long, but it will result in a smaller aperture size of the conductive hole. As a result, there is insufficient space for subsequent deposition of dielectric material, which leads to a large resistance of the conductive plug formed in the conductive hole, thus causing the technical problem of poor electrical performance reliability of the semiconductor structure.

[0052] To address the aforementioned issues, this application provides a semiconductor structure and its fabrication method. The fabrication method ensures that the space dimension of the middle portion of the formed conductive hole is larger than that at both ends, providing sufficient deposition space for subsequent dielectric materials to improve deposition efficiency, increase the size of the conductive plug, thereby reducing the resistance of the conductive plug and ultimately enhancing the reliability of the semiconductor structure's electrical performance.

[0053] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0054] The semiconductor structure provided in this application can be a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This application uses a DRAM memory device as an example for illustration.

[0055] Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in this application embodiment. Please refer to... Figure 1 The method for preparing a semiconductor structure provided in this application includes:

[0056] Step S101: Provide a substrate, the substrate including a transistor structure.

[0057] Substrate 110 provides a structural basis for subsequent structures and processes. The material of substrate 110 may include any or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator (SiI) substrate, and germanium-on-insulator (GDI) substrate. In the embodiments of this application, at least a portion of substrate 110 is a silicon substrate, and the silicon material may be single-crystal silicon. Substrate 110 can be prepared by chemical vapor deposition (CVD).

[0058] Please refer to Figure 2The substrate 110 includes multiple first active regions, on which multiple transistor structures 200 are disposed. These transistor structures 200 constitute a peripheral control circuit within the semiconductor structure. The peripheral control circuit is used to implement functions other than storing signals, such as storage logic, signal amplification and transmission, and clock control, in the DRAM memory device. Each transistor structure 200 includes a gate 210, a source, and a drain. The gate 210 of some transistor structures 200 can be connected to the transistor control voltage of the peripheral control circuit in the semiconductor structure 100. The source and drain of each transistor structure 200 are respectively connected to the transmission voltage of the peripheral control circuit in the semiconductor structure 100. Through the switching on and off of the array-embedded transistors, the peripheral control circuit uses the transmission voltage to realize the storage and retrieval of external signals to the memory cells.

[0059] The substrate includes an array region and a peripheral region, which are adjacent to each other. The transistor structure 200 is located in the peripheral region. The array region includes multiple word lines arranged in parallel and spaced apart along a first direction and multiple bit lines arranged in parallel and spaced apart along a second direction. The first and second directions are alternately arranged. The array region also includes multiple memory cells. Each memory cell includes a buried transistor located in the array region. The gate of the buried transistor in the array region is connected to the word line, the drain is connected to the bit line, and the source is connected to a capacitor that is subsequently fabricated. The voltage signal on the word line can control the opening or closing of the buried transistor in the array region, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor for storage through the bit line. A bit line isolation structure is provided between adjacent bit lines. The voltage signal of the word line and the data information transmitted by the bit line are both transmitted through the peripheral control circuit.

[0060] In this process, the metal portion of the gate 210 in the peripheral region transistor structure 200 and the metal portion of the bit line in the array region can be formed in the same step using the same material and the same process. Then, a gate sidewall insulating layer 211 is formed on the metal portion of the gate 210 in the peripheral region transistor structure 200 to electrically isolate the gate. Simultaneously, a bit line sidewall insulating layer is formed on the metal portion of the bit line in the array region to electrically isolate the bit line. The gate sidewall insulating layer 211 and the bit line sidewall insulating layer can be formed in the same step using the same material and the same process. Due to the process technology, the shape of the gate sidewall insulating layer 211 is, for example, [insert shape here]. Figure 1 The shape shown in Figure 1 In the process, the gate sidewall insulating layer 211 has an arc-shaped structure, and the radial dimension of the gate sidewall insulating layer 211 decreases sequentially from the bottom to the top.

[0061] Step S102: A stacked structure is formed on the substrate. The stacked structure includes a dielectric layer and an insulating layer stacked sequentially along the thickness direction of the substrate. The insulating layer is disposed on the side of the dielectric layer away from the substrate.

[0062] Please continue to refer to Figure 2 A dielectric layer 121 and an insulating layer 122 are sequentially formed on the substrate 110 by means of atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, wherein the insulating layer 122 is disposed on the side of the dielectric layer 121 facing away from the substrate 110.

[0063] The dielectric layer 121 may be made of an oxide material; the insulating layer 122 may be made of silicon nitride (SiN).

[0064] Step S103: Form a through-hole in the stacked structure to expose the source / drain of the transistor structure.

[0065] Please continue to refer to Figure 2 After forming the stacked structure 120 on the substrate 110, a mask layer 300 and an initial mask layer 400 are first formed on the stacked structure 120. The initial mask layer 400 is located on the side of the mask layer 300 away from the stacked structure 120. The mask layer 300 can be a spin-on hard mask (SOH), and its material can be a silicon-rich compound.

[0066] The initial mask layer 400 may include an initial mask base layer 410 and an initial mask pattern layer 420. The initial mask pattern layer 420 is located on the side of the initial mask base layer 410 facing away from the stacked structure 120. The initial mask base layer 410 may be formed using deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The material of the initial mask base layer 410 may be silicon oxynitride.

[0067] A photoresist layer can then be coated on the initial mask base layer 410. The material can be an organic compound that is sensitive to light (e.g., ultraviolet light), such as polyvinyl cinnamate. A mask with mask openings is then placed on the photoresist layer. Ultraviolet light passes through the mask and irradiates the photoresist surface to cause a chemical reaction in the exposed areas of the photoresist. The photoresist in the exposed areas (positive photoresist) or the photoresist in the unexposed areas (negative photoresist) is then dissolved and removed by a development technique, thereby forming the initial mask pattern layer 420.

[0068] Using the initial mask pattern layer 420 as a mask, the initial mask base layer 410 and the mask layer 300 are etched to transfer the pattern of the initial mask pattern layer 420 to the mask layer 300, forming a patterned mask layer 300. The pattern on the mask layer 300 corresponds to the shape, size, and position of the via 123 to be fabricated on the stacked structure 120. Using the patterned mask layer 300 as a mask, a dry etching process is employed to etch the stacked structure 120, forming vias 123 penetrating the stacked structure 120. Figure 3 As shown, a via 123 penetrating the stacked structure 120 exposes the source / drain 220 of the transistor structure 200 so that the conductive plug 130 subsequently formed in the via 123 can be electrically connected to the source / drain 220 of the transistor.

[0069] In some embodiments, the cross-sectional shape of the through hole 123 can be any shape such as circular, elliptical, or square. In the following embodiments, the cross-sectional shape of the through hole 123 will be described as circular.

[0070] After forming a through-hole 123 through the stacked structure 120, the mask layer 300 on the stacked structure 120 is removed to expose the surface of the stacked structure 120.

[0071] Step S104: Etch at least a portion of the sidewalls of the via located in the dielectric layer to form a conductive hole in the insulating layer and the dielectric layer; wherein the diameter of the conductive hole in the middle portion is larger than the diameter of the holes at both ends.

[0072] Please refer to Figures 5 to 7 As shown, at least a portion of the sidewalls of the via 123 located in the dielectric layer 121 are further etched so that the aperture size of the middle position of the conductive hole 124 is larger than the aperture size of the two ends, forming a structure shape such as a "dumbbell shape" to increase the surface area of ​​the via 123, thereby increasing the contact area of ​​the conductive plug 130 formed in the conductive hole 124 in subsequent processes, thereby reducing the resistance value of the conductive plug 130.

[0073] It should be noted that forming a conductive hole 124 in the insulating layer 122 and the dielectric layer 121 refers to forming a conductive hole 124 by further etching at least a portion of the sidewall of the via 123 located in the dielectric layer 121. The material of the insulating layer may include silicon nitride, etc.

[0074] In the above scheme, by further etching at least a portion of the sidewalls of the via 123 located in the dielectric layer 121, the aperture size of the middle part of the formed conductive hole 124 is larger than that of the two ends, thereby increasing the surface area of ​​the conductive hole 124. This increases the contact area of ​​the conductive plug 130 formed in the conductive hole 124 in subsequent processes, thereby reducing the resistance of the conductive plug 130 and improving the electrical performance of the semiconductor structure 100.

[0075] The following describes in detail, with reference to the accompanying drawings, the specific steps of etching the via 123 located on at least a portion of the sidewalls in the dielectric layer 121 to form a conductive hole 124 in the insulating layer 122 and the dielectric layer 121; wherein the diameter of the conductive hole 124 in the middle portion is larger than the diameter of the holes at both ends.

[0076] In this embodiment, after forming a via 123 on the stacked structure 120 using a dry etching process, elements such as fluorine (F) and carbon (C) in the dry etching gas react with the silicon material in the stacked structure 120 to form byproducts such as polymers. These byproducts have strong adhesion and adhere to the hole wall of the via 123 to form an adhesion layer. Therefore, in this embodiment, after forming the via 123 on the stacked structure 120, oxygen (O2) can be introduced into the via 123 first, so that the adhesion layer reacts with the oxygen to form byproducts that are not easily adhered to the hole wall.

[0077] Please refer to Figure 4 As shown, after oxygen is introduced into the via 123, the byproducts resulting from the reaction between oxygen and the adhesive layer, as well as the remaining adhesive layer, can be removed by an acid pickling solution. For example, the acid pickling solution can be a mixture of hydrogen peroxide and hydrofluoric acid, wherein the etching selectivity ratio of the adhesive layer and byproducts relative to the gate sidewall insulating layer 211 can be 3 to 5:1 or higher. By controlling the pickling time, it is possible to avoid the gate sidewall insulating layer 211 being essentially unetched while removing the byproducts and remaining adhesive layer from the reaction between oxygen and the adhesive layer, thus preventing an increase in leakage current at the gate 210.

[0078] In addition, by removing the byproducts and remaining adhesive layer after the reaction of oxygen with the adhesive layer by the pickling solution, the aperture size of the via 123 can be further increased, providing space for subsequent dielectric material deposition. This increases the contact area of ​​the conductive plug 130 formed in the via 123, thereby reducing the resistance value of the conductive plug 130 and improving the reliability of the electrical performance of the semiconductor structure.

[0079] Next, please refer to Figure 5As shown, in some embodiments, at least a portion of the sidewalls of the via 123 located in the dielectric layer 121 can be etched by dry etching gas, wherein the gas flow rate of the dry etching gas in the middle part of the via 123 is greater than the gas flow rate at both ends of the via 123.

[0080] It is understandable that by increasing the gas flow rate of the dry etching gas in the middle of the via 123 compared to the two ends, the etching amount in the middle of the via 123 is increased. This results in a higher etching rate in the middle of the via 123 compared to the two ends, thereby allowing the diameter of the formed conductive via 124 in the middle to be larger than that at the two ends. Different kinetic energies can be applied to the dry etching gas by controlling the gas temperature, causing the gas to move downwards and remain at different locations within the via 123 for reaction.

[0081] The middle part of the through hole 123 can be located at 1 / 2 to 1 / 3 of the height of the conductive hole 124 from top to bottom.

[0082] In some embodiments, the dry etching gas includes a main etching gas, ammonia, and an inert gas. The main etching gas can be a fluorine (F)-containing gas, for example, a mixture of fluorine hydride (HF) and hydrogen nitride (NH3). The inert gas can be argon. It is understood that the inert gas can provide a certain amount of ion bombardment to adjust the etching rate according to specific needs.

[0083] In some embodiments, the flow rate ratio of the main etching gas, ammonia, and inert gas can be 4:4:1 to 2:2:1. For example, the flow rate ratio of the main etching gas, ammonia, and inert gas is 4:4:1; or, the flow rate ratio of the main etching gas, ammonia, and inert gas is 3:3:1; or, the flow rate ratio of the main etching gas, ammonia, and inert gas is 2:2:1. The specific ratio can be adapted to actual needs and is not specifically limited here.

[0084] The dry etching gas is introduced for 20-30 seconds, which ensures the area in the middle of the conductive hole 124 and avoids further etching of the dielectric layer 121 due to excessive time, which would cause the conductive hole 124 to become skewed and be detrimental to subsequent deposition.

[0085] In some embodiments, when the sidewalls of the via 123 are etched with a dry etching gas, the etching selectivity ratio of the dielectric layer 121 to the insulating layer 122 is greater than 10:1, for example, 15:1, 20:1, 50:1, 100:1, etc. Thus, by selecting a dry etching gas with a high etching selectivity ratio and controlling the etching time of the sidewalls of the conductive via 124, the size of the via 123 in the insulating layer 122 can remain essentially unchanged, while the hole walls of the via 123 in the dielectric layer 121 will be further etched by the dry etching gas, increasing the size of the via 123 in the dielectric layer 121. Furthermore, by controlling the amount of dry etching gas entering the via 123 in the dielectric layer 121... The flow rate is adjusted so that different positions of the via 123 in the dielectric layer 121 can have different etching amounts. For example, the flow rate of the dry etching gas on the side of the via 123 in the dielectric layer 121 near the insulating layer 122 is greater than the flow rate of the dry etching gas on the side of the via 123 in the dielectric layer 121 near the substrate 110. This makes the aperture size of the middle part of the formed conductive hole 124 larger than the aperture size at both ends. This avoids damage to the gate sidewall insulating layer 211 and increases the surface area of ​​the conductive hole 124, thereby increasing the contact area of ​​the conductive plug 130 formed in subsequent processes, reducing the resistance value of the conductive plug 130, and thus improving the reliability of the electrical performance of the semiconductor structure 100.

[0086] Furthermore, since the insulating layer 122 is basically not etched when the dry etching gas is used to etch the dielectric layer 121, when the dry etching gas enters the via 123, the insulating layer 122 at the top of the dielectric layer 121 will block the dry etching gas, causing it to be buffered or its direction of movement to change and accumulate below the insulating layer 122. This further increases the flow rate of the dry etching gas in the middle part of the via 123 (i.e., the end of the dielectric layer 121 near the insulating layer 122), thereby increasing the etching amount in the middle part of the via 123. Meanwhile, the end of the via 123 near the substrate 110 is basically not etched, resulting in the diameter of the middle part of the final conductive hole 124 being larger than the diameter of the two ends.

[0087] In some embodiments, the etching time of the dry etching gas on at least a portion of the sidewalls of the via 123 located in the dielectric layer 121 can be 20s to 30s. By controlling the etching time of the dry etching gas on at least a portion of the sidewalls of the via 123 located in the dielectric layer 121, the etching accuracy of the via 123 can be further precisely controlled, ensuring that the insulating layer 122 and the bottom of the via 123 are basically not etched, thereby improving the dimensional accuracy of the formed conductive hole 124.

[0088] For example, the etching time of at least part of the sidewall of the via 123 located in the dielectric layer 121 by the dry etching gas can be 20s, 25s, 28s, 30s, etc. The specific time can be adapted according to the actual situation, and no specific limitation is made here.

[0089] In some embodiments, the dry etching gas can be a mixture of HF and NH3, with an etching selectivity ratio of, for example, 20:1 and an etching duration of 26 s. When the dry etching gas etches the sidewalls of the conductive via 124, the specific reaction mechanism is as follows:

[0090] SiO2+4HF+4NH3→SiF4+2H2O+4NH3 (1)

[0091] SiF4+2HF+2NH3→(NH4)2SiF6 (2)

[0092] (NH4)2SiF6→SiF4+2NH3+2HF (3)

[0093] As can be seen from the above scheme, by introducing fluorine-containing dry etching gas into the via 123 for a time between 20 and 30 seconds, such as 26 seconds, the etching time and etching selectivity are controlled to ensure that the insulating layer 122 on the dielectric layer 121 and the gate sidewall insulating layer 211 are hardly etched during the etching process. This achieves a more ideal size for the conductive via 124 without affecting other properties of the semiconductor structure 100. Furthermore, due to the obstruction of the insulating layer 122 on top of the dielectric layer 121 during etching, the dry etching process... The etching gas is buffered or its movement direction is changed and it accumulates below the insulating layer 122, which increases the flow rate of dry etching gas in the middle part of the via 123 (i.e., the end of the dielectric layer 121 near the insulating layer 122). This increases the etching amount in the middle part of the via 123, so that the aperture size of the middle part of the final conductive hole 124 is larger than that at both ends. For example, the difference between the widest aperture size in the middle part of the conductive hole 124 and the aperture size at both ends of the conductive hole 124 is about 6nm to 7nm.

[0094] Since the dry etching gas will react with the silicon material in the dielectric layer 121 to form some byproducts when at least part of the sidewalls of the dielectric layer 121 is etched using dry etching gas, after the conductive hole 124 is formed in the dielectric layer 121 and the insulating layer 122, oxygen can be introduced into the conductive hole 124 so that the oxygen reacts with the byproducts to form byproducts that are not easy to adhere. Then, an acid pickling solution is introduced into the conductive hole 124 to remove the byproducts on the bottom wall and sidewalls of the conductive hole 124. At the same time, by introducing the acid pickling solution for a short time, the sidewalls of the conductive hole 124 can be further made smooth, thereby increasing the surface area of ​​the conductive hole 124.

[0095] In some embodiments, after removing byproducts formed on the hole walls (i.e., the bottom and sidewalls of the conductive hole 124) by pickling solution, a metal layer can be formed on the hole walls of the conductive hole 124, and the conductive hole 124 can be heat-treated to form an ohmic contact layer 150 on the hole walls of the conductive hole 124, such as... Figure 6 As shown, the material of the ohmic contact layer 150 can be a metal silicide.

[0096] It is understandable that by forming an ohmic contact layer 150 on the wall of the conductive hole 124, the contact resistance between the conductive plug 130 formed in the conductive hole 124 and the source / drain 220 in subsequent processes can be reduced.

[0097] Please continue to refer to Figure 6 After forming an ohmic contact layer 150 on the wall of the conductive hole 124, a barrier layer 140 is formed on the ohmic contact layer 150.

[0098] Among them, an atomic layer deposition process or a CVD process can be used to form a barrier layer 140 on the ohmic contact layer 150, and the material of the barrier layer 140 can be titanium nitride (TiN).

[0099] It is understood that by forming a barrier layer 140 in the conductive hole 124, ion diffusion between the conductive plug 130 formed in the conductive hole 124 and the dielectric layer 121 in subsequent processes can be avoided.

[0100] After forming the barrier layer 140 in the conductive via 124, the process includes: depositing a conductive metal material within the conductive via 124 to form a conductive plug 130, such as... Figure 7 As shown, the source / drain 220 is electrically connected to a structure such as a capacitor or bit line via the conductive plug 130.

[0101] The conductive plug 130 can be made of conductive materials such as tungsten (W).

[0102] In addition, while depositing conductive metal material in the conductive holes, conductive metal material is also deposited in the array region, such as between adjacent bit lines, in the same process. After depositing conductive metal material between adjacent bit lines, it is patterned to form capacitor pads, so that the capacitors subsequently fabricated can be electrically connected to the array region embedded transistors through capacitor plugs and capacitor pads.

[0103] Please continue to refer to Figure 6 and Figure 7 This application also provides a semiconductor structure 100, including: a substrate 110, a stacked structure 120 and a conductive via 124; wherein, the substrate 110 can be a single-layer structure or a multi-layer composite structure; the substrate 110 includes a transistor structure 200, and the transistor includes a gate 210, a source and a drain.

[0104] The stacked structure 120 is located on the substrate 110. The stacked structure 120 includes a dielectric layer 121 and an insulating layer 122 stacked sequentially along a direction perpendicular to the substrate 110. The insulating layer 122 is disposed on the side of the dielectric layer 121 facing away from the substrate 110.

[0105] The conductive via 124 penetrates the stacked structure 120 to expose the source / drain 220 of the transistor structure 200, wherein the aperture size of the middle part of the conductive via 124 is larger than the aperture size of the two ends.

[0106] In the above scheme, by making the aperture size of the middle part of the conductive hole 124 larger than that of the two ends, the surface area of ​​the conductive hole 124 can be increased, providing sufficient space for subsequent dielectric material deposition. This increases the contact area of ​​the conductive plug 130 formed in the conductive hole 124, reduces the resistance of the conductive plug 130, and improves the reliability of the electrical performance of the semiconductor structure 100.

[0107] The cross-sectional shape of the conductive hole 124 can be any shape such as a circle, ellipse, square, or regular polygon. In this embodiment, the cross-sectional shape of the conductive hole 124 is described as a circle.

[0108] In some embodiments, the difference between the aperture size of the widest part of the middle portion of the conductive hole 124 and the aperture size of the two ends of the conductive hole 124 is, for example, 6nm to 7nm. For example, the difference between the aperture size of the widest part of the middle portion of the conductive hole 124 and the aperture size of the two ends of the conductive hole 124 is, for example, 6nm, 6.2nm, 6.5nm, 6.8nm, 7nm, etc.

[0109] In some embodiments, the direction from the insulating layer 122 to the substrate 110 (i.e. Figure 6(From top to bottom) The middle part of the conductive hole 124 is at 1 / 2 to 1 / 3 of the height of the conductive hole 124, that is, the distance between the widest part of the middle part of the conductive hole 124 and the bottom surface of the insulating layer 122 is 1 / 2 to 1 / 3 of the height of the conductive hole 124. For example, the distance between the widest part of the middle part of the conductive hole 124 and the bottom surface of the insulating layer 122 is 1 / 2 or 1 / 3 of the height of the conductive hole 124, so that the diameter of the middle part of the conductive hole 124 is larger than that at both ends, thereby increasing the surface area of ​​the conductive hole 124. This increases the contact area of ​​the conductive plug 130 formed in the conductive hole 124, reduces the resistance of the conductive plug 130, and improves the reliability of the electrical performance of the semiconductor structure 100.

[0110] In some embodiments, a conductive plug 130 is provided in the conductive hole 124. The material of the conductive plug 130 may include conductive materials such as tungsten metal, so that the conductive plug 130 is electrically connected to the source / drain 220 of the transistor structure 200 exposed in the conductive hole 124.

[0111] Specifically, the conductive hole 124 exposes the source / drain 220 of the transistor structure 200 in the substrate 110. After the conductive plug 130 is formed in the conductive hole 124, the conductive plug 130 is electrically connected to the source / drain 220. In this way, the source / drain 220 of the transistor structure 200 can be electrically connected to the capacitor or bit line through the conductive plug 130.

[0112] In some embodiments, please continue to refer to Figure 6 A barrier layer 140 is provided between the conductive plug 130 and the hole wall of the conductive hole 124. The barrier layer 140 can be a titanium nitride (TiN) layer to prevent ion diffusion between the conductive plug 130 and the dielectric layer 121.

[0113] In order to reduce the contact resistance between the conductive plug 130 and the source / drain 220, in this embodiment of the application, an ohmic contact layer 150 is also provided between the barrier layer 140 and the hole wall of the conductive hole 124. The material of the ohmic contact layer 150 can be a metal silicide, so as to reduce the contact resistance of the conductive plug 130 through the ohmic contact layer 150.

[0114] The semiconductor structure and its fabrication method provided in this application embodiment include: providing a substrate, the substrate including a transistor structure; forming a stacked structure on the substrate, the stacked structure including a dielectric layer and an insulating layer sequentially stacked along the thickness direction of the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate; forming a through-hole in the stacked structure to expose the source / drain of the transistor structure; etching at least a portion of the sidewalls of the through-hole in the dielectric layer to form conductive holes in the insulating layer and the dielectric layer; wherein the diameter of the conductive hole in the middle portion is larger than the diameter of the holes at both ends. In the above scheme, by etching at least a portion of the sidewalls of the through-hole in the dielectric layer, the diameter of the conductive hole in the middle portion formed in the insulating layer and the dielectric layer is made larger than the diameter of the holes at both ends, thereby increasing the size of the conductive plug formed in the conductive hole, thereby reducing the resistance of the conductive plug, and thus improving the reliability of the electrical performance of the semiconductor structure.

[0115] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, the substrate comprising a transistor structure; A multilayer structure is formed on the substrate; The stacked structure includes a dielectric layer and an insulating layer stacked sequentially along the thickness direction of the substrate, wherein the insulating layer is disposed on the side of the dielectric layer facing away from the substrate; Through-holes are formed in the stacked structure to expose the source / drain of the transistor structure; The via is etched to form at least a portion of the sidewalls in the dielectric layer, thereby forming a conductive via in the insulating layer and the dielectric layer; wherein the diameter of the conductive via is larger in the middle portion than that at both ends.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The step of etching at least a portion of the sidewalls of the via located in the dielectric layer to form a conductive via in the insulating layer and the dielectric layer includes: The through-hole is etched by a dry etching gas at least a portion of its sidewalls located in the dielectric layer, wherein the gas flow rate of the dry etching gas in the middle of the through-hole is greater than the gas flow rate at both ends of the through-hole.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The dry etching gas includes: main etching gas, ammonia and inert gas, and the flow rate ratio of the main etching gas, ammonia and inert gas is 4:4:1 to 2:2:1; The main etching gas is a fluorine-containing gas.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, When the sidewall of the via is etched using the dry etching gas, the etching selectivity ratio of the dielectric layer to the insulating layer is greater than 10:

1.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The etching time for at least a portion of the sidewalls of the via located in the dielectric layer by the dry etching gas is 20s to 30s.

6. The method of claim 2, wherein the semiconductor structure is formed by a method comprising: Before etching at least a portion of the sidewalls of the via located in the dielectric layer using the dry etching gas, the process further includes: Oxygen is introduced into the through hole to remove the adhesive layer formed on the sidewall of the through hole; The byproducts of the reaction between oxygen and the adhesive layer, as well as the remaining adhesive layer, are removed by acid washing solution.

7. The method of producing a semiconductor structure according to any one of claims 1 to 3, wherein Etching the via is performed on at least a portion of the sidewalls located in the dielectric layer. After forming the conductive via in the insulating layer and the dielectric layer, the process further includes: A conductive plug is formed inside the conductive hole.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Before forming the conductive plug within the conductive hole, the method further includes: A barrier layer is formed on the wall of the conductive hole.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The step of forming a barrier layer on the wall of the conductive hole includes: A metal layer is formed on the wall of the conductive hole, and the conductive hole is heat-treated to form an ohmic contact layer on the wall of the conductive hole. A barrier layer is formed on the ohmic contact layer.

10. A semiconductor structure, characterized by include: Substrate, the substrate including a transistor structure; A stacked structure is located on the substrate, the stacked structure comprising a dielectric layer and an insulating layer sequentially stacked along a direction perpendicular to the substrate, the insulating layer being disposed on the side of the dielectric layer facing away from the substrate; A conductive via penetrates the stacked structure to expose the source / drain of the transistor structure, wherein the diameter of the conductive via in the middle is larger than the diameter of the via at both ends.

11. The semiconductor structure of claim 10, wherein, The difference between the diameter of the middle part of the conductive hole and the diameter of the two ends of the conductive hole is 6nm~7nm.

12. The semiconductor structure of claim 10, wherein, The middle part of the conductive hole is close to the bottom surface of the insulating layer, and the distance between the widest part of the middle part of the conductive hole and the bottom surface of the insulating layer is 1 / 2 to 1 / 3 of the height of the conductive hole.

13. The semiconductor structure of claim 10, wherein, A conductive plug is disposed in the conductive hole, and the conductive plug is connected to the source / drain of the transistor structure.

14. The semiconductor structure of claim 13, wherein, A barrier layer is also provided between the conductive plug and the wall of the conductive hole.

15. The semiconductor structure of claim 14, wherein, An ohmic contact layer is also provided between the barrier layer and the hole wall of the conductive hole. The barrier layer is a titanium nitride layer; and / or, the ohmic contact layer is a metal silicide layer.

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