Semiconductor structure and method of forming the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate, the substrate comprises active strips and first grooves which are arranged alternately along a second direction and extend along a first direction; the first direction and the second direction are any two directions in a plane where the substrate is located; forming an isolation structure which extends along the first direction at the bottom of the first groove; wherein the isolation structure and the active strips have a first gap in the projection area along the second direction; forming a bit line structure in the first gap.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Currently, miniaturization is achieved by forming Dynamic Random Access Memory (DRAM) with embedded bit line structures to improve the integration density of DRAM.

[0003] However, in related technologies, a groove is formed by etching the bottom of the active post and filling the groove with bit line metal material to form an embedded bit line structure. Therefore, in related technologies, the active post is prone to collapse during the etching process. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided, the substrate comprising active strips and a first trench extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within the plane of the substrate;

[0007] An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area along the second direction;

[0008] A bitline structure is formed in the first gap.

[0009] In some embodiments, the substrate includes a substrate and a first isolation layer located on the surface of the substrate;

[0010] The first isolation layer includes a semiconductor isolation layer and / or an insulating layer, the semiconductor isolation layer and / or the insulating layer being used to isolate the bit line structure from the substrate.

[0011] In some embodiments, the semiconductor isolation layer includes at least a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer;

[0012] The active strip is located on the surface of the first N-type semiconductor layer.

[0013] In some embodiments, the first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps:

[0014] A first initial semiconductor layer is formed on the surface of the substrate;

[0015] The first initial semiconductor layer is subjected to a first heavy doping to form the first P-type semiconductor layer;

[0016] A second initial semiconductor layer is formed on the surface of the first P-type semiconductor layer;

[0017] The second initial semiconductor layer is subjected to a second doping to form the first N-type semiconductor layer.

[0018] In some embodiments, the substrate is a P-type doped substrate, and the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, wherein the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.

[0019] In some embodiments, the active strip includes a third semiconductor layer located within the projection region of the first gap along the second direction. After forming the isolation structure, the method further includes:

[0020] The third semiconductor layer is etched along the second direction to form a third sub-semiconductor layer; wherein, the isolation structure and the third sub-semiconductor layer have a second gap in the projection region along the second direction, and the second gap includes the first gap;

[0021] The bit line structure is formed in the second gap.

[0022] In some embodiments, the isolation structure is convex in shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure; the isolation structure is formed by the following steps:

[0023] A first initial isolation structure is formed on the surface of the active strip and the inner wall of the first trench;

[0024] The second isolation structure is formed at the bottom of the first trench having the first initial isolation structure;

[0025] The first initial isolation structure is etched back to form the first U-shaped isolation structure; the top surface of the second isolation structure extends beyond the top surface of the first U-shaped isolation structure.

[0026] In some embodiments, after forming the bit line structure, the method further includes:

[0027] The active strip in the projection region of the bit line structure along the second direction is doped to form a drain portion.

[0028] In some embodiments, after forming the bit line structure, the method further includes:

[0029] The bit line structure and the active strip are heat-treated to form a metal silicide located between the bit line structure and the active strip.

[0030] In some embodiments, the method further includes:

[0031] A third isolation structure is formed by covering the surface of the bit line structure and the surface of the second isolation structure.

[0032] The top surface of the third isolation structure does not extend beyond the top surface of the active strip.

[0033] In some embodiments, a fourth isolation structure is formed on the surface of the third isolation structure;

[0034] The top surface of the fourth isolation structure is flush with the top surface of the active strip.

[0035] In some embodiments, the active strip and the first trench are formed by the following steps:

[0036] A semiconductor active layer is formed on the surface of the first N-type semiconductor layer;

[0037] A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction, the first sub-patterns exposing a portion of the semiconductor active layer;

[0038] By passing through the first mask layer, a portion of the semiconductor active layer exposed by the first sub-pattern is removed, forming the active strips and the first trench that extend along the first direction and are alternately arranged along the second direction.

[0039] In some embodiments, the method further includes: forming a second mask layer having a second pattern on the surfaces of the active strip and the fourth isolation structure; the second pattern includes a plurality of second sub-patterns extending along the second direction and arranged along the first direction, the second sub-patterns exposing a portion of the active strip and a portion of the fourth isolation structure;

[0040] The active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched through the second mask layer, or the active strips and all of the fourth isolation structure exposed by the second sub-pattern are etched to form a second trench and an active isolation layer alternately arranged along the first direction; wherein the size of the second trench along a third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched fourth isolation structures alternately arranged along the second direction;

[0041] The active columns are insulated from each other;

[0042] A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not extend beyond the top surface of the active post.

[0043] In some embodiments, the method further includes: doping a portion of the active pillar located outside the projection region of the word line structure along the first direction to form a source portion;

[0044] A capacitor structure connected to the source electrode is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked sequentially.

[0045] In a second aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising:

[0046] The substrate includes drain portions and isolation structures extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within the plane of the substrate.

[0047] The bit line structure is located between the isolation structure and the drain portion.

[0048] In some embodiments, the substrate includes a substrate and a first isolation layer located on the surface of the substrate;

[0049] The first isolation layer includes a semiconductor isolation layer and / or an insulating layer, the semiconductor isolation layer and / or the insulating layer being used to isolate the bit line structure from the substrate.

[0050] In some embodiments, the semiconductor isolation layer includes at least a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the drain portion is located on the surface of the first N-type semiconductor layer.

[0051] In some embodiments, the substrate is a P-type doped substrate, and the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, wherein the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.

[0052] In some embodiments, the isolation structure is convex in shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure, and the top surface of the second isolation structure extends beyond the top surface of the first U-shaped isolation structure;

[0053] Both the first U-shaped isolation structure and the second isolation structure are in contact with the bit line structure.

[0054] In some embodiments, the semiconductor structure further includes:

[0055] A third isolation structure is located on the surfaces of the bit line structure and the second isolation structure.

[0056] In some embodiments, the semiconductor structure further includes:

[0057] The metal silicide located between the bit line structure and the drain portion.

[0058] In some embodiments, the semiconductor structure further includes: an active pillar located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and a word line structure located on the sidewall of the active pillar, arranged along the first direction and extending along the second direction.

[0059] The top surface of the word line structure does not extend beyond the top surface of the active column.

[0060] In some embodiments, the semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion;

[0061] The source electrode is located outside the projection area of ​​the active column along the second direction;

[0062] The capacitor structure is located on the top surface of the active pillar, and the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer.

[0063] In some embodiments, a portion of the bitline structure is located within the projection region of the active post along a third direction, or the bitline structure is located outside the projection region of the active post along the third direction.

[0064] The third direction intersects with the plane containing the base.

[0065] The semiconductor structure and its formation method provided in this disclosure include a method where, during the formation of the embedded bit line structure, the active strip is not etched, thus preventing the active strip from collapsing and resulting in greater stability of the semiconductor structure during formation. Furthermore, in this disclosure, by forming the bit line structure in the gap between the active strip and the isolation structure, the fabrication process of the embedded bit line structure is simplified, reducing the process complexity of the semiconductor structure. Attached Figure Description

[0066] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0067] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0068] Figures 2a to 2o This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0069] Figures 3a to 3g This is a schematic diagram of another semiconductor structure formation process provided in an embodiment of the present disclosure;

[0070] Figure 4 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0071] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0072] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0073] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0074] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0075] The terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0076] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The substrate may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies), two intersecting (e.g., perpendicular) directions are defined. For example, the direction of the bitline structure extension can be defined as the first direction, and the direction of the bitline structure arrangement can be defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. In the embodiments of this disclosure, the first direction, the second direction, and the third direction may be mutually perpendicular; in other embodiments, the first direction, the second direction, and the third direction may not be perpendicular. In the embodiments of this disclosure, the first direction is defined as the X-axis, the second direction as the Y-axis, and the third direction as the Z-axis.

[0077] This disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0078] Step S101, providing a substrate, the substrate including active strips and a first trench extending along a first direction and alternately arranged along a second direction.

[0079] In this embodiment of the disclosure, the substrate includes at least a semiconductor substrate, which may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0080] In some embodiments, the substrate includes a substrate and a first isolation layer located on the surface of the substrate; the first isolation layer may include a semiconductor isolation layer and / or an insulating layer, the semiconductor isolation layer and / or the insulating layer being used to isolate the bit line structure from the substrate. For example, the first isolation layer may include a semiconductor isolation layer, or the first isolation layer may include an insulating layer, or the first isolation layer may include a semiconductor isolation layer and an insulating layer; wherein, when the first isolation layer includes a semiconductor isolation layer and an insulating layer, the insulating layer may be located on the surface of the semiconductor isolation layer, or the semiconductor isolation layer may be located on the surface of the insulating layer.

[0081] In some embodiments, the insulating layer may be made of silicon oxide or other suitable materials. The semiconductor isolation layer includes at least a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the active strip is located on the surface of the first N-type semiconductor layer.

[0082] In this embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction. The bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct. This can prevent leakage of the bit line structure.

[0083] In other embodiments, the substrate can be a P-type doped silicon substrate, and the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, with the first P-type semiconductor layer located on the surface of the second N-type semiconductor layer. In this case, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate can form another PN junction. Thus, when a high voltage is applied to the bit line structure, both PN junctions are reverse biased, which can more effectively prevent leakage current in the bit line structure.

[0084] In some embodiments, the active strip may include a third semiconductor layer located within the projection region of the first gap along the second direction, and the third semiconductor layer may be a silicon-germanium layer.

[0085] Step S102: An isolation structure extending in a first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area in the second direction.

[0086] In this embodiment of the disclosure, the isolation structure is convex in shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure; wherein, the first U-shaped isolation structure is used to isolate the subsequently formed bit line structure from the substrate to prevent leakage current; the second isolation structure is used to isolate two adjacent isolation structures subsequently formed.

[0087] Step S103: A bit line structure is formed in the first gap.

[0088] In this embodiment of the disclosure, a bit line structure can be formed by depositing a bit line conductive material in the first void; wherein, the bit line conductive material includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0089] The semiconductor structure formation method provided in this disclosure eliminates the need for etching the active strip during the formation of the embedded bit line structure. This reduces the risk of the active strip collapsing and enhances the stability of the semiconductor structure during formation. Furthermore, by forming the bit line structure within the gap between the active strip and the isolation structure, the fabrication process of the embedded bit line structure is simplified, reducing the complexity of the semiconductor structure fabrication.

[0090] Figures 2a to 2o This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 2a to 2o The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail. Figure 2h This is a sectional view along c-c'. Figure 2i for Figure 2h Cross-sectional views along a-a', b-b', and d-d'. Figure 2l This is a sectional view of a-a'. Figure 2m for Figure 2l Cross-sectional views along e-e' and c-c'. Figure 2n for Figure 2m Cross-sectional views along the middle b-b' and d-d'.

[0091] First, you can refer to Figures 2a to 2d Step S101 is performed, providing a substrate, the substrate including active strips and a first trench extending along a first direction and alternately arranged along a second direction.

[0092] like Figure 2a As shown, the substrate includes a substrate 10 and a first isolation layer located on the surface of the substrate 10. The first isolation layer includes a semiconductor isolation layer 11, which includes a first P-type semiconductor layer 11a located on the surface of the substrate 10 and a first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a. In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.

[0093] In some embodiments, the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b can be formed by the following steps: forming a first initial semiconductor layer (not shown) on the surface of the substrate 10; performing a first heavy doping on the first initial semiconductor layer to form the first P-type semiconductor layer 11a; forming a second initial semiconductor layer (not shown) on the surface of the first P-type semiconductor layer; and performing a second heavy doping on the second initial semiconductor layer to form the first N-type semiconductor layer 11b.

[0094] In this embodiment of the disclosure, the doping element of the first doping can be a group III element, such as a trivalent impurity element such as boron, gallium, or indium; the doping element of the second doping can be a group V element, such as a pentavalent impurity element such as phosphorus, antimony, or arsenic.

[0095] In this embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction. The bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct. Since the reverse resistance of the PN junction is very high, the bit line structure and the substrate can be isolated to prevent leakage of the bit line structure.

[0096] For ease of understanding, Figures 2b to 2o Only the semiconductor isolation layer 11 is shown; the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b in the semiconductor isolation layer 11 are not shown.

[0097] In some embodiments, the active strip and the first trench can be formed by the following steps: forming a semiconductor active layer on the surface of a first N-type semiconductor layer; forming a first mask layer having a first pattern on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along a first direction and arranged along a second direction, the first sub-patterns exposing a portion of the semiconductor active layer; removing the portion of the semiconductor active layer exposed by the first sub-patterns through the first mask layer to form an active strip and a first trench that extend along the first direction and are alternately arranged along the second direction.

[0098] like Figure 2b As shown, a semiconductor active layer 12a is formed on the surface of the first N-type semiconductor layer (i.e., semiconductor isolation layer 11).

[0099] In this embodiment of the disclosure, the semiconductor active layer 12a can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, or other suitable process.

[0100] like Figures 2b to 2d As shown, a first mask layer 25 with a first pattern is formed on the surface of the semiconductor active layer 12a; the first pattern includes a plurality of first sub-patterns E extending along the X-axis direction and arranged along the Y-axis direction, the first sub-patterns E exposing a portion of the semiconductor active layer 12a; through the first mask layer 25, the portion of the semiconductor active layer 12a exposed by the first sub-patterns E is removed, forming active strips 12 extending along the X-axis direction and alternatingly arranged with first trenches 13 along the Y-axis direction.

[0101] In this embodiment of the disclosure, the material of the first mask layer 25 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the first mask layer 25 may be formed by any suitable deposition process.

[0102] In this embodiment of the disclosure, after forming the active strip 12 and the first trench 13, the method for forming the semiconductor structure further includes: removing the first mask layer 25 to expose the upper surface of the active strip 12.

[0103] Next, you can refer to Figures 2e to 2g Step S102 is executed, in which an isolation structure extending in a first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area in the second direction.

[0104] In some embodiments, the isolation structure is convex in shape, and the isolation structure includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure; the isolation structure can be formed by the following steps: forming a first initial isolation structure on the surface of the active strip and the inner wall of the first trench; forming a second isolation structure at the bottom of the first trench having the first initial isolation structure; etching back the first initial isolation structure to form the first U-shaped isolation structure; the top surface of the second isolation structure extends beyond the top surface of the first U-shaped isolation structure.

[0105] like Figure 2e As shown, a first isolation material is deposited on the surface of the active strip 12 and the inner wall of the first trench 13 to form a first initial isolation structure 14a; the first isolation material may be silicon oxide or other suitable materials.

[0106] like Figure 2f As shown, a second isolation material is deposited in a first trench 13 having a first initial isolation structure 14a to form a second initial isolation structure (not shown); the second initial isolation structure is etched back to form a second isolation structure 15; the second isolation material may be silicon nitride or other suitable materials.

[0107] In this embodiment of the present disclosure, during the process of re-etching the second initial isolation structure, the etching selectivity between the second isolation material and the substrate is greater than that between the first isolation material and the substrate. For example, the etching selectivity between the second isolation material and the substrate is 3 to 10 times that between the first isolation material and the substrate. In this way, the first initial isolation structure 14a can be avoided when re-etching the second initial isolation structure.

[0108] In this embodiment of the disclosure, the first initial isolation structure 14a and the second initial isolation structure can be formed by any suitable deposition process.

[0109] like Figure 2g As shown, the first initial isolation structure 14a is etched back (reference). Figure 2f The first U-shaped isolation structure 14 is formed, and the first initial isolation structure can be etched back using a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling). In this embodiment, the top surface of the second isolation structure 15 extends beyond the top surface of the first U-shaped isolation structure 14.

[0110] In this embodiment of the disclosure, the isolation structure is convex in shape, and the isolation structure (i.e., the second isolation structure 15) and the active strip 12 have a first gap 16a in the projection area along the Y-axis direction.

[0111] In this embodiment of the present disclosure, during the process of re-etching the first initial isolation structure, the etching selectivity between the first isolation material and the substrate is greater than that between the second isolation material and the substrate. For example, the etching selectivity between the first isolation material and the substrate is 5 to 10 times that between the second isolation material and the substrate. In this way, the second isolation structure 15 can be avoided when re-etching the first initial isolation structure 14a.

[0112] In this embodiment of the disclosure, the first U-shaped isolation structure 14 located in the convex isolation structure is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 15 located in the convex isolation structure is used to isolate two adjacent bit line structures located in the same first trench 13 to prevent leakage of the bit line structure, thereby improving the electrical performance of the semiconductor structure.

[0113] In other embodiments, the first U-shaped isolation structure may also be a semiconductor isolation layer, or the first U-shaped isolation structure may also be a composite isolation structure composed of a semiconductor isolation layer and an insulating layer (e.g., an oxide layer).

[0114] Finally, you can refer to Figures 2h to 2o In step S103, a bit line structure is formed in the first gap.

[0115] like Figure 2h and Figure 2i As shown, bit line metal material is deposited in the first trench 13 with an isolation structure to form an initial bit line structure (not shown), and the initial bit line structure is etched back to form a bit line structure 16.

[0116] In this embodiment of the disclosure, the bit line metal material includes: tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0117] In this embodiment of the disclosure, the initial bit line structure can be etched back using a dry etching process to form the bit line structure 16.

[0118] It should be noted that, in this embodiment, the top surface of the bit line structure 16 does not extend beyond the top surface of the second isolation structure 15. In other embodiments, the top surface of the bit line structure 16 may be flush with the top surface of the second isolation structure 15.

[0119] In some embodiments, after forming the bit line structure, the method for forming the semiconductor structure further includes: removing residual metal located in the first trench 13 by a wet etching process.

[0120] In this embodiment of the present disclosure, after removing the residual metal located in the first trench 13, the method for forming the semiconductor structure further includes: thermally oxidizing and growing silicon oxide of a predetermined thickness on the surfaces of the second isolation structure 15 and the bit line structure 16. The silicon oxide is used to further remove residual metal from the sidewalls of the active strip 12 and prevent the formation of silicides on the surface of the channel structure during subsequent processes. In this embodiment of the present disclosure, the predetermined thickness can be 1 to 5 nanometers (nm).

[0121] In some embodiments, after removing residual metal, the method of forming a semiconductor structure further includes: covering the surface of the bit line structure and the surface of the isolation structure to form a third isolation structure; wherein the top surface of the third isolation structure does not extend beyond the top surface of the active strip.

[0122] like Figure 2j As shown, a third isolation material is deposited on the surface of the bit line structure 16 and the surface of the second isolation structure 15 to form a third isolation structure 17. The third isolation material can be silicon oxide, silicon oxynitride, or other suitable materials.

[0123] In this embodiment of the disclosure, a third isolation material can be deposited using an atomic deposition process to form a third isolation structure 17, thereby improving the quality of the film layer.

[0124] In some embodiments, such as Figure 2k As shown, after forming the third isolation structure 17, the method for forming the semiconductor structure further includes: performing heat treatment on the bit line structure 16 and the active strip 12 to form a metal silicide 19 located between the bit line structure 16 and the active strip 12.

[0125] In this embodiment, a rapid thermal processing (RTP) process can be used to react the bit line metal material with the active strip 12, thereby forming a metal silicide 19 on the surface of the active strip 12. Since the metal silicide has a low resistance, the contact resistance between the bit line structure 16 and the active strip 12 can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0126] Please continue to refer to this. Figure 2k After forming the metal silicide, the method for forming the semiconductor structure further includes: doping the active strip 12 in the projection region of the bit line structure along the Y-axis to form a drain portion 26, which can serve as the drain D of a transistor structure.

[0127] In this embodiment, ion implantation is performed on the active strip 12 within the Y-axis projection region of the bit line structure to form the drain D. Ion implantation can be achieved through processes such as thermal diffusion and plasma doping. The energy and dosage used in the ion implantation process, as well as the type of implanted ions, can be determined according to the type of transistor to be formed. For example, P-type metal-oxide-semiconductor (PMOS) can be shallowly and heavily doped with BF2. + Ion implantation; N-type metal-oxide-semiconductor (NMOS) can undergo shallow, heavily doped arsenic ion implantation. Following ion implantation, a high-temperature annealing process can be performed to repair lattice damage caused by ion implantation and reactivate the implanted impurities.

[0128] It should be noted that the order of forming the drain D, the metal silicide 19, and the third isolation structure 17 is not limited in the embodiments disclosed herein. For example, the drain D can be formed first, then the third isolation structure 17 can be formed, and finally the metal silicide 19 can be formed; the metal silicide 19 can be formed first, then the third isolation structure 17 can be formed, and finally the drain D can be formed; or the drain D can be formed first, then the metal silicide 19 can be formed, and finally the third isolation structure 17 can be formed.

[0129] In some embodiments, the method of forming a semiconductor structure further includes: forming a fourth isolation structure on the surface of a third isolation structure; wherein the top surface of the fourth isolation structure is flush with the top surface of the active strip.

[0130] Please continue to refer to this. Figure 2k A fourth isolation material is deposited on the surface of the third isolation structure 17 to form a fourth isolation structure 18. The fourth isolation material can be silicon oxide, silicon oxynitride, or other suitable materials. The third isolation material and the fourth isolation material can be the same or different.

[0131] It should be noted that during the process of depositing the fourth isolation material on the surface of the third isolation structure 17 to form the fourth isolation structure 18, some of the fourth isolation material is often also deposited on the surface of the active strip 12. Then, it will undergo chemical mechanical polishing (CMP) treatment to make the top surface of the fourth isolation structure 18 flush with the top surface of the active strip 12.

[0132] In some embodiments, after forming the fourth isolation structure 18, the method for forming the semiconductor structure further includes forming a word line structure, a source portion, and a capacitor structure.

[0133] In some embodiments, the word line structure can be formed by the following steps: forming a second mask layer having a second pattern on the surfaces of the active strip and the fourth isolation structure; the second pattern includes a plurality of second sub-patterns extending along a second direction and arranged along a first direction, the second sub-patterns exposing a portion of the active strip and a portion of the fourth isolation structure; etching the active strip and a portion of the fourth isolation structure exposed by the second sub-patterns through the second mask layer, or etching the active strip and all of the fourth isolation structure exposed by the second sub-patterns to form a second trench and an active isolation layer alternately arranged along the first direction; wherein the size of the second trench along a third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched fourth isolation structures alternately arranged along the second direction; the active pillars are insulated from each other; a word line structure is formed on the sidewall of the second trench, the top surface of the word line structure not extending beyond the top surface of the active pillars.

[0134] like Figures 2l to 2n As shown, a second mask layer 27 with a second pattern is formed on the surface of the active strip 12 and the fourth isolation structure 18; the second pattern includes a plurality of second sub-patterns F extending along the Y-axis direction and arranged along the X-axis direction, the second sub-patterns F exposing a portion of the active strip 12 and a portion of the fourth isolation structure 18; through the second mask layer 27, the portion of the active strip 12 and the portion of the fourth isolation structure 18 exposed by the second sub-patterns F is etched until the third isolation structure 17 is exposed, forming a second trench 22a and an active isolation layer 20 alternately arranged along the X-axis direction; wherein, the second trench 22a extends along the Y-axis direction, and the active isolation layer 20 includes active pillars 21 alternately arranged along the Y-axis direction and the etched fourth isolation structure 18, the active pillars 21 being insulated from each other by the fourth isolation structure 18. In this embodiment of the present disclosure, the dimension d1 of the second trench 22a in the Z-axis direction (e.g., Figure 2l As shown) is equal to the initial dimension d2 of the fourth isolation structure 18 in the Z-axis direction (as shown). Figure 2m (As shown).

[0135] In other embodiments, a portion of the active strip 12 and a portion of the fourth isolation structure 18 exposed by the second sub-pattern F are etched through the second mask layer 27 to form a second trench 22a and an active isolation layer 20 that are alternately arranged along the X-axis direction; wherein, the second trench 22a extends along the Y-axis direction, the active isolation layer 20 includes active pillars 21 and a fourth isolation structure 18 located between two adjacent active pillars 21 along the Y-axis direction, the active pillars 21 are insulated from each other by the fourth isolation structure 18, and the size of the second trench 22a in the Z-axis direction is smaller than the initial size d2 of the fourth isolation structure 18 in the Z-axis direction.

[0136] In this embodiment of the disclosure, the material of the second mask layer 27 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the second mask layer 27 may be formed by any suitable deposition process.

[0137] In some embodiments, after forming the active isolation layer 20, the method for forming the semiconductor structure further includes removing the second mask layer 27 having the second pattern.

[0138] like Figure 2n and Figure 2o As shown, a gate dielectric layer 221 and a gate conductive layer located on the surface of the gate dielectric layer 221 are sequentially deposited on the sidewall of the second trench 22a. The gate conductive layer can serve as a word line structure 22, and the top surface of the word line structure 22 does not extend beyond the top surface of the active pillar. In this embodiment, the active pillar 21 located within the projection area of ​​the word line structure 22 along the X-axis direction constitutes a channel structure.

[0139] In some embodiments, the gate dielectric layer 221 may be made of silicon oxide or other suitable materials; the gate conductive layer may be made of any material with good conductivity, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu). The gate dielectric layer and the gate conductive layer may be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0140] It should be noted that the gate structure in this embodiment is a dual-gate structure. In other embodiments, the etched fourth isolation structure 18 located between the active pillars 21 can be removed to form a full-ring gate structure on the surface of the active pillars 21.

[0141] In some embodiments, after forming the word line structure 22, the method of forming the semiconductor structure further includes: depositing a fifth isolation material in a second trench 22a having the word line structure 22 to form a fifth isolation structure 23. The fifth isolation material may be silicon oxide or other suitable materials, and the fifth isolation structure 23 is used to isolate two adjacent word line structures 22.

[0142] In some embodiments, reference Figure 2o After forming the word line structure 22, the method for forming the semiconductor structure further includes: performing ion implantation on the active pillar 21 outside the projection area of ​​the word line structure 22 along the X-axis direction to form a source portion, wherein the source portion can serve as the source S of a transistor structure.

[0143] In this embodiment, the source and drain are located on both sides of the channel structure along a third direction. That is, the transistor structure in this embodiment is vertical. A vertical transistor structure (or channel structure) can give the semiconductor structure a higher density of arrangement, thereby improving the integration of the semiconductor structure and achieving miniaturization.

[0144] In some embodiments, after the source portion is formed, a capacitor structure connected to the source portion is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked sequentially.

[0145] Please continue to refer to this. Figure 2o A capacitor structure 24 connected to the source electrode is formed on the top surface of the active pillar. The capacitor structure includes a first electrode layer 241, a dielectric layer 242, and a second electrode layer 243 stacked sequentially.

[0146] In this embodiment, the materials of the first electrode layer 241 and the second electrode layer 243 may include metal nitrides or metal silicides, such as titanium nitride. The material of the dielectric layer 242 may include a high-k dielectric material, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or hafnium silicate (HfSiO₂). x One or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2).

[0147] In this embodiment of the disclosure, the first electrode layer 241, the dielectric layer 242, and the second electrode layer 243 can be formed by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0148] The semiconductor structure formation method provided in this disclosure eliminates the need for etching the active strip during the formation of the embedded bit line structure. This reduces the risk of the active strip collapsing and enhances the stability of the semiconductor structure during formation. Furthermore, by forming the bit line structure within the gap between the active strip and the isolation structure, the fabrication process of the embedded bit line structure is simplified, reducing the complexity of the semiconductor structure fabrication.

[0149] Figures 3a to 3g This is a schematic diagram of another semiconductor structure formation process provided in this disclosure embodiment, which is described below in conjunction with... Figures 3a to 3g The formation process of another semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0150] First, refer to Figure 3a and 3b This forms active strips 12 and first grooves 13 that extend along the X-axis and are alternately arranged along the Y-axis.

[0151] like Figure 3a As shown, the substrate includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 includes a first P-type semiconductor layer 11a located on the surface of the substrate 10 and a first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a.

[0152] For ease of understanding, Figures 3b to 3g Only the semiconductor isolation layer 11 is shown; the first P-type semiconductor layer 11a and the first N-type semiconductor layer 11b in the semiconductor isolation layer 11 are not shown.

[0153] In this embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction. The bit line structure formed subsequently is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct. This can prevent leakage of the bit line structure.

[0154] Please continue to refer to this. Figure 3a A first active semiconductor layer 121a, a third initial semiconductor layer 122a, and a second active semiconductor layer 123a are sequentially formed on the surface of the first N-type semiconductor layer 11b (i.e., semiconductor isolation layer 11). The first active semiconductor layer 121a, the third initial semiconductor layer 122a, and the second active semiconductor layer 123a constitute the active semiconductor layer 12a. In this embodiment, the first active semiconductor layer 121a and the second active semiconductor layer 123a may be silicon layers, and the third initial semiconductor layer 122a may be a silicon-germanium layer.

[0155] like Figure 3bAs shown, the active semiconductor layer 12a is etched to form active strips 12 extending along the X-axis and alternating with first trenches 13 along the Y-axis. The active strips 12 include a first active strip 121, a third semiconductor layer 122, and a second active strip 123 arranged sequentially from bottom to top along the Z-axis.

[0156] Next, please refer to Figures 3b-3d This forms an isolation structure.

[0157] Please continue to refer to this. Figure 3b and Figure 3c A first initial isolation structure 14a is formed on the surface of the active strip 12 and the inner wall of the first trench 13; a second initial isolation structure (not shown) is formed in the first trench 13 having the first initial isolation structure 14a; the second initial isolation structure is etched back to form a second isolation structure 15.

[0158] like Figure 3d As shown, the first initial isolation structure 14a is etched back to form a first U-shaped isolation structure 14. The second isolation structure 15 and the first U-shaped isolation structure 14 together constitute an isolation structure. The isolation structure and the third semiconductor layer 122 have a first gap 16a in the projection region along the second direction.

[0159] In this embodiment of the disclosure, the first U-shaped isolation structure 14 is used to isolate the subsequently formed bit line structure and the substrate to prevent leakage of the bit line structure; the second isolation structure 15 is used to isolate two adjacent bit line structures located in the same first trench 13 to prevent leakage of the bit line structure.

[0160] Next, refer to Figures 3e to 3g After forming the isolation structure, the method for forming the semiconductor structure further includes: laterally etching the third semiconductor layer along the second direction to form the third sub-semiconductor layer; wherein the isolation structure and the third sub-semiconductor layer have a second gap in the projection region along the second direction, the second gap including the first gap; and forming a bit line structure in the second gap.

[0161] like Figure 3e and 3f As shown, the third semiconductor layer 122 is etched laterally along the Y-axis to form the third sub-semiconductor layer 28; wherein, the isolation structure is convex in shape, and the isolation structure (or the second isolation structure 15) and the third sub-semiconductor layer 28 have a second gap 16b in the projection area along the Y-axis, the second gap 16b including the first gap 16a; a bit line structure 16 is formed in the second gap 16b.

[0162] In this embodiment of the disclosure, the isolation structure is convex in shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structures from the substrate, prevent leakage current, and improve the electrical performance of the semiconductor structure.

[0163] In this embodiment of the present disclosure, the third semiconductor layer 122 can be etched laterally using a wet etching process to form the third sub-semiconductor layer 28; the wet etching solution can be hydrofluoric acid (DHF), or a mixed solution of diluted hydrofluoric acid and ammonia (NH4OH), or a mixed solution including diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH).

[0164] like Figure 3g As shown, after forming the bit line structure 16, the method for forming the semiconductor structure further includes: performing rapid thermal processing on the bit line structure 16, the first active strip 121, the second active strip 123, and the third sub-semiconductor layer 28 to form a first metal silicide 191 located between the bit line structure 16 and the first active strip 121, a third metal silicide 193 located between the bit line structure 16 and the second active strip 123, and a third metal silicide 193 located between the bit line structure 16 and the third sub-semiconductor layer 28. Figure 3g The second metal silicide 192 is located between (not shown in the diagram). The first metal silicide 191, the second metal silicide 192, and the third metal silicide 193 constitute metal silicide 19. In this embodiment, since metal silicide 19 has a low resistance, the contact resistance between bit line structure 16 and the second active strip 123, and between bit line structure 16 and the third sub-semiconductor layer, can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0165] In this embodiment of the disclosure, a third isolation structure is formed by covering the surface of the bit line structure 16 and the surface of the second isolation structure 15.

[0166] In some embodiments, the method for forming a semiconductor structure further includes forming a drain, a word line structure, a source, and a capacitor structure.

[0167] The methods for forming the drain, word line structure, source, and capacitor structure in this embodiment are similar to those for forming the drain, word line structure, source, and capacitor structure in the above embodiments. Please refer to the above embodiments for a detailed understanding.

[0168] The semiconductor structure formation method provided in this disclosure does not require complete etching of the active strip during the formation of the embedded bit line structure. This makes the active strip less prone to collapse and allows the bit line structure to be formed between the third sub-semiconductor layer and the isolation structure in the active strip. Part of the bit line structure is located in the projection area of ​​the first active strip along the third direction, thereby improving the fabrication yield of the semiconductor structure.

[0169] The method for forming a semiconductor structure provided in this disclosure is similar to the method for forming a semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0170] In addition, this disclosure also provides a semiconductor structure, which is formed by the semiconductor structure formation method described in the above embodiments. Figure 4 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure 100 includes: a substrate, the substrate including a drain portion 26 extending along the X-axis and alternately arranged along the Y-axis and an isolation structure; and a bit line structure 16 located between the isolation structure and the drain portion 26. The drain portion 26 can serve as the drain D of a transistor structure.

[0171] In some embodiments, the substrate includes a substrate and a first isolation layer located on the surface of the substrate; the first isolation layer includes a semiconductor isolation layer and / or an insulating layer, the semiconductor isolation layer and / or the insulating layer being used to isolate the bit line structure from the substrate.

[0172] In this embodiment of the disclosure, please continue to refer to Figure 4 The substrate includes a substrate 10 and a first isolation layer located on the surface of the substrate 10, wherein the first isolation layer includes a semiconductor isolation layer 11.

[0173] In other embodiments, the first isolation layer may include an insulating layer, or the first isolation layer may include an insulating layer and a semiconductor isolation layer.

[0174] In this embodiment of the disclosure, please continue to refer to Figure 4 The semiconductor isolation layer 11 is used to isolate the bit line structure 16 from the substrate 10; the semiconductor isolation layer includes at least a first P-type semiconductor layer 11a located on the surface of the substrate and a first N-type semiconductor layer 11b located on the surface of the first P-type semiconductor layer 11a; the drain portion 26 is located on the surface of the first N-type semiconductor layer 11b.

[0175] In this embodiment of the present disclosure, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction. The bit line structure is close to the first N-type semiconductor layer, that is, the bit line structure is close to the N end of the PN junction. In this way, when a high voltage is applied to the bit line structure, the PN junction is reverse biased and will not conduct. This can prevent leakage of the bit line structure.

[0176] In other embodiments, the substrate 10 is a P-type doped substrate, and the semiconductor isolation layer 11 may further include a second N-type semiconductor layer located on the surface of the substrate 10, with the first P-type semiconductor layer located on the surface of the second N-type semiconductor layer. In this case, the first P-type semiconductor layer and the first N-type semiconductor layer can form a PN junction, and the second N-type semiconductor layer and the P-type doped silicon substrate can form another PN junction. Thus, when a high voltage is applied to the bit line structure, both PN junctions are reverse biased, which can more effectively prevent leakage current in the bit line structure.

[0177] In some embodiments, please refer to Figure 4 The isolation structure is convex in shape and includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the bottom surface of the U-shape of the first U-shaped isolation structure 14, and the top surface of the second isolation structure 15 extends beyond the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.

[0178] In this embodiment of the disclosure, the isolation structure is convex in shape. Therefore, the isolation structure can not only isolate adjacent bit line structures, but also isolate the bit line structures from the substrate, prevent leakage current, and improve the electrical performance of the semiconductor structure.

[0179] In some embodiments, please refer to Figure 4 The semiconductor structure 100 further includes a third isolation structure 17, which is located on the surface of the bit line structure 16 and the surface of the second isolation structure 15.

[0180] In some embodiments, please refer to Figure 4 The semiconductor structure 100 also includes a metal silicide 19 located between the bit line structure 16 and the drain portion 26. Since the metal silicide 19 has a low resistance, the contact resistance between the bit line structure 16 and the drain portion 26 can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0181] In some embodiments, please refer to Figure 4 The semiconductor structure 100 further includes: an active pillar 21 located on the surface of the drain portion 26 and arranged in an array along the X-axis and Y-axis directions, and a word line structure 22 located on the sidewall of the active pillar 21, arranged along the X-axis and extending along the Y-axis; wherein the top surface of the word line structure 22 does not extend beyond the top surface of the active pillar 21.

[0182] In this embodiment, the semiconductor structure 100 further includes a fourth isolation structure 18, wherein the active pillars 21 arranged alternately in the Y-axis direction and the fourth isolation structure 18 constitute an active isolation layer 20. In other embodiments, the fourth isolation structure 18 may not be included.

[0183] In this embodiment of the disclosure, the bit line structure 16 is located outside the projection area of ​​the active pillar 21 along the Z-axis direction.

[0184] In some embodiments, please refer to Figure 4 The semiconductor structure 100 further includes a gate structure, which includes a gate conductive layer on the surface of the gate dielectric layer 221, wherein the gate conductive layer can serve as a word line structure 22.

[0185] In some embodiments, please refer to Figure 4The semiconductor structure 100 further includes a source portion and a capacitor structure 24 connected to the source portion. The source portion is located outside the projection area of ​​the active pillar 21 along the Y-axis direction; wherein, the source portion can serve as the source S of a transistor structure. The capacitor structure 24 is located on the top surface of the active pillar 21, and the capacitor structure 24 includes a first electrode layer 241, a dielectric layer 242, and a second electrode layer 243.

[0186] In some embodiments, please refer to Figure 4 The semiconductor structure 100 further includes a fifth isolation structure 23, which is located between adjacent word line structures 22 along the X-axis direction and between adjacent source portions along the X-axis direction.

[0187] The semiconductor structure provided in this embodiment is similar to the semiconductor structure formed by the method described in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0188] The semiconductor structure in this embodiment includes an embedded bit line structure, which is located between the active strip and the isolation structure. Compared with related technologies, the bottom of the active strip in the semiconductor structure provided by this embodiment is not etched or is not completely etched off during the formation of the bit line structure. Thus, this embodiment can provide a semiconductor structure with higher stability.

[0189] This disclosure also provides a semiconductor structure formed by the semiconductor structure formation method described in the above embodiments. Please continue to refer to... Figure 3g The semiconductor structure includes: a substrate, the substrate including a drain portion 26 extending along the X-axis and alternately arranged along the Y-axis and an isolation structure; and a bit line structure 16 located between the isolation structure and the drain portion 26, the drain portion 26 being a drain of a transistor structure.

[0190] In this embodiment of the disclosure, please continue to refer to Figure 3g The semiconductor structure also includes active pillars located on the surface of the drain portion 26 and arranged in an array along the X-axis and Y-axis directions.

[0191] In this embodiment of the disclosure, please continue to refer to Figure 3g The drain portion 26 includes a first active strip 121 and a third sub-semiconductor layer ( Figure 3g (not shown in the text) and part of the second active clause 123.

[0192] In this embodiment of the disclosure, please continue to refer to Figure 3gThe semiconductor structure also includes metal silicide 19, which includes a first metal silicide 191 between the bit line structure 16 and the first active strip 121, a second metal silicide 192 between the bit line structure 16 and the third sub-semiconductor layer, and a third metal silicide 193 between the bit line structure 16 and the second active strip 123.

[0193] In this embodiment of the disclosure, please continue to refer to Figure 3g Part of the bitline structure 16 is located within the projection area of ​​the active column along the Z-axis.

[0194] In this embodiment of the disclosure, please continue to refer to Figure 3g The isolation structure is convex in shape and includes a first U-shaped isolation structure 14 and a second isolation structure 15 located on the bottom surface of the U-shape of the first U-shaped isolation structure 14, and the top surface of the second isolation structure 15 extends beyond the top surface of the first U-shaped isolation structure 14; both the first U-shaped isolation structure 14 and the second isolation structure 15 are in contact with the bit line structure 16.

[0195] In some embodiments, please refer to Figure 3g The substrate includes a substrate 10 and a semiconductor isolation layer 11 located on the surface of the substrate 10. The semiconductor isolation layer 11 is used to isolate the bit line structure 16 from the substrate 10. The semiconductor isolation layer 11 includes a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer.

[0196] The semiconductor structure provided in this disclosure is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0197] The semiconductor structure in this embodiment includes an embedded bit line structure. The bit line structure is located between the third sub-semiconductor layer and the isolation structure in the active strip, and part of the bit line structure is located in the projection area of ​​the first active strip along the third direction. Compared with related technologies, the bottom of the active strip in the semiconductor structure provided by this embodiment is not completely etched off during the formation of the bit line structure. Thus, this embodiment can provide a semiconductor structure with higher stability.

[0198] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0199] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0200] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate comprising active strips and a first trench extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within the plane of the substrate; An isolation structure extending along the first direction is formed at the bottom of the first trench; wherein the isolation structure and the active strip have a first gap in the projection area along the second direction; A bitline structure is formed in the first gap; The substrate includes a substrate and a first isolation layer located on the surface of the substrate; The first isolation layer includes a semiconductor isolation layer and / or an insulating layer, wherein the semiconductor isolation layer and / or the insulating layer are used to isolate the bit line structure from the substrate; The semiconductor isolation layer includes at least a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; The active strip is located on the surface of the first N-type semiconductor layer; The active strip includes a third semiconductor layer located within the projection region of the first gap along the second direction. After forming the isolation structure, the method further includes: The third semiconductor layer is etched along the second direction to form a third sub-semiconductor layer; wherein, the isolation structure and the third sub-semiconductor layer have a second gap in the projection region along the second direction, and the second gap includes the first gap; The bit line structure is formed in the second gap.

2. The method according to claim 1, characterized in that, The first P-type semiconductor layer and the first N-type semiconductor layer are formed by the following steps: A first initial semiconductor layer is formed on the surface of the substrate; The first initial semiconductor layer is subjected to a first heavy doping to form the first P-type semiconductor layer; A second initial semiconductor layer is formed on the surface of the first P-type semiconductor layer; The second initial semiconductor layer is subjected to a second doping to form the first N-type semiconductor layer.

3. The method according to claim 1, characterized in that, The substrate is a P-type doped substrate, and the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, wherein the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.

4. The method according to any one of claims 1 to 3, characterized in that, The isolation structure is convex in shape, and includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure; the isolation structure is formed by the following steps: A first initial isolation structure is formed on the surface of the active strip and the inner wall of the first trench; The second isolation structure is formed at the bottom of the first trench having the first initial isolation structure; The first initial isolation structure is etched back to form the first U-shaped isolation structure; The top surface of the second isolation structure extends beyond the top surface of the first U-shaped isolation structure.

5. The method according to claim 4, characterized in that, After forming the bit line structure, the method further includes: The active strip in the projection region of the bit line structure along the second direction is doped to form a drain portion.

6. The method according to claim 5, characterized in that, After forming the bit line structure, the method further includes: The bit line structure and the active strip are heat-treated to form a metal silicide located between the bit line structure and the active strip.

7. The method according to claim 6, characterized in that, The method further includes: A third isolation structure is formed by covering the surface of the bit line structure and the surface of the second isolation structure. The top surface of the third isolation structure does not extend beyond the top surface of the active strip.

8. The method according to claim 7, characterized in that, A fourth isolation structure is formed on the surface of the third isolation structure; The top surface of the fourth isolation structure is flush with the top surface of the active strip.

9. The method according to claim 8, characterized in that, The active strip and the first trench are formed through the following steps: A semiconductor active layer is formed on the surface of the first N-type semiconductor layer; A first mask layer having a first pattern is formed on the surface of the semiconductor active layer; the first pattern includes a plurality of first sub-patterns extending along the first direction and arranged along the second direction, the first sub-patterns exposing a portion of the semiconductor active layer; By passing through the first mask layer, a portion of the semiconductor active layer exposed by the first sub-pattern is removed, forming the active strips and the first trench that extend along the first direction and are alternately arranged along the second direction.

10. The method according to claim 9, characterized in that, The method further includes: A second mask layer with a second pattern is formed on the surfaces of the active strip and the fourth isolation structure; the second pattern includes a plurality of second sub-patterns extending along the second direction and arranged along the first direction, the second sub-patterns exposing a portion of the active strip and a portion of the fourth isolation structure; The active strips and part of the fourth isolation structure exposed by the second sub-pattern are etched through the second mask layer, or the active strips and all of the fourth isolation structure exposed by the second sub-pattern are etched to form a second trench and an active isolation layer alternately arranged along the first direction; wherein the size of the second trench along a third direction is less than or equal to the initial size of the fourth isolation structure in the third direction; the second trench extends along the second direction, and the active isolation layer includes active pillars and etched fourth isolation structures alternately arranged along the second direction; The active columns are insulated from each other; A word line structure is formed on the sidewall of the second trench, and the top surface of the word line structure does not extend beyond the top surface of the active post.

11. The method according to claim 10, characterized in that, The method further includes: The portion of the active pillar located outside the projection area of ​​the word line structure along the first direction is doped to form the source portion; A capacitor structure connected to the source electrode is formed on the top surface of the active pillar, wherein the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer stacked sequentially.

12. A semiconductor structure, characterized in that, Obtained by the method according to any one of claims 1 to 11, comprising: The substrate includes drain portions and isolation structures extending along a first direction and alternately arranged along a second direction; the first direction and the second direction are any two directions within the plane of the substrate. The bit line structure is located between the isolation structure and the drain portion.

13. The semiconductor structure according to claim 12, characterized in that, The substrate includes a substrate and a first isolation layer located on the surface of the substrate; The first isolation layer includes a semiconductor isolation layer and / or an insulating layer, the semiconductor isolation layer and / or the insulating layer being used to isolate the bit line structure from the substrate.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor isolation layer includes at least a first P-type semiconductor layer located on the surface of the substrate and a first N-type semiconductor layer located on the surface of the first P-type semiconductor layer; the drain portion is located on the surface of the first N-type semiconductor layer.

15. The semiconductor structure according to claim 14, characterized in that, The substrate is a P-type doped substrate, and the semiconductor isolation layer further includes a second N-type semiconductor layer located on the surface of the substrate, wherein the first P-type semiconductor layer is located on the surface of the second N-type semiconductor layer.

16. The semiconductor structure according to claim 15, characterized in that, The isolation structure is convex in shape, and includes a first U-shaped isolation structure and a second isolation structure located on the bottom surface of the U-shape of the first U-shaped isolation structure; the top surface of the second isolation structure extends beyond the top surface of the first U-shaped isolation structure. Both the first U-shaped isolation structure and the second isolation structure are in contact with the bit line structure.

17. The semiconductor structure according to claim 16, characterized in that, The semiconductor structure also includes: A third isolation structure is located on the surfaces of the bit line structure and the second isolation structure.

18. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure also includes: The metal silicide located between the bit line structure and the drain portion.

19. The semiconductor structure according to claim 18, characterized in that, The semiconductor structure further includes: an active pillar located on the surface of the drain portion and arranged in an array along the first direction and the second direction, and a word line structure located on the sidewall of the active pillar, arranged along the first direction and extending along the second direction. The top surface of the word line structure does not extend beyond the top surface of the active column.

20. The semiconductor structure according to claim 19, characterized in that, The semiconductor structure further includes: a source portion and a capacitor structure connected to the source portion; The source electrode is located outside the projection area of ​​the active column along the second direction; The capacitor structure is located on the top surface of the active pillar, and the capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer.

21. The semiconductor structure according to claim 20, characterized in that, Some of the bitline structures are located within the projection area of ​​the active column along the third direction, or the bitline structures are located outside the projection area of ​​the active column along the third direction. The third direction intersects with the plane containing the base.

Images