Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure, which comprises: a substrate, the substrate has a transistor group in the array area, the transistor group comprises a plurality of layers of transistors arranged in a first direction; the transistor comprises a word line, a second source-drain electrode and two first source-drain electrodes, the word line and the second source-drain electrode are arranged in a second direction, and the two first source-drain electrodes are arranged in the first direction and located on opposite sides of the word line; in the first direction, two adjacent transistors share one first source-drain electrode; the peripheral area has a sub-word line driver, the word line is electrically connected with the sub-word line driver, and the sub-word line driver does not simultaneously provide an opening signal for two adjacent word lines in the first direction. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, specifically relating to a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a stored binary bit is 1 or 0.

[0003] 3D DRAM is a structure that stacks multiple layers of memory cells. It has a high degree of integration and a larger capacity per unit area, which helps to reduce the cost per unit area. However, the performance of 3D DRAM still needs to be improved. Summary of the Invention

[0004] This disclosure provides a semiconductor structure that at least improves the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate, wherein the substrate of the array region has a transistor group, the transistor group including multilayer transistors arranged in a first direction; the transistors include word lines, second source-drains and two first source-drains, the word lines and the second source-drains are arranged in a second direction, the two first source-drains are arranged in the first direction and located on opposite sides of the word lines; in the first direction, two adjacent transistors share one first source-drain; a sub-word line driver is provided in the peripheral region, the word lines are electrically connected to the sub-word line driver, and the sub-word line driver does not simultaneously provide an enable signal for two adjacent word lines in the first direction.

[0006] The technical solution provided in this disclosure has at least the following advantages: the two first source and drain electrodes of the transistor are arranged in a first direction and located on opposite sides of a word line. In the first direction, two adjacent transistors share a single first source and drain electrode. That is, when the transistor is turned on, two channels, upper and lower, can be formed, which is beneficial to improving the electrical performance of the transistor. In addition, since two adjacent word lines are not turned on simultaneously, signal interference between adjacent transistors can be avoided. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0008] Figure 1(d) shows a top view of a semiconductor structure provided in an embodiment of the present disclosure in a front-end process;

[0009] Figures 1(a) to 1(c) Different cross-sectional views of the semiconductor structure shown in Figure 1(d) are shown respectively;

[0010] Figures 2(a) to 2(c) Enlarged views of different cross-sections of a semiconductor structure provided in an embodiment of the present disclosure are shown;

[0011] Figures 3-4 , Figures 6-7 as well as Figures 9-10 Different top views of a semiconductor structure provided in an embodiment of this disclosure during a back-end process are shown;

[0012] Figure 5 A schematic diagram of a step region in a semiconductor structure provided in an embodiment of the present disclosure is shown;

[0013] Figure 8 A partial cross-sectional view of a bit line interconnect in a semiconductor structure provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0014] As the background technology shows, the performance of 3D DRAM needs improvement. There are two main types of 3D DRAM. The first type is based on indium gallium zinc oxide (IGZO) material, forming a 3D DRAM with a vertical annular channel (CAA) device structure. However, the uniformity of IGZO material is difficult to control, resulting in numerous defects. The second type is based on superlattice technology, forming a structure composed of alternating layers of different materials, namely, alternating layers of silicon and germanium silicon. However, depositing multiple layers of silicon and germanium silicon can cause numerous interface defects.

[0015] This disclosure provides a semiconductor structure in which a substrate has multiple layers of transistors arranged in a first direction. Each transistor includes a word line, a second source / drain, and two first source / drains. The word line and the second source / drain are arranged in a second direction, and the two first source / drains are arranged in the first direction and located on opposite sides of the word line. In the first direction, two adjacent transistors share a single first source / drain. This 3D stacking method of the transistors differs from the two aforementioned technologies, thus avoiding many of the defects caused by the former two technologies. Furthermore, by preventing adjacent word lines from being turned on simultaneously, signal interference between adjacent transistors can be avoided.

[0016] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0017] like Figures 1(a) to 10 As shown, one embodiment of this disclosure provides a semiconductor structure, which includes: a substrate 1, an array region AR, and a transistor group T0 within the substrate 1. The transistor group T0 includes multilayer transistors T arranged in a first direction X. Each transistor T includes a word line WL, a second source / drain 62, and two first source / drains 61. The word line WL and the second source / drain 62 are arranged in a second direction Y, and the two first source / drains 61 are arranged in the first direction X and located on opposite sides of the word line WL. In the first direction X, two adjacent transistors T share a first source / drain 61. A sub-word line driver SWD is provided in the peripheral region P. The word line WL is electrically connected to the sub-word line driver SWD, and the sub-word line driver SWD does not simultaneously provide an enable signal for two adjacent word lines WL in the first direction X.

[0018] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0019] The semiconductor structure has a first direction X, a second direction Y, and a third direction Z, which are not identical. For example, the first direction X is perpendicular to the second direction Y and the third direction Z, and the second direction Y is perpendicular to the third direction Z. In some embodiments, the semiconductor structure can be a Dynamic Random Access Memory (DRAM).

[0020] The structure of the array region (AR) will be described in detail below.

[0021] Referring to Figures 1(a) and 1(d), Figure 1(d) is a top view of the semiconductor structure in the front-end fabrication process, and Figure 1(a) shows a cross-sectional view of the semiconductor structure shown in Figure 1(d) along the A-A1 direction. The substrate 1 has first trenches 2 and second trenches 5 arranged alternately in the second direction Y, and the depth direction of both is the first direction X. The first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction X; the second trench 5 includes a plurality of second sub-trenches 50 arranged in the first direction X. The sidewalls of both the first sub-trenches 20 and the second sub-trenches 50 are convex, i.e., the sidewalls of the first trench 2 are wavy, and the sidewalls of the second trench 5 are wavy. For example, the first trenches 2 and the second trenches 5 can be formed using a Bosch process.

[0022] In some embodiments, referring to FIG1(d), a plurality of first trenches 2 are arranged in a third direction Z, and a plurality of second trenches 5 are arranged in a third direction Z. To illustrate the first trenches 2 and the second trenches 5 more clearly, only one row of first trenches 2 and one row of second trenches 5 are shown in FIGS1(a) and 1(d). In other embodiments, referring to... Figure 3 The first trenches 2 are arranged in an array within the substrate 1, and the second trenches 5 are also arranged in an array within the substrate 1. That is, multiple rows of the first trenches 2 are arranged in the second direction Y, and multiple rows of the second trenches 5 are arranged in the second direction Y. For example, the multiple rows of the first trenches 2 and the multiple rows of the second trenches 5 are also arranged alternately in the second direction Y.

[0023] Referring to Figures 1(a), 1(b), 2(a), and 2(b), where Figure 2(a) is a partially enlarged view of Figure 1(a) and Figure 2(b) is a partially enlarged view of Figure 1(b), the character line WL is located at the boundary of adjacent first sub-grooves 20 and protrudes outward from the interior of the first groove 2. Specifically, the boundary of adjacent first sub-grooves 20 has a hole 21 protruding outward from the first groove 2, and the character line WL is located within the hole 21. The character line WL is also located between the first groove 2 and the second groove 5.

[0024] The inner wall of the hole 21 also has a gate dielectric layer 31, which covers the surface of the word line WL. Specifically, the gate dielectric layer 31 covers the side of the word line WL away from the interior of the first trench 2. The gate dielectric layer 31 is in contact with the first source / drain 61 and the second source / drain 62.

[0025] Referring again to Figures 1(a), 1(b), 2(a), and 2(b), the first source / drain electrode 61 is located on two opposite sidewalls of the first sub-trench 20, and these two sidewalls are arranged in the second direction Y. The second source / drain electrode 62 is located at the boundary of adjacent second sub-trench 50 and protrudes outward from the interior of the second trench 5. The second source / drain electrode 62 is also located between the first trench 2 and the second trench 5. Furthermore, both the first source / drain electrode 61 and the second source / drain electrode 62 can extend in the third direction Z, that is, both can be columnar structures in the third direction Z.

[0026] In other words, by utilizing the wavy first trench 2 and second trench 5, stacked transistors T can be formed within the substrate 1. For example, the steps of forming the word line WL and the gate dielectric layer 31 include: forming a first isolation layer on the sidewall of the first sub-trench 20, exposing the substrate 1 at the junction of adjacent first sub-trench 20s; etching the substrate 1 at the junction of adjacent first sub-trench 20s to form a hole 21; forming a gate dielectric layer 31 covering the inner wall of the hole 21; and then depositing the word line WL within the hole 21. The step of forming the first source / drain 61 includes: after forming the word line WL, removing the first isolation layer to expose the sidewall of the first sub-trench 20; and doping the sidewall of the first sub-trench 20 to form the first source / drain 61. The steps for forming the second source / drain 62 include: forming a second isolation layer 51 on the sidewall of the second sub-trench 50, with the second isolation layer 51 exposing the substrate 1 at the junction of adjacent second sub-trench 50; and performing a doping treatment on the substrate 1 at the junction of adjacent first sub-trench 20 to form the second source / drain 62. This method helps reduce defects in the transistor T, thereby improving the performance of the semiconductor structure.

[0027] In some embodiments, continuing to refer to Figures 1(a), 1(b), 2(a), and 2(b), the aperture 21 also includes an insulating layer 33, located on the side of the word line WL facing the first trench 2. The gate dielectric layer 31 may also cover the surface of the insulating layer 33. The insulating layer 33 can prevent an overlap area between the word line WL and the first source / drain 61, or reduce the overlap area between them. That is, the insulating layer 33 can be directly opposite the first source / drain 61 in the first direction X, thereby offsetting the first source / drain 61 and the word line WL in the first direction X, thus preventing leakage between the first source / drain 61 and the word line WL. Additionally, the insulating layer 33 can also isolate adjacent first source / drain 61s.

[0028] In some embodiments, there are multiple transistor groups T0, and the multiple transistor groups T0 are arranged in an array within the substrate 1. That is, the multiple transistor groups T0 are arranged in the second direction Y, and the multiple transistor groups T0 are also arranged in the third direction Z. In other words, the multiple transistor groups T0 arranged in the third direction Z constitute a transistor unit T1, and the multiple transistor units T1 are arranged in the second direction Y. Thus, the number of transistor groups T0 can be increased, thereby increasing the storage capacity of the semiconductor structure. It should be noted that the dashed box in Figure 1(d) shows the position of the orthographic projection of a transistor unit T1 on the substrate 1.

[0029] refer to Figures 1(a) to 2(c)The word line WL extends along the third direction Z, and one word line WL is shared by multiple transistors T in the same layer of the transistor unit T1. In some embodiments, the word lines WL are arranged in an array within the substrate 1, that is, multiple word lines WL are arranged in the first direction X, and multiple word lines WL are also arranged in the second direction Y.

[0030] Referring to Figures 1(a) and 2(a), the semiconductor structure further includes bit lines BL filled in the second trench 5, and each bit line BL is connected to a plurality of second source and drain electrodes 62 of the same transistor group T0. In some embodiments, the bit lines BL are arranged in an array in the substrate 1, that is, multiple bit lines BL are arranged in the second direction Y, and multiple bit lines BL are also arranged in the third direction Z.

[0031] In addition, in order to reduce the contact resistance between the bit line BL and the second source / drain 62, a first metal silicide layer 63 can also be formed between the bit line BL and the second source / drain 62.

[0032] Referring to Figures 1(b), 1(d), and 2(c), Figure 1(b) shows a cross-sectional view of the semiconductor structure shown in Figure 1(d) along the B-B1 direction, and Figure 2(c) is a magnified partial cross-sectional view of the semiconductor structure, with the cross-section perpendicular to the first direction X. The semiconductor structure further includes a third trench 9, which alternates with the second trench 5 along the third direction Z; the third trench 9 has an electrode layer 7 electrically connected to the substrate 1. The electrode layer 7 prevents charge accumulation within the substrate 1, thereby avoiding the floating body effect and improving the performance of the semiconductor structure.

[0033] For example, electrode layer 7 includes a heavily doped layer 71 and a conductive layer 73. The type of dopant ions in the heavily doped layer 71 can be the same as the type of dopant ions in the substrate 1, for example, both can be P-type doped. In this way, a fast outflow channel can be provided for the charge in the substrate 1, avoiding charge accumulation in the substrate 1. In the second direction Y, the doping depth of the heavily doped layer 71 is less than the doping depth of the second source / drain electrode 62. That is, the smaller doping depth of the heavily doped layer 71 can prevent the second source / drain electrode 62 from contacting the heavily doped layer 71, and also prevent the heavily doped layer 71 from contacting the gate dielectric layer 31, thereby avoiding leakage or short circuit problems.

[0034] The conductive layer 73 can be made of metals such as tungsten and titanium nitride, thereby reducing resistance. In addition, the electrode layer 7 may also include a second metal silicide layer 72 located between the heavily doped layer 71 and the conductive layer 73, which can reduce the contact resistance between the heavily doped layer 71 and the conductive layer 73.

[0035] In some embodiments, the third trench 9 includes a plurality of third sub-trenches 90 arranged in a first direction X, the sidewalls of the third sub-trenches 90 being convex. A heavily doped layer 71 is located within the substrate 1 at the junction of adjacent third sub-trenches 90; a conductive layer 73 fills the first trench 2. In other embodiments, the heavily doped layer 71 may also cover the entire sidewall of the third trench 9.

[0036] In some other embodiments, the substrate 1 may not have an electrode layer 7 and a third trench 9, in which case the width of the second trench 5 in the third direction Z may be equal to the width of the first trench 2 in the third direction Z.

[0037] Referring to Figures 1(a) and 2(a), the semiconductor structure further includes a dielectric layer 81 and a capacitor plate 82. The dielectric layer 81 is located on two opposite sidewalls of the first trench 2, and these two sidewalls are arranged in the second direction Y. The capacitor plate 82 fills the first trench 2, and the dielectric layer 81 is also located between the first source / drain electrode 61 and the capacitor plate 82. That is, the first source / drain electrode 61, the dielectric layer 81, and the capacitor plate 82 constitute a capacitor. The capacitor and the transistor T can form a basic memory cell.

[0038] When a turn-on voltage is supplied to the word line WL, two channels are formed, meaning current flows between the first source-drain 61 and the second source-drain 62 on both the upper and lower sides of the word line WL. When the transistor T is turned on, the capacitor can store or release charge.

[0039] refer to Figures 1(c) to 1(d) Figure 1(c) shows a cross-sectional view of the semiconductor structure shown in Figure 1(d) along the C-C1 direction. The semiconductor structure also includes a plurality of spaced-apart first isolation structures 41 and a plurality of spaced-apart second isolation structures 52. The plurality of first isolation structures 41 extend along the second direction Y and are arranged in the third direction Z. The plurality of second isolation structures 52 extend along the second direction Y and are arranged in the third direction Z. Furthermore, the width of the second isolation structure 52 in the second direction Y is smaller than the width of the first isolation structure 41 in the second direction Y.

[0040] The first trench 2, arranged adjacently in the third direction Z, is separated by the first isolation structure 41. The second trench 5 and the third trench 9, arranged adjacently in the third direction Z, are separated by the first isolation structure 41 or the second isolation structure 52. That is, in the third direction Z, the first source and drain electrodes 61 arranged adjacently are separated by the first isolation structure 41, the capacitor plates 82 arranged adjacently are separated by the first isolation structure 41, and the bit lines BL and electrode layers 7 are separated by the first isolation structure 41 or the second isolation structure 52. In other words, the first isolation structure 41 and the second isolation structure 52 are used to isolate the transistor groups T0 that are adjacent in the third direction Z.

[0041] Referring to Figure 1(c), the first isolation structure 41 covers multiple word lines WL, that is, the first isolation structure 41 does not cut off the word lines WL, and the word lines WL pass through multiple first grooves 2 in the third direction Z.

[0042] In some embodiments, the top of the first trench 2, the second trench 5 and the third trench 9 may also have a third isolation layer (not shown in the figure), which covers the upper surface of the capacitor plate 82, the upper surface of the bit line BL and the upper surface of the electrode layer 7, thereby protecting the capacitor plate 82, the bit line BL and the electrode layer 7.

[0043] refer to Figure 3 , Figure 3 This shows a top view of a semiconductor structure in the back-end manufacturing process for a more intuitive understanding. Figure 3 Only a partial structure is shown. After the front-end process is completed, a capacitor plug 83 is formed on the upper surface of the capacitor plate 82, a bit line contact layer BLC is formed on the upper surface of the bit line BL, and an electrode contact layer 74 is formed on the upper surface of the electrode layer 7. The capacitor plug 83, the bit line contact layer BLC, and the electrode contact layer 74 can all extend in the first direction X. Figure 3 The dashed box in the middle shows the position of the orthographic projection of a transistor group T1 onto substrate 1.

[0044] The following will provide a detailed explanation of the connection structure and relationship between the array region AR and the peripheral region P.

[0045] refer to Figure 4 The peripheral area P contains a sub-word line driver SWD, which is electrically connected to the word line WL and is used to provide an enable or disable signal to the word line WL. The connection relationship between the sub-word line driver SWD and the word line WL is as follows:

[0046] refer to Figures 4-5 The sub-word line driver SWD and the word line WL are electrically connected via lead posts 32. Specifically, the array region AR includes a memory region AR1 and a stepped region AR2, which are arranged in the third direction Z. The word line WL extends from the memory region AR1 into the stepped region AR2, and in the direction from the upper surface of the substrate 1 to the lower surface of the substrate 1, the lengths of the multiple word lines WL increase sequentially, that is, the lower the layer of the word line WL, the longer it is; the stepped region AR2 has multiple lead posts 32 extending in the first direction X, and the multiple lead posts 32 are connected one-to-one with the multiple word lines WL, and the lead posts 32 are electrically connected to the sub-word line driver SWD. That is, through layer etching, the orthographic projections of the word lines WL on the substrate 1 are staggered, and they are connected through the lead posts 32.

[0047] In some embodiments, reference Figure 4There are two step regions AR2, which are arranged in the third direction Z and located on opposite sides of the storage region AR1. This provides more space for the lead posts 32, thereby increasing the distance between multiple lead posts 32 and reducing the parasitic capacitance between adjacent lead posts 32.

[0048] In some embodiments, multiple sub-word line drivers (SWDs) are located on opposite sides of the array region AR arranged in the third direction Z. That is, the multiple sub-word line drivers (SWDs) are respectively positioned opposite the step region AR2. This reduces the distance between the sub-word line drivers (SWDs) and the step region AR2, thereby reducing trace length and trace resistance. Furthermore, since the sub-word line drivers (SWDs) need to occupy a large area on the substrate 1, and the lead posts 32 are arranged in the step region AR2 layer, it provides more ample space for the sub-word line drivers (SWDs).

[0049] In some embodiments, reference Figure 4 Multiple word lines WL of the same transistor unit T1 can extend from the same side of the array region AR to the same step region AR2, and the lead posts 32 connected to the word lines WL of the same transistor unit T1 are located on the same side of the array region AR. Therefore, multiple sub-word line drivers SWD electrically connected to the same transistor unit T1 can be located on the same side of the array region AR, which facilitates the electrical connection of the sub-word line drivers SWD to the lead posts 32, thereby reducing the trace length and reducing the trace resistance.

[0050] Furthermore, the word lines WL of adjacent transistor units T1 can extend from both sides of the array region AR into the two stepped regions AR2. This alternating arrangement helps improve the uniformity of the structure and increases the spacing between the multiple lead posts 32, thereby reducing parasitic capacitance. In addition, the multiple sub-word line drivers SWD electrically connected to adjacent transistor units T1 are located on different sides of the array region AR, so that the multiple sub-word line drivers SWD are evenly distributed in the peripheral region P, which also provides more space for the sub-word line drivers SWD and reduces space waste.

[0051] It should be noted that since the upper and lower transistors T share a common first source-drain 61, to prevent read / write errors, the two adjacent transistors T can not be turned on simultaneously. That is, the sub-word line driver SWD does not simultaneously provide enable signals to the two adjacent word lines WL in the first direction X.

[0052] In some embodiments, transistor T includes an isolation transistor and active transistors, which are alternately arranged in a first direction X. A normally off voltage is supplied to the isolation transistor to isolate the two active transistors. In other words, an isolation transistor is provided between the two active transistors, thereby increasing the distance between the active transistors, and the isolation transistor is in a normally off state, thus isolating the two active transistors and preventing mutual interference between adjacent active transistors.

[0053] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The word line WL of the effective transistor is the first word line WL1, and the word line WL of the isolation transistor is the second word line WL2. That is, the word line WL includes first word lines WL1 and second word lines WL2 alternately arranged in the first direction X. Multiple first word lines WL1 are electrically connected to different sub-word line drivers SWD, and multiple second word lines WL2 are connected to the same normally-off signal source. Specifically, multiple first word lines WL1 are connected to different sub-word line drivers SWD through first wires 34. Multiple second word lines WL2 can be connected together through second wires 35, and a normally-off signal source applies a normally-off signal to the second wires 35. In some embodiments, the second wire 35 can be directly connected to the normally-off signal source. In other embodiments, the second wire 35 can be connected to the sub-word line driver SWD that provides the normally-off signal. This reduces the number of sub-word line drivers SWD, thereby reducing the size of the semiconductor structure.

[0054] It should be noted that the first conductor 34 and the second conductor 35 can be connected to the lead post 32 from opposite sides, thereby avoiding crossing and reducing interference. For example, refer to... Figure 4 The first conductor 34 is connected to the left side of the lead post 32, and the second conductor 35 is connected to the left side of the lead post 32.

[0055] In other embodiments, each word line WL may also be electrically connected to a different sub-word line driver SWD, so that the active transistor and the isolation transistor can switch to each other according to the signal provided by the sub-word line driver SWD, thus allowing for more flexible use of transistor T.

[0056] refer to Figures 6-8 The peripheral region P also contains a sensing amplifier SA, which is electrically connected to the bit line BL. The sensing amplifier SA is used to detect the signal on the bit line BL and amplify the signal on the bit line BL. The connection structure and relationship between the sensing amplifier SA and the bit line BL are as follows:

[0057] refer to Figure 6After forming the capacitor plug 83, bit line contact layer BLC, and electrode contact layer 74, the method further includes: forming a first contact layer 84 on the upper surface of the capacitor plug 83, forming a second contact layer BL2 on the upper surface of the bit line contact layer BLC, and forming a third contact layer 75 on the upper surface of the electrode layer 7. Except for the first contact layer 84, second contact layer BL2, and third contact layer 75 located at the edge, the remaining first contact layer 84, second contact layer BL2, and third contact layer 75 located in the middle of the array region AR are shared by two adjacent transistor groups T0 arranged in the second direction Y. That is, the capacitor plate 82 is shared by the transistor groups T0 on both sides, the bit line BL is shared by the transistor groups T0 on both sides, and the electrode layer 7 is shared by the transistor groups T0 on both sides. This improves the utilization efficiency of the substrate 1 area.

[0058] In some embodiments, a plurality of first contact layers 84 and a plurality of third contact layers 75 are arranged in a straight line, and a plurality of second contact layers BL2 are arranged in another straight line. This arrangement facilitates the subsequent installation of connecting wires.

[0059] Reference Figure 6 and Figure 7 The sensing amplifier SA and the bit line BL can be electrically connected via the bit line connection line BL1.

[0060] Specifically, multiple bit line connection lines BL1 extend in the second direction Y and are arranged in the third direction Z; the bit line connection lines BL1 are electrically connected to multiple bit lines BL, that is, the bit line connection lines BL1 connect to a row of second contact layers BL2 arranged in the second direction Y, thereby electrically connecting a row of bit lines BL. The bit line connection lines BL1 are intersected with word lines WL, and the intersection point of the two can correspond to a transistor T.

[0061] In some embodiments, multiple sensing amplifiers SA are located on opposite sides of the array region AR, arranged in the second direction Y. This provides more space for the sensing amplifiers SA. Additionally, a fourth contact layer BL3 is provided at the end of the bit line connection line BL1, which is used for electrical connection with the sensing amplifiers SA. When multiple sensors are located on opposite sides of the array region AR, the multiple fourth contact layers BL3 are also located at opposite edges of the array region AR, which helps to increase the spacing between the fourth contact layers BL3, thereby reducing the parasitic capacitance between the fourth contact layers BL3. In other embodiments, the multiple sensing amplifiers SA may also be located on the same side of the array region AR.

[0062] Adjacent bit line connectors BL1 connect the sensing amplifiers SA on different sides of the array region AR. Therefore, the arrangement of multiple sensing amplifiers SA is more uniform and the manufacturing process is simpler. In addition, the spacing between multiple fourth contact layers BL3 on the same side is the same, which is beneficial for balancing parasitic capacitance.

[0063] refer to Figure 8 , Figure 8 This is a partial cross-sectional view of the bit line connector BL1, with the cross-section perpendicular to the second direction Y. The top and sidewalls of the bit line connector BL1 have a fourth isolation layer 64 to protect the bit line connector BL1 and isolate it from the word line WL. The material of the fourth isolation layer 64 can be silicon nitride or silicon oxide.

[0064] The peripheral region P also contains a bias signal source (not shown in the figure). The electrode layer 7 is electrically connected to the bias signal source, which provides a bias signal to the electrode layer 7 to fix the potential of the substrate 1 and prevent charge accumulation in the substrate 1. The connection structure and relationship between the electrode layer 7 and the bias signal source are described below:

[0065] refer to Figure 9 The semiconductor structure further includes: electrode connection lines 76, which are electrically connected to a plurality of electrode layers 7 and connected to a bias signal source. In some embodiments, the electrode connection lines 76 include a first electrode connection line 77 and a plurality of second electrode connection lines 78 connected together, wherein the first electrode connection line 77 extends in a second direction Y, and the second electrode connection lines 78 extend in a third direction Z; the second electrode connection lines 78 are electrically connected to the plurality of electrode layers 7, that is, the second electrode connection lines 78 are connected to a third contact layer 75 (reference). Figure 7 The electrodes are connected to each other, and then electrically connected to the electrode layer 7. Through this connection method, multiple electrode layers 7 can obtain the same bias signal, which helps to simplify the structure.

[0066] The peripheral region P also contains a capacitor signal source (not shown in the figure), and the capacitor plate 82 is electrically connected to the capacitor signal source. The bias signal source provides a capacitor signal to the capacitor plate 82. The connection structure and relationship between the capacitor plate 82 and the capacitor signal source are described below:

[0067] refer to Figure 9 The semiconductor structure also includes: electrode connection lines 85, which are electrically connected to multiple capacitor electrodes 82 and to a capacitor signal source. In some embodiments, the electrode connection lines 85 include a first electrode connection line 86 and multiple second electrode connection lines 87 connected together, wherein the first electrode connection line 86 extends in a second direction Y, and the second electrode connection lines 87 extend in a third direction Z; the second electrode connection lines 87 are electrically connected to the multiple capacitor electrodes 82. Through the above connection method, the multiple capacitor electrodes 82 can acquire the same capacitor signal, thereby simplifying the structure. For example, the capacitor signal can be a ground voltage.

[0068] In some embodiments, the first electrode connection line 86 and the first electrode connection line 77 are located on opposite sides of the array region AR; the second electrode connection line 87 and the second electrode connection line 78 are arranged alternately in the second direction Y. Therefore, the arrangement of the electrode connection line 85 and the electrode connection line 76 is simpler and avoids crossing relationships between them, thereby reducing signal interference. This arrangement also helps to shorten the length of the electrode connection line 85 and the electrode connection line 76. Furthermore, the electrode connection line 85 and the electrode connection line 76 can be arranged in the same layer, meaning they can be formed through the same process step, which helps to reduce production costs. Additionally, a third isolation structure 79 can be provided between the electrode connection line 85 and the electrode connection line 76, and the material of the third isolation structure 79 can be silicon nitride.

[0069] refer to Figure 10 , Figure 10 The complete semiconductor structure is shown. In summary, the semiconductor structure provided in this disclosure embodiment has 3D stacked transistors and capacitors, which constitute memory cells. In the first direction X, interference between adjacent memory cells can be avoided by not simultaneously enabling adjacent memory cells. Specifically, the word lines WL include alternating first word lines WL1 and second word lines WL2 in the first direction X. Multiple first word lines WL1 can be connected to different sub-word line drivers SWD, and the signal on the second word line WL2 can be a normally off signal. Additionally, the bit lines BL are electrically connected together via a bit line connection line BL1 and connected to the sense amplifier SA. All electrode layers 7 can be electrically connected together, and all capacitor plates 82 can be electrically connected together. The aforementioned layout helps reduce signal interference and avoids wasted space, thereby improving the performance of the semiconductor structure.

[0070] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0071] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, said semiconductor structure comprising an array region and a peripheral region, characterized in that, include: A substrate, wherein the array region has a transistor group within the substrate, the transistor group comprising multilayer transistors arranged in a first direction; each transistor includes a word line, a second source / drain, and two first source / drains, the word line and the second source / drain being arranged in a second direction, the two first source / drains being arranged in the first direction and located on opposite sides of the word line; in the first direction, two adjacent transistors share one first source / drain. The peripheral area has a sub-word line driver, the word line is electrically connected to the sub-word line driver, and the sub-word line driver does not simultaneously provide an enable signal to two adjacent word lines in the first direction; The transistor groups are multiple, and the multiple transistor groups arranged in a third direction constitute a transistor unit, and the multiple transistor units are arranged in the second direction; the third direction is perpendicular to the second direction, and both are perpendicular to the first direction; The word line extends along the third direction, and one word line is shared by multiple transistors in the same layer of the transistor unit; The plurality of the sub-word line drivers are respectively located on opposite sides of the array region arranged in the third direction; Multiple sub-word line drivers electrically connected to the same transistor cell are located on the same side of the array region; multiple sub-word line drivers electrically connected to adjacent transistor cells are located on different sides of the array region.

2. The semiconductor structure according to claim 1, characterized in that, The word lines include first word lines and second word lines arranged alternately in the first direction, wherein multiple first word lines are electrically connected to different sub-word line drivers, and multiple second word lines are connected to the same normally off signal source.

3. The semiconductor structure according to claim 1, characterized in that, The array area includes a storage area and two stepped areas, which are arranged upwards on the third side and located on opposite sides of the storage area. The word lines extend from the storage area into the stepped area, and in the direction from the upper surface of the substrate to the lower surface of the substrate, the lengths of the multiple word lines increase sequentially. The stepped area has a plurality of lead posts extending in the first direction, and the plurality of lead posts are connected one-to-one with the plurality of word lines, and the lead posts are electrically connected to the sub-word line driver.

4. The semiconductor structure according to claim 1, characterized in that, The substrate has a first trench and a second trench arranged alternately in the second direction, and the depth direction of both trenches is the first direction. The first trench includes a plurality of first sub-trenches arranged in the first direction; The second trench includes a plurality of second sub-trenches arranged in the first direction; The word line is located at the junction of adjacent first sub-grooves and protrudes outward from the interior of the first groove. The word line is also located between the first groove and the second groove. The first source and drain electrodes are located on two opposite sidewalls of the first sub-grooves. The second source and drain are located at the junction of adjacent second sub-trenches and protrude outwards from the interior of the second trench; the second source and drain are also located between the first trench and the second trench.

5. The semiconductor structure according to claim 4, characterized in that, The transistor groups are multiple, and the multiple transistor groups are arranged in an array within the substrate; The semiconductor structure further includes: bit lines filling the second trench, and each bit line is connected to a plurality of second source and drain electrodes of the same transistor group.

6. The semiconductor structure according to claim 5, characterized in that, A plurality of the first trenches are arranged in a third direction, and a plurality of the second trenches are arranged in the third direction; The semiconductor structure further includes: a plurality of bit line connection lines extending in the second direction and arranged in the third direction; the bit line connection lines are electrically connected to the plurality of bit lines; The peripheral area also includes a sensing amplifier, and the bit line connection line is electrically connected to the sensing amplifier.

7. The semiconductor structure according to claim 6, characterized in that, The plurality of the sensing amplifiers are respectively located on opposite sides of the array region arranged in the second direction; The adjacent bit line connection lines are respectively connected to the sensing amplifiers on different sides of the array region.

8. The semiconductor structure according to claim 4, characterized in that, Also includes: The third groove is alternately arranged with the second groove in a third-direction orientation; The third trench has an electrode layer, which is electrically connected to the substrate. The semiconductor structure further includes: electrode connection lines, which are electrically connected to the plurality of electrode layers and electrically connected to a bias signal source.

9. The semiconductor structure according to claim 8, characterized in that, Also includes: A dielectric layer and capacitor plates, wherein the dielectric layer is located on two opposite sidewalls of the first trench; The capacitor plate is filled in the first trench, and the dielectric layer is also located between the first source and drain electrodes and the capacitor plate. The semiconductor structure further includes: an electrode connection line, which is electrically connected to a plurality of capacitor electrodes and electrically connected to a capacitor signal source.

10. The semiconductor structure according to claim 9, characterized in that, The electrode connection line includes a first electrode connection line and multiple second electrode connection lines connected together, wherein the first electrode connection line extends in the second direction, and the second electrode connection lines extend in the third direction; the second electrode connection lines are electrically connected to the multiple capacitor electrodes. The electrode connection line includes a first electrode connection line and a plurality of second electrode connection lines connected together, wherein the first electrode connection line extends in the second direction, and the second electrode connection lines extend in the third direction; the second electrode connection lines are electrically connected to the plurality of electrode layers. The first electrode plate connection line and the first electrode connection line are located on opposite sides of the array region; the second electrode plate connection line and the second electrode connection line are arranged alternately in the second direction.

11. The semiconductor structure according to claim 8, characterized in that, The third trench includes a plurality of third sub-trenches arranged in the first direction; The electrode layer includes a heavily doped layer and a conductive layer. The heavily doped layer is located within the substrate at the junction of adjacent third sub-trenches. The conductive layer fills the first trench.

12. The semiconductor structure according to claim 11, characterized in that, The sidewalls of the first sub-groove, the second sub-groove, and the third sub-groove are all convex.

13. The semiconductor structure according to claim 4, characterized in that, The junction of adjacent first sub-grooves has a hole protruding away from the first groove; The letter line is located inside the hole; The inner wall of the hole also has a gate dielectric layer, which covers the surface of the word line and is in contact with the first source / drain and the second source / drain; The hole also has an insulating layer, which is located on the side of the letter line facing the first groove.

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