Channel prediction behavior and fault analysis

Abstract

Channel prediction behavior and fault analysis can be provided. The forward time value can be determined, which includes the time it takes for the forward signal to travel from the transmitter through the channel to the receiver. Next, the reflection time value can be determined, which includes the time it takes for the reflected signal to travel to the receiver. The reflected signal can be correlated with the forward signal. Discontinuities in the channel can then be identified based on the forward and reflection time values. Reflected signals may be caused by discontinuities and high or low impedance present at the transmitter after the forward signal has been transmitted.

Description

[0001] Cross-reference to related applications

[0002] This application, filed as a PCT international patent application on June 3, 2022, claims the benefit and priority of U.S. Provisional Patent Application No. 17 / 342,316, filed on June 8, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to channel prediction behavior and fault analysis. Background Technology

[0004] A serializer / deserializer (SerDes) is a pair of functional blocks used in high-speed communication to compensate for limited input / output (I / O). These functional blocks convert data between serial and parallel interfaces in each direction. The term "SerDes" generally refers to the interface used in a variety of technologies and applications. The primary purpose of SerDes is to provide data transmission over single wires or differential pairs to minimize the number of I / O pins and interconnects.

[0005] The basic functionality of SerDes consists of two functional blocks: i) Parallel In Serial Out (PISO) block (i.e., parallel-to-serial converter); and ii) Serial In Parallel Out (SIPO) block (i.e., serial-to-parallel converter). There are four different SerDes architectures: i) Parallel Clock SerDes; ii) Embedded Clock SerDes; iii) 8b / 10b SerDes; and iv) Bit-Interleaved SerDes.

[0006] A PISO block typically has a parallel clock input, a set of data input lines, and an input data latch. It can use an internal or external phase-locked loop (PLL) to multiply the input parallel clock by the serial frequency. The simplest form of a PISO has a single shift register that receives parallel data once per parallel clock cycle and shifts it out at a higher serial clock rate. Implementations can also utilize double-buffered registers to avoid metastability when transferring data between clock domains.

[0007] The SIPO block has a receive clock output, a set of data output lines, and an output data latch. The receive clock can be recovered from the data using serial clock recovery techniques. However, the SerDes, which does not transmit a clock, uses a reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the input clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used for timing in the serial stream, while the other register is used to hold data for the slower parallel side. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate various embodiments of the present disclosure. In the drawings:

[0009] Figure 1 This is a block diagram of the operating environment used to provide connectivity failure detection;

[0010] Figure 2 This is a flowchart of a method for providing connectivity fault detection;

[0011] Figure 3A , Figure 3B and Figure 3C This demonstrates connectivity failure detection; and

[0012] Figure 4 It is a block diagram of a computing device. Detailed Implementation

[0013] The invention is set forth in the independent claims, and preferred features are set forth in the dependent claims. A feature of one aspect may be applied individually to each aspect or in combination with other aspects to each aspect.

[0014] Channel prediction behavior and fault analysis can be provided. The forward time value can be determined, which includes the time it takes for the forward signal to travel from the transmitter through the channel to the receiver. Next, the reflection time value can be determined, which includes the time it takes for the reflected signal to travel to the receiver. The reflected signal can be correlated with the forward signal. Discontinuities in the channel can then be identified based on the forward and reflection time values. Reflected signals are caused by discontinuities and high or low impedance present at the transmitter after the forward signal has been transmitted.

[0015] The foregoing overview and the following exemplary embodiments are both illustrative and explanatory only, and should not be considered as limiting the scope of the described and claimed disclosure. Furthermore, features and / or variations may be provided in addition to the described features and / or variations. For example, embodiments of the disclosure may be directed to various combinations and sub-combinations of features described in the exemplary embodiments.

[0016] Example Implementation

[0017] The following detailed description refers to the accompanying drawings. Where possible, the same reference numerals are used in the drawings and the following description to refer to the same or similar elements. While embodiments of the present disclosure can be described, modifications, adjustments, and other implementations are possible. For example, elements shown in the drawings may be replaced, added, or modified, and the methods described herein may be modified by replacing, reordering, or adding stages to the disclosed methods. Therefore, the following detailed description does not limit the present disclosure. Rather, the appropriate scope of the present disclosure is defined by the appended claims.

[0018] Typically, pins on the backplane / printed circuit board (PCB) or cable connectors may not form a good electrical connection (e.g., resulting in discontinuities), which can lead to signal reflection or partial signal loss. This can cause SerDes link failure or bit error rate (BER) degradation. Therefore, it may be necessary to locate the physical connectivity failure so that the user can try to improve or replace the connection.

[0019] Traditional systems can use a time-domain reflectometer (TDR) to detect connectivity failures. This can be done using a driver that can both transmit and receive signals. Some high-speed SerDes can only operate in one direction. This may mean that the receiver may only receive signals and not transmit. Similarly, the transmitter may only transmit signals and not receive them. Accordingly, it is not possible to use a TDR to detect channel connectivity failures in a SerDes receiver.

[0020] Embodiments of this disclosure provide a process for detecting connectivity faults without the transmitter detecting reflected signals. Unlike optical TDR (OTDR) and full-duplex (where the driver can both transmit and receive) methods, embodiments of this disclosure can detect signals using only a receiver and measure the location of discontinuities based on the time difference between the direct signal transmitted from the transmitter to the receiver and the reflected signal transmitted to the receiver.

[0021] In situations with a large number of links on electronic devices, channel prediction behavior and fault analysis can be challenging. Embodiments of this disclosure can provide link analysis using metrics obtained from data collection and applied machine learning (ML). Link analysis can be used to predict link performance on other systems that also use similar metrics. Metrics used in this link analysis may include those obtained from the aforementioned connectivity fault detection.

[0022] Furthermore, SerDes power may account for a significant portion of the total chip power (e.g., 20%). With a large number of chips (e.g., 30) used in each modular / backplane system, energy consumption can be substantial. Embodiments of this disclosure can provide a “green” optimization process that minimizes energy costs through metric-based system power and performance tradeoffs. Metrics used in this optimization may include those obtained from the aforementioned connectivity failure detection.

[0023] Connectivity Failure Detection

[0024] Figure 1 An operating environment 100 for providing connectivity failure detection is shown. For example... Figure 1 As shown, the operating environment 100 may include a transmitter 105, a receiver 110, and a channel 115 connecting the transmitter 105 and the receiver 110. According to embodiments of this disclosure, the transmitter 105 may include a SerDes transmitter, and the receiver 110 may include a SerDes receiver. The transmitter 105 and the receiver 110 may be included in a SerDes link. Figure 1 As shown, channel 115 may include discontinuity 120 (e.g., a defect or poor electrical connection). As described in more detail below, a forward signal 125 may be transmitted from transmitter 105 through discontinuity 120 and may be received by receiver 110. The forward signal 125 may include, but is not limited to, a step or pulse signal.

[0025] The aforementioned components of operating environment 100 (e.g., transmitter 105 and receiver 110) can be implemented in hardware and / or software (including firmware, resident software, microcode, etc.) or any other circuit or system. The components of operating environment 100 can be implemented in circuits (including discrete electronic components, packaged or integrated electronic chips containing logic gates, circuits utilizing microprocessors), or on a single chip containing electronic components or a microprocessor. Furthermore, the components of operating environment 100 can also be implemented using other technologies capable of performing logical operations (e.g., AND, OR, NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. See below for reference. Figure 4 In more detail, the components of the operating environment 100 can be implemented in the computing device 400.

[0026] Figure 2 This is a flowchart illustrating the overall stages involved in a method 200 for providing connectivity failure detection according to embodiments of this disclosure. Method 200 can be described using the methods referenced above. Figure 1The receiver 110 will be implemented in more detail below. For example, in some embodiments of this disclosure, method 200 may be implemented at the firmware level of the SerDes, which includes transmitter 105 and receiver 110. The manner in which the various stages of implementing method 200 are implemented will be described in more detail below.

[0027] Method 200 may begin at start block 205 and proceed to stage 210, in which receiver 110 may determine a forward time value that includes the time taken for the forward signal 125 to travel from transmitter 105 to receiver 110 on channel 115. For example, the forward time value may include t d , where t d It can include t r1 and t r2 The sum (i.e., t) d =t r1 +t r2 ).like Figure 3A , Figure 3B and Figure 3C As shown, t r1 This can include the time taken for the forward signal 125 to travel from the transmitter 105 to the discontinuity 120. After the forward signal 125 reaches the discontinuity 120, t r2 This may include the time it takes for the forward signal 125 to travel from the discontinuity point 120 to the receiver 110.

[0028] Starting from stage 210, where receiver 110 determines the forward time value (including the time required for the forward signal 125 to travel from transmitter 105 to receiver 110 via channel 115), method 200 can proceed to stage 220, where receiver 110 can determine the reflection time value (including the time required for the reflected signal 130 to travel to receiver 110). The reflected signal 130 may be associated with the forward signal 125. For example, the reflection time value may include t r , t r It can include three t r1 With t r2 The sum of (i.e., t) r =3t r1 +t r2 ).

[0029] like Figure 3A , Figure 3B and Figure 3C As shown, t r1 This can include the time taken for the forward signal 125 to travel from the transmitter 105 to the discontinuity 120. r1 After reaching the discontinuity point 120 within the range, t r1 It may also include reflected signal 130 (i.e., such as...) Figure 3A The forward signal 125 shown in the reflection form is reflected from the discontinuity 120 and travels back to the transmitter 105 from the discontinuity 120 (e.g., as shown in the reflection form). Figure 3B The time taken (as shown). Because transmitter 105 may have been turned off after sending forward signal 125, when reflected signal 130 is transmitted to transmitter 105, reflected signal 130 may be reflected from transmitter 105, and in time t... r1 The internal path travels from transmitter 105 back to discontinuity point 120. (Example) Figure 3C As shown, once the reflected signal 130 is transmitted to the discontinuity point 120, t r2 This can include the time it takes for the reflected signal 130 to travel from the discontinuity 120 to the receiver 110. Accordingly, starting from the initial transmission of the forward signal 125 from the transmitter 105, the reflected signal 130 can travel at time t. r Inside (e.g., t) r =3t r1 +t r2 () is transmitted to receiver 110.

[0030] As described above, once the forward signal 125 is initially transmitted from the transmitter 105, the transmitter 105 can be turned off, thereby creating a high-impedance (e.g., open-circuit point) or low-impedance state to induce reflection at the transmitter 105. Turning off the transmitter 105 can create conditions for the reflected signal 130 to be reflected from the transmitter 105. According to embodiments of this disclosure, conditions can be created at the transmitter 105 to induce signal reflection. For example, these conditions may include, but are not limited to, the created low impedance or the created high impedance.

[0031] Once receiver 110 has determined the reflection time value (including the time required for reflected signal 130 to travel to receiver 110) in stage 220, method 200 may proceed to stage 230, where receiver 110 may determine the presence of discontinuity 120 on channel 115 based on the forward time value and the reflection time value. The reflected signal may be caused by discontinuity 120 and by a high or low impedance present at transmitter 105 after the transmission of forward signal 125. For example, if receiver 110 receives a reflected version of forward signal 125 (i.e., reflected signal 130) at some time after receiving forward signal 125, and if the amplitude of the reflected version of forward signal 125 (i.e., reflected signal 130) is greater than a predetermined threshold, receiver 110 may determine that discontinuity 120 exists.

[0032] Furthermore, receiver 110 can determine the location of discontinuity 120 based on forward time and reflection time values. According to embodiments of this disclosure, in determining the location of discontinuity 120, receiver 110 can determine the distance in channel 115 from receiver 110 to discontinuity 120. For example, transmitter 105 and receiver 110 can be synchronized. Receiver 110 can know the time when forward signal 125 was transmitted from transmitter 105. For example, transmitter 105 can transmit the time of transmission of forward signal 125 via a timestamp in forward signal 125 or by other means. Receiver 110 can record the time when forward signal 125 was received at receiver 110. The difference between the time when forward signal 125 was transmitted from transmitter 105 and the time when forward signal 125 was received at receiver 110 can include the forward time value t as described above. d Similarly, receiver 110 can record the time at which the reflected signal 130 is received at receiver 110. The difference between the time when the forward signal 125 is transmitted from transmitter 105 and the time when the reflected signal 130 is received at receiver 110 can include the reflection time value t as described above. r .

[0033] t d and t r The above equation (i.e., t) d =t r1 +t r2 and t r =3t r1 +t r2 ) can be solved as: t r2 =0.5 (3t) d -t r Accordingly, the distance from receiver 110 to discontinuity 120 in channel 115 may include t. r2 Multiply by c and divide by The square root (i.e., ), where c is the speed of light in a vacuum, and t is the dielectric constant of the transmission line dielectric (i.e., channel 115). Similarly, the distance from transmitter 105 to discontinuity 120 in channel 115 can be expressed in a similar manner using t. r1 The method 200 can end in stage 240 after the receiver 110 determines that there is a discontinuity 120 on the channel 115 based on the forward time value and the reflection time value in stage 230.

[0034] Link analysis using metrics obtained from data collection and applied ML.

[0035] Because there are numerous high-speed channel links on the hardware board, it may be necessary to be able to track metrics related to the quality of each link at different times, on different PCBs, and under different environmental conditions. According to embodiments of this disclosure, these metrics may include, for example, those referenced above. Figure 2 The described metrics are associated with open or short circuits (e.g., discontinuities) in a link. Other examples may be associated with how link quality is determined. Accordingly, embodiments of this disclosure may include a process for debugging, detecting, analyzing, and monitoring a link, collecting data over time via system logs or the cloud, and utilizing ML processes that can be used to predict link performance as a similar metric on other systems. As described in more detail below, this process may be performed by computing device 400.

[0036] In addition to the above references Figure 2 In addition to metrics associated with open or short circuits in the link, the description may include: i) loss and impulse response; ii) bit error rate (BER) / mean square error (MSE) / signal-to-noise ratio (SNR) / eye opening curves (horizontal and vertical) / bathtub curves (horizontal and vertical); iii) pre-forward error correction (FEC) BER data / post-FEC BER data; iv) analog-to-digital converter (ADC) saturation, synthetic aperture radar (SAR) values; v) sum of gain levels equal to the total equalization applied for prediction; vi) continuous-time linear equalization (CTLE) values, automatic gain control (AGC) values; and vii) timestamp metrics over time. For example, metrics and data can be extracted from a SerDes design. In some cases (e.g., predictive loss), this can be calculated as a Fourier transform of the impulse response.

[0037] Embodiments of this disclosure may include a process for providing channel prediction behavior and fault analysis. This process may include measuring metrics on links (e.g., with reference to the above) among multiple high-speed channel links (e.g., SerDes links) on a hardware board in an electronic device. Figure 2 The metrics associated with open or short circuits in the described links. The measured metrics (labeled by link type and timestamp) can be categorized into multiple buckets. For example, buckets can include, but are not limited to, loss buckets, equalization buckets, and BER buckets. If the BER is poor (e.g., below a predetermined level), the link can be shut down for analysis. In the analysis, pre-FEC / post-FEC data can be collected along with SNR, impulse response, SAR values, and other metrics. If the BER is good (e.g., above a predetermined level), timestamped data can be collected to serve as the initial ML dataset.

[0038] Once sufficient data has been collected over time on a specific system or channel of a specific type, embodiments of this disclosure can begin building an initial dataset for an ML algorithm. In other words, initial data and data preparation can be performed, an ML model can be trained, the model can be evaluated (and retrained), the model can be deployed, and results can be collected. Over time, the timestamp data can be used to perform the following operations: i) outliers in link quality can be identified; ii) unexpected receiver behavior can be detected; iii) small changes in the metrics / parameters used to build buckets can be tracked; and iv) links can be challenged with alternative metrics to reconstruct the ML model from the initial dataset. Accordingly, the use of the ML model can include, but is not limited to: i) applying tracking equalization with a BER target specific to a loss bucket; ii) converting training data for equalization and BER metrics into loss metrics; iii) new links on new systems can use the trained ML data to predict BER or equalization metrics from expected loss data; iv) the ML model can be used to check link quality as expected and improve the ML model. (For example, for users who are permitted to collect data via the cloud) Data can be collected via the cloud. Alternatively, data can be collected via a standard console port based on system log messages and then transmitted to a local server.

[0039] According to embodiments of this disclosure, preventative maintenance windows and full maintenance windows can be used. Preventative maintenance windows can enable data collection on various links via system logs or the cloud. Through preventative maintenance windows, a predetermined link can be dropped, a metric test can be run, and the link can be re-enabled. An ML model can then be used to compare predicted and actual changes in the metric to create quality metrics. Thus, predictions about which links might cause potential problems over time can be made based on the ML model. If any metric goes out of range, a full maintenance window can be run. Through full maintenance windows, the identified link can be dropped, SerDes can be retuned, the metric test can be run again, and then the link can be re-enabled.

[0040] Green mode optimization process that minimizes energy costs

[0041] There can be multiple lines (i.e., links) on the system, some of which are channels to the backplane, some to the front end, and some are chip-to-chip channels. Embodiments of this disclosure may include a process for optimizing SerDes power relative to performance to repurchase some thermal footprint (i.e., power benefit) for performance. In other words, embodiments of this disclosure can repurchase power margins by optimizing line performance in response to link analysis and not running SerDes in full-power mode if full power is not required. As described in more detail below, this process can be performed by computing device 400.

[0042] SerDes power can be contributed by various individual blocks, such as PLLs, digital blocks, ADCs, feedforward equalizers (FFEs), and decision feedback equalizers (DFEs). The power of some blocks may vary with the bit rate, while others may not, thus power may be bit rate-dependent. For example, converting a 16-delimited FFE to an 8-delimited FFE can reduce the power of the FFE block by 65%. Reducing a 7-bit ADC to a 3-bit ADC may reduce power consumption on the analog side by 10% and save some power on the digital side. Reducing the number of finite impulse response (FIR) taps in the transmitter can further save power. This may not necessarily degrade SerDes performance, but rather is optimized based on accurate system channel information and the correct metric trade-offs. In addition to power cost-effectiveness, reducing power consumption can also bring thermal benefits from a system cooling perspective.

[0043] During this process, predictive channel failure analysis can be used to check line (i.e., link) quality as described above. If the line is healthy, link loss analysis can be performed to optimize power, packet drop, or bit rate power scaling, etc. With power optimization, a target BER can be set, and each SerDes block can be optimized against that target BER to track BER reduction. In other words, the relationship between power and target BER can be tracked to optimize line SerDes power. With packet drop optimization, an acceptable target percentage of packet loss and a new BER target can be set. Then power optimization is run again. With bit rate power scaling optimization, lines that can have their link rates reduced can be selected and a BER target can be set. The BER target can be set according to user tolerances or requirements, using user-defined values. Then power optimization is run again.

[0044] Figure 4 A computing device 400 is shown. (For example...) Figure 4 As shown, computing device 400 may include a processing unit 410 and a memory unit 415. Memory unit 415 may include software module 420 and database 425. Software module 420, when executed on processing unit 410, may perform (for example) as described above. Figure 2 The description includes a process for providing connectivity failure detection. For example, computing device 400 can provide an operating environment for transmitter 105 or receiver 110. Transmitter 105 or receiver 110 can operate in other environments, not limited to computing device 400.

[0045] Computing device 400 can be implemented using Wi-Fi access points, tablet devices, mobile devices, smartphones, telephones, remote control devices, set-top boxes, digital video recorders, cable modems, personal computers, network computers, mainframes, routers, switches, server clusters, smart TV devices, network storage devices, network relay devices, or other similar microcomputer-based devices. Computing device 400 can include any computer operating environment, such as handheld devices, multiprocessor systems, microprocessor-based or programmable transmitter electronics, minicomputers, mainframes, etc. Computing device 400 can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices. The systems and devices described above are examples, and computing device 400 can include other systems or devices.

[0046] Embodiments of this disclosure may include a method for providing connectivity failure detection. The method may include: determining a forward time value by a receiver, the forward time value including the time taken for a forward signal to travel from a transmitter through a channel to the receiver; determining a reflection time value by the receiver, the reflection time value including the time taken for a reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and determining, based on the forward time value and the reflection time value, that a discontinuity exists in the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal has been transmitted. Determining the existence of the discontinuity further includes: determining that the amplitude of the reflected signal is greater than a predetermined value. The method may further include: determining the location of the discontinuity based on the forward time value and the reflection time value. Determining the location of the discontinuity may include: determining the distance in the channel from the receiver to the discontinuity. The reflected signal is a reflected version of the forward signal, reflected from the discontinuity, traveling back to the transmitter, reflected from the transmitter due to high or low impedance, and traveling through the discontinuity to the receiver. The high or low impedance at the transmitter is caused by shutting down the transmitter after transmitting a forward signal. The method may also include: using the identified discontinuities to predict link performance on another system, or using the identified discontinuities to determine whether a lower power level can be sustained on the channel.

[0047] Another embodiment of this disclosure may include a system for providing connectivity failure detection. The system may include a memory and a processing unit disposed in a receiver and coupled to the memory. The processing unit may be operated to: determine a forward time value, including the time taken for a forward signal to travel from the transmitter through the channel to the receiver; determine a reflection time value, including the time taken for a reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and determine, based on the forward time value and the reflection time value, that a discontinuity exists in the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal has been transmitted. The processing unit being operated to determine the existence of the discontinuity further includes: the processing unit being operated to determine that the amplitude of the reflected signal is greater than a predetermined value. The processing unit may also be operated to determine the location of the discontinuity based on the forward time value and the reflection time value. The processing unit being operated to determine the location of the discontinuity includes: the processing unit being operated to determine the distance in the channel from the receiver to the discontinuity. A reflected signal is a reflected version of the forward signal. The reflected signal is reflected from a discontinuity, travels back to the transmitter, is reflected from the transmitter due to high or low impedance, and travels to the receiver through the discontinuity. The high or low impedance at the transmitter is caused by turning off the transmitter after transmitting the forward signal.

[0048] According to another embodiment of this disclosure, a computer-readable medium storing a set of instructions, which, when executed, perform a method performed by the set of instructions. The set of instructions may include: determining a forward time value by a receiver, the forward time value including the time taken for a forward signal to travel from a transmitter through a channel to the receiver; determining a reflection time value by the receiver, the reflection time value including the time taken for a reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and determining, based on the forward time value and the reflection time value, the existence of a discontinuity in the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal has been transmitted. The set of instructions may further include: determining the location of the discontinuity based on the forward time value and the reflection time value, wherein determining the location of the discontinuity includes: determining the distance in the channel from the receiver to the discontinuity. The reflected signal may include a reflected version of the forward signal, reflected from the discontinuity, traveling back to the transmitter, reflected from the transmitter due to high or low impedance, and traveling through the discontinuity to the receiver. The high or low impedance at the transmitter is caused by shutting down the transmitter after transmitting the forward signal. The set of instructions may also include: using the identified discontinuities to predict link performance on another system, or using the identified discontinuities to determine whether a lower power level can be maintained on the channel.

[0049] For example, embodiments of this disclosure can be implemented as a computer process (method), computing system, or article of manufacture, such as a computer program product or a computer-readable medium. A computer program product can be a computer storage medium readable by a computer system and encodes a computer program containing instructions for performing the computer process. A computer program product can also be a propagated signal on a carrier wave readable by a computing system and encode a computer program containing instructions for performing the computer process. Therefore, this disclosure can be embodied in hardware and / or software (including firmware, resident software, microcode, etc.). In other words, embodiments of this disclosure can take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied therein for use by or in conjunction with an instruction execution system. A computer-usable or computer-readable medium can be any medium capable of containing, storing, communicating, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0050] Computer-usable or computer-readable media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, apparatuses, or propagation media. More specific examples of computer-readable media (a non-exhaustive list) may include the following: electrical connections having one or more wires, portable computer floppy disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), fiber optics, and portable optical disc read-only memory (CD-ROM). Note that computer-usable or computer-readable media can even be paper or other suitable media for printing programs, as programs can be electronically captured via optical scanning of, for example, paper or other media, then compiled, interpreted, or processed in a suitable manner as necessary, and then stored in computer memory.

[0051] While some embodiments of this disclosure have been described, other embodiments may exist. Furthermore, although embodiments of the invention have been described in association with data stored in memory and other storage media, data may also be stored on or read from other types of computer-readable media, such as secondary storage devices (e.g., hard disks, floppy disks, or CD-ROMs), carrier waves from the Internet, or other forms of RAM or ROM. Moreover, the stages of the disclosed method may be modified in any way without departing from this disclosure, including by reordering and / or inserting or deleting stages.

[0052] Furthermore, embodiments of this disclosure can be practiced in circuits (including discrete electronic components, packaged or integrated electronic chips containing logic gates, circuits utilizing microprocessors), or on a single chip containing electronic components or a microprocessor. Embodiments of this disclosure can also be practiced using other techniques capable of performing logical operations (e.g., AND, OR, NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. Additionally, embodiments of the invention can be practiced within a general-purpose computer or in any other circuit or system.

[0053] Embodiments of this disclosure can be practiced via a system-on-a-chip (SOC), wherein Figure 1 Each or more of the elements shown can be integrated onto a single integrated circuit. Such a SoC device may include one or more processing units, graphics units, communication units, system virtualization units, and various application functions, all of which can be integrated (or “programmed”) onto a chip substrate as a single integrated circuit. When operating via the SoC, the functions described herein with respect to embodiments of this disclosure can be performed via dedicated logic integrated on a single integrated circuit (chip) along with other components of the computing device 400.

[0054] For example, embodiments of the present disclosure have been described above with reference to block diagrams and / or operational illustrations of methods, systems, and computer program products according to embodiments of the present disclosure. Functions / actions indicated in the blocks may occur in any order shown in any flowchart. For example, depending on the functions / actions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order.

[0055] Although the specification includes examples, the scope of this disclosure is indicated by the appended claims. Furthermore, although this specification has been described using language specific to structural features and / or methodological actions, the claims are not limited to the features or actions described above. Rather, the specific features and actions described above are disclosed as examples of embodiments of this disclosure.

Claims

1. A method for providing connectivity fault detection, comprising: The forward time value is determined by the receiver, and the forward time value includes the time taken for the forward signal to travel from the transmitter through the channel to the receiver; The receiver determines a reflection time value, which includes the time it takes for the reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and Based on the forward time value and the reflection time value, a discontinuity is determined to exist on the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal is transmitted, and the high or low impedance at the transmitter is caused by the transmitter being turned off after the forward signal is transmitted.

2. The method according to claim 1, wherein, Determining the existence of the discontinuity also includes determining that the amplitude of the reflected signal is greater than a predetermined value.

3. The method according to claim 1 or 2, further comprising: The location of the discontinuity is determined based on the forward time value and the reflection time value.

4. The method according to claim 3, wherein, Determining the location of the discontinuity includes determining the distance from the receiver to the discontinuity in the channel.

5. The method according to claim 1, wherein, The reflected signal is a reflected version of the forward signal, which is reflected from the discontinuity, travels back to the transmitter, is reflected from the transmitter due to the high or low impedance, and travels through the discontinuity to the receiver.

6. The method according to claim 1, further comprising: Use the identified discontinuities to predict link performance on another system.

7. The method according to claim 1, wherein, Also includes: The identified discontinuities are used to determine whether a lower power level can be sustained on the channel.

8. A system for providing connectivity fault detection, comprising: Memory; as well as A processing unit disposed in the receiver, the processing unit being coupled to the memory, wherein the processing unit is operated to: Determine the forward time value, which includes the time it takes for the forward signal to travel from the transmitter through the channel to the receiver; Determine a reflection time value, the reflection time value including the time taken for the reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and Based on the forward time value and the reflection time value, a discontinuity is determined to exist on the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal is transmitted, and the high or low impedance at the transmitter is caused by the transmitter being turned off after the forward signal is transmitted.

9. The system according to claim 8, wherein, The processing unit is operated to determine the existence of the discontinuity, which further includes: the processing unit is operated to determine that the amplitude of the reflected signal is greater than a predetermined value.

10. The system according to claim 8 or 9, further comprising: The processing unit is operated to determine the location of the discontinuity based on the forward time value and the reflection time value.

11. The system according to claim 10, wherein, The processing unit is operated to determine the location of the discontinuity by: the processing unit being operated to determine the distance in the channel from the receiver to the discontinuity.

12. The system according to claim 8, wherein, The reflected signal is a reflected version of the forward signal, which is reflected from the discontinuity, travels back to the transmitter, is reflected from the transmitter due to the high or low impedance, and travels through the discontinuity to the receiver.

13. A computer-readable medium storing a set of instructions, said set of instructions, when executed, performing a method performed by said set of instructions, said method comprising: The forward time value is determined by the receiver, and the forward time value includes the time taken for the forward signal to travel from the transmitter through the channel to the receiver; The receiver determines a reflection time value, which includes the time it takes for the reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and Based on the forward time value and the reflection time value, a discontinuity is determined to exist on the channel, wherein the reflected signal is caused by the discontinuity and a high or low impedance present at the transmitter after the forward signal is transmitted, and the high or low impedance at the transmitter is caused by the transmitter being turned off after the forward signal is transmitted.

14. The computer-readable medium of claim 13, further comprising: The location of the discontinuity is determined based on the forward time value and the reflection time value, wherein determining the location of the discontinuity includes determining the distance from the receiver to the discontinuity in the channel.

15. The computer-readable medium according to claim 13 or 14, wherein, The reflected signal is a reflected version of the forward signal, which is reflected from the discontinuity, travels back to the transmitter, is reflected from the transmitter due to the high or low impedance, and travels through the discontinuity to the receiver.

16. The computer-readable medium of claim 13, further comprising: Use the identified discontinuities to predict link performance on another system.

17. The computer-readable medium of claim 13, further comprising: The identified discontinuities are used to determine whether a lower power level can be sustained on the channel.

18. An apparatus for providing connectivity fault detection, comprising: A module for determining a forward time value by a receiver, the forward time value including the time taken for a forward signal to travel from the transmitter through the channel to the receiver; A module for determining a reflection time value by the receiver, the reflection time value including the time taken for the reflected signal to travel to the receiver, wherein the reflected signal is associated with the forward signal; and A module for determining the existence of discontinuities on the channel based on the forward time value and the reflection time value, wherein the reflected signal is caused by the discontinuity and by a high or low impedance present at the transmitter after the forward signal is transmitted, and the high or low impedance at the transmitter is caused by shutting down the transmitter after the forward signal is transmitted.

19. The apparatus of claim 18, further comprising: Apparatus for implementing the method according to any one of claims 2 to 7.

20. A computer program product comprising instructions that, when executed by a computer, cause the computer to perform the steps of the method according to any one of claims 1 to 7.

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