Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display area of the display panel comprises a main display area and a sub-display area; the driving back plate of the display panel comprises a substrate, a plurality of pixel circuits, a first power supply bus connected with a second electrode, and a first electrode connected with a pixel circuit. The driving back plate comprises a substrate and a plurality of circuit units, the circuit unit comprises two pixel circuits distributed along a row direction, the light-emitting device comprises a first electrode, a light-emitting layer and a second electrode, the first electrode is connected with the pixel circuit; the line group comprises two data lines distributed along the row direction; the two data lines of one line group are connected with two columns of pixel circuits of one column of circuit units respectively; each data line comprises a plurality of first data lines and second data lines; the first data line extends from the main display area to a lead-out area; the second data line is located in the sub-display area; the power supply line extends from the display area to the lead-out area along a column direction; two columns of pixel circuits of one column of circuit units are connected with one power supply line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels have advantages such as self-illumination, wide color gamut, high contrast, flexibility, and high response, and have broad application prospects. However, current display panels consume a relatively large amount of power.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a display panel and a display device.

[0005] According to one aspect of this disclosure, a display panel is provided, including a display area and a peripheral area outside the display area, the peripheral area including a lead-out area extending in a direction away from the display area, the lead-out area having a binding portion, the display area and the lead-out area being distributed along a column direction; the display area including a main display area and sub-display areas disposed on both sides of the main display area along a row direction;

[0006] The display panel includes a driving backplate and a plurality of light-emitting devices disposed on one side of the driving backplate. The driving backplate includes a substrate and a plurality of circuit units located on one side of the substrate. Each circuit unit includes two pixel circuits distributed along the row direction, and the two pixel circuits of the same circuit unit are symmetrically arranged.

[0007] The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked in a direction away from the driving backplate, wherein the first electrode is connected to a pixel circuit.

[0008] The drive backplate includes:

[0009] A first power bus is located in the peripheral area and connected to the second electrode;

[0010] Multiple data lines extend along the column direction and are divided into multiple line groups distributed along the row direction. Each line group includes two data lines distributed along the row direction. The two data lines of one line group are respectively connected to two columns of pixel circuits of one column of circuit units. Each data line includes multiple first data lines and second data lines. The first data lines extend from the main display area to the lead-out area and are connected to the binding part. The second data lines are located in the sub-display area.

[0011] Multiple power lines extend from the display area to the lead-out area along the column direction; two columns of pixel circuits of one column of the circuit unit are connected to one of the power lines;

[0012] Multiple first connecting lines extend along the row direction, and at least some of the first connecting lines include first adapter lines and first dummy lines spaced apart; the first adapter lines extend from the sub-display area to the main display area.

[0013] Multiple second connecting lines extend along the column direction, one second connecting line is located between two adjacent line groups, and the data lines of the two adjacent line groups are symmetrically arranged with respect to the second connecting line between the two line groups; at least a portion of the second connecting lines include second adapter lines and second dummy lines arranged at intervals; the second adapter lines extend from the main display area to the lead-out area and are connected to the binding part;

[0014] A first adapter cable and a second adapter cable are connected to form an adapter cable; a second data cable is connected to the bonding part through at least one of the adapter cables;

[0015] The first connecting line is insulated from the data line; at least a portion of the first dummy line and at least a portion of the second dummy line are connected, and are connected to the first power bus.

[0016] In one exemplary embodiment of this disclosure, the first adapter line and the first dummy line are disposed on the same layer on the side of the power line closer to the substrate; the second adapter line and the second dummy line are disposed on the same layer on the side of the first connecting line away from the substrate.

[0017] In the same first connecting line, adjacent first adapter wires and first dummy wires are separated by a break; in the same second connecting line, adjacent second adapter wires and second dummy wires are separated by a break.

[0018] At least a portion of the break in the first connecting line overlaps with the second connecting line or the power line.

[0019] In one exemplary embodiment of this disclosure, the first connection line is located on the side of the data line closer to the substrate.

[0020] In one exemplary embodiment of this disclosure, at least a portion of the fracture overlaps with a portion of the first electrode.

[0021] In one exemplary embodiment of this disclosure, the display panel further includes:

[0022] A touch layer is disposed on the side of the light-emitting device away from the substrate, and includes a touch electrode layer, wherein the touch electrode layer is a mesh structure surrounded by multiple channel lines, and at least part of the break overlaps with part of the channel lines.

[0023] In one exemplary embodiment of this disclosure, the break in the first connecting wire is a first break, and the break in the second connecting wire is a second break.

[0024] A portion of the first break overlaps with the second connecting line, and another portion of the first break overlaps with the power line;

[0025] The second break overlaps with the first electrode or the channel line.

[0026] In one exemplary embodiment of this disclosure, a portion of the first adapter wire extends continuously along the row direction to the peripheral area, and a portion of the second adapter wire extends continuously along the column direction to the lead-out area.

[0027] In one exemplary embodiment of this disclosure, the second connecting line is disposed on the same layer as the data line and the power line, and is located on the side of the first connecting line away from the substrate;

[0028] The drive backplane also includes an array of first adapters and an array of second adapters, wherein the first adapter, the second adapter, and the first connecting line are arranged on the same layer.

[0029] A column of first adapter sections overlaps with a data line, and the data line is connected to each pixel circuit in a column of pixel circuits through each of the overlapping first adapter sections; a first adapter line is connected to a second data line through a first adapter section;

[0030] A second adapter section overlaps with a second connecting line, and a second adapter line is connected to a first adapter line through a second adapter section.

[0031] In one exemplary embodiment of this disclosure, at least a portion of the second dummy line is connected to at least a portion of the first dummy line via at least a portion of the second adapter.

[0032] In one exemplary embodiment of this disclosure, the first adapter is connected to the data cable via a first contact hole; the second adapter is connected to the second connecting cable via a second contact hole.

[0033] Each of the first contact holes and the second contact holes can be divided into multiple arrayed hole groups, and a column of the hole groups is located between the power lines connected to two adjacent circuit units;

[0034] One of the hole groups includes two first contact holes and one second contact hole, with the two first contact holes symmetrically arranged about the second contact hole.

[0035] In one exemplary embodiment of this disclosure, the two first contact holes and one second contact hole of the same hole group are arranged in a triangular pattern.

[0036] In one exemplary embodiment of this disclosure, the driving backplane further includes an array of first electrode adapters and an array of second electrode adapters. The first electrode adapters are disposed on the same layer as the first and second adapters. The second electrode adapters are located on the side of the first electrode adapters away from the substrate, and one first electrode adapter and one second electrode adapter overlap and are connected through a third contact hole. The first electrode is connected to the pixel circuit through the second electrode adapter, the third contact hole, and the first electrode adapter. The hole group further includes the third contact hole.

[0037] In the same group of holes, the first contact hole is connected to the (n+1)th row pixel circuit, and the third contact hole is connected to the nth row pixel circuit; the two third contact holes are located on both sides of the second contact hole and are distributed along the column direction.

[0038] In one exemplary embodiment of this disclosure, the pixel circuit includes a driving transistor, a writing transistor, a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor; the driving backplane also includes a first reset control line, a first reset signal line, a second reset control line, a second reset signal line, a third reset signal line, a first scan line, a second scan line, and a light-emitting control line;

[0039] The gate of the driving transistor is connected to the first node, the first electrode is connected to a power line through the first light-emitting control transistor, and the second electrode is connected to the first electrode of the light-emitting device through the second light-emitting control transistor; the gates of the first light-emitting control transistor and the second light-emitting control transistor are connected to the light-emitting control line.

[0040] The gate of the first reset transistor is connected to the first reset control line, the first terminal is connected to the first reset signal line, and the second terminal is connected to the first node;

[0041] The gate of the write transistor is connected to the first scan line, the first electrode is connected to a data line, and the second electrode is connected to the first electrode of the drive transistor.

[0042] The gate of the compensation transistor is connected to the second scan line, the first terminal is connected to the second terminal of the driving transistor, and the second terminal is connected to the first node;

[0043] The gate of the two reset transistors is connected to the second reset control line, the first electrode is connected to the second reset signal line, and the second electrode is connected to the first electrode.

[0044] The gate of the third reset transistor is connected to the second reset control line, the first terminal is connected to the third reset signal line, and the second terminal is connected to the first terminal of the driving transistor.

[0045] The first plate of the storage capacitor is connected to the power line, and the second plate is connected to the first node.

[0046] The first reset transistor and the compensation transistor are metal-oxide transistors; the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor are polysilicon transistors.

[0047] In one exemplary embodiment of this disclosure, the drive backplane further includes:

[0048] A first semiconductor layer is disposed on one side of the substrate and includes the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light-emitting control transistor, and the channel of the second light-emitting control transistor.

[0049] A first gate insulating layer covers the first semiconductor layer;

[0050] A first gate layer is disposed on the surface of the first gate insulating layer away from the substrate and overlaps with at least a portion of the first semiconductor layer. The first gate layer includes a second reset control line, the light emission control line, the first scan line, and the first electrode plate.

[0051] A first insulating layer covers the first gate layer;

[0052] The second gate layer is disposed on the surface of the first insulating layer away from the substrate, and includes a second electrode plate overlapping the first electrode plate;

[0053] A second insulating layer covers the second gate layer;

[0054] A second semiconductor layer is disposed on the surface of the second insulating layer away from the substrate, and includes the channel of the first reset transistor and the compensation transistor;

[0055] A second gate insulating layer covers the second semiconductor layer;

[0056] A third gate layer is disposed on the surface of the third gate insulating layer away from the substrate and overlaps with at least a portion of the second semiconductor layer. The third gate layer includes the first reset control line, the first reset signal line, the second scan line, and at least a portion of the third reset signal line.

[0057] A third insulating layer covers the third gate layer;

[0058] A first source / drain layer is disposed on the surface of the third insulating layer away from the substrate, and includes the second reset signal line and at least a portion of the third reset signal line;

[0059] A first planarization layer is disposed on the side of the first source / drain layer away from the substrate;

[0060] The second source / drain layer is disposed on the surface of the first planarization layer away from the substrate, and includes the first connection line;

[0061] A second planarization layer covers the second source / drain layer;

[0062] The third source / drain layer is disposed on the surface of the second planarization layer away from the substrate, and includes the data line, power line, and second connection line;

[0063] A third planarization layer covers the third source / drain layer; the first electrode is disposed on the surface of the third planarization layer away from the substrate.

[0064] In one exemplary embodiment of this disclosure, the second semiconductor layer includes an active oxide portion extending along the column direction, the active oxide portion being located between the first reset signal line and the third reset signal line; the first reset control line overlaps with the active oxide portion to form the first reset transistor, and the second reset control line overlaps with the active oxide portion to form the compensation transistor;

[0065] The first source / drain layer includes a first connection portion, one end of which is connected to the first electrode plate, and the other end of which is connected to the oxide active portion between the channel of the first reset transistor and the second reset control line.

[0066] The driving backplane also includes a plurality of shielding portions located in the second source-drain layer; one of the shielding portions overlaps with a first connection portion of the pixel circuit and the channel of the compensation transistor, and is connected to a power line connected to the pixel circuit.

[0067] In one exemplary embodiment of this disclosure, in a circuit unit where the shielding portion and the first connecting portion overlapping therewith are located, both second electrode plates of the pixel circuit of the circuit unit overlap and are connected to the shielding portion.

[0068] In one exemplary embodiment of this disclosure, the first source / drain layer includes a second connection portion and a third connection portion, wherein the second connection portion connects two second electrode plates; and the third connection portion connects one second electrode plate and the first electrode of the first light-emitting control transistor.

[0069] In one exemplary embodiment of this disclosure, in a circuit unit where the shielding portion and the first connecting portion overlapping therewith are located, the two data lines connected to the circuit unit are located on both sides of the shielding portion, and the power line connected to the circuit unit is located between the two data lines, and overlaps with and is connected to the shielding portion.

[0070] In one exemplary embodiment of this disclosure, in a power line and a circuit unit connected thereto, the power line has protrusions that bulge outwards in both directions along the row direction, and the two protrusions overlap with the channels of the first reset transistors of the two pixel circuits, respectively.

[0071] In one exemplary embodiment of this disclosure, the first reset control line, the first reset signal line, the second reset control line, the second reset signal line, the third reset signal line, the first scan line, the second scan line, and the light emission control line connecting the pixel circuits in the same row all extend along the row direction and are distributed along the column direction;

[0072] The first reset control line, the first scan line, the second scan line, the third reset signal line, the light emission control line, and the second reset control line are located between the first reset signal line and the second reset signal line; the first scan line, the second scan line, at least a portion of the third reset signal line, and the light emission control line are located between the first reset control line and the second reset control line; the second scan line is located between the first scan line and the light emission control line; the second electrode is located between the second scan line and at least a portion of the third reset signal line; the light emission control line overlaps with at least a portion of the third reset signal line.

[0073] The first reset signal line connecting the pixel circuit in row (n+1) overlaps with the second reset control line connecting the pixel circuit in row (n).

[0074] In one exemplary embodiment of this disclosure, the second reset signal line connecting the pixel circuit in the (n+1)th row overlaps with both the first reset control line and the first scan line connecting the pixel circuit in the nth row.

[0075] In one exemplary embodiment of this disclosure, the third reset signal line includes a line body extending along the row direction and a line branch connected to the side of the line body near the second reset signal line, the line body and the line branch being located in different layers; the line body is located between the second scan line and the second reset control line, and overlaps with the light emission control line; the line branch extends between the second reset control line and the second reset signal line, and is connected to the first electrode of the third reset transistor.

[0076] In one exemplary embodiment of this disclosure, the line body is located in the third gate layer, and the line branch is located in the first source / drain layer.

[0077] In one exemplary embodiment of this disclosure, a first reset signal line overlaps with a first connection line.

[0078] In one exemplary embodiment of this disclosure, the oxide active portion has a capacitor portion extending along the row direction, and the capacitor portion is connected between the channels of the first reset transistor and the compensation transistor; the capacitor portion overlaps with the first scan line and is connected to the first connection portion.

[0079] In one exemplary embodiment of this disclosure, the second gate layer further includes an auxiliary control line and an auxiliary scan line extending along the row direction, wherein the auxiliary control line overlaps with and is connected to the first reset control line, and the auxiliary scan line overlaps with and is connected to the second scan line.

[0080] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0081] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0082] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0083] Figure 1 This is a top view of one embodiment of the display panel of this disclosure.

[0084] Figure 2 This is a data line distribution diagram of one embodiment of the display panel of this disclosure.

[0085] Figure 3This is a cross-sectional schematic diagram of one embodiment of the display panel of this disclosure.

[0086] Figure 4 This is a schematic diagram of the pixel circuit in one embodiment of the display panel of this disclosure.

[0087] Figure 5 This is a top view of a circuit unit in one embodiment of the display panel of this disclosure.

[0088] Figure 6 for Figure 5 A schematic diagram of the first semiconductor layer and the first gate layer.

[0089] Figure 7 for Figure 5 A schematic diagram of the first semiconductor layer to the second gate layer.

[0090] Figure 8 for Figure 5 A schematic diagram of the first semiconductor layer to the oxide semiconductor layer.

[0091] Figure 9 for Figure 5 A schematic diagram of the first semiconductor layer to the third gate layer.

[0092] Figure 10 for Figure 5 A schematic diagram of the first semiconductor layer to the first source / drain layer.

[0093] Figure 11 for Figure 5 A schematic diagram of the first semiconductor layer to the second source / drain layer.

[0094] Figures 12-20 These are partial schematic diagrams of a portion of the film layer of the driving backplate in one embodiment of the display panel of this disclosure.

[0095] Figure 21 This is a partial top view of the second and third source / drain layers in one embodiment of the display panel of this disclosure.

[0096] Figure 22 This is a partial top view of the second source / drain layer in one embodiment of the display panel of this disclosure.

[0097] Figure 23 This is a partial top view of the third source / drain layer in one embodiment of the display panel of this disclosure.

[0098] Figure 24 This is a partial top view of the shielding layer of another embodiment of the display panel disclosed herein.

[0099] Figure 25 This is a partial top view of the third source / drain layer and the first electrode in one embodiment of the display panel of this disclosure.

[0100] Figure 26 This is a partial top view of the third source / drain layer and the touch electrode layer in one embodiment of the display panel of this disclosure.

[0101] Figure 27 This is a partial top view of a series of circuit units in one embodiment of the display panel of this disclosure. Detailed Implementation

[0102] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0103] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0104] In this document, the row direction X and column direction Y are only two mutually perpendicular directions. In the accompanying drawings of this disclosure, the row direction X can be horizontal and the column direction Y can be vertical, but are not limited to this. If the display panel is rotated, the actual orientation of the row direction X and column direction Y may change.

[0105] In this paper, the "overlap" of features A and B means that the orthographic projections of features A and B on the substrate at least partially coincide.

[0106] In this paper, "same layer" for features A and B means that features A and B can be formed simultaneously, and they are discontinuous or continuous different regions in the same film layer, and they are not separated by other film layers in the direction perpendicular to the substrate. "Different layers" means that features A and B are distributed at intervals along the direction perpendicular to the substrate, and they are separated by other film layers.

[0107] In this article, "adjacent" A features refer to two A features that do not have any other A features between them.

[0108] This disclosure provides a display panel, such as... Figure 1 and Figure 2As shown, the display panel may have a display area AA and an outer peripheral area WA located outside the display area AA. The outer peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA. The shape of the outer peripheral area WA is not specifically limited here.

[0109] The peripheral area WA may include a lead-out area FA extending in a direction away from the display area AA. The display area AA and the lead-out area FA may be distributed along the column direction Y. The lead-out area FA has a bonding portion PA, which may have multiple pads. Each pad can be bonded to a flexible circuit board, thereby controlling the display area AA of the display panel to emit light through a control circuit board bonded to the flexible circuit board to display an image.

[0110] The display area AA may include a main display area MA and two secondary display areas SA located on either side of the main display area MA along the row direction X. That is, there are two secondary display areas SA, separated by the display area MA. For example, the display area AA may be quadrilateral in shape, with rounded corners. The width of the secondary display area SA in the row direction X is not greater than the width of the rounded corners in the row direction X.

[0111] like Figure 3 As shown, the display panel may include a driving backplane BP and multiple light-emitting devices (LDs). The driving backplane BP has a driving circuit. Each light-emitting device (LD) may be located on one side of the driving backplane BP and within the display area AA. Both the main display area MA and the sub-display area SA are equipped with light-emitting devices (LDs), and each light-emitting device (LD) may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked along a direction away from the driving backplane BP. The light-emitting device (LD) may be an OLED (Organic Light-Emitting Diode), or of course, a MicroLED (Micron Light-Emitting Diode), a Mini LED (Submillimeter Light-Emitting Diode), or a QLED (Quantum Dot Diode), etc.

[0112] like Figure 3 As shown, the first electrode ANO can be disposed on one side of the driving backplane BP. The light-emitting layer EL can include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked along a direction away from the driving backplane BP. Each light-emitting device LD can share a second electrode CAT. That is, the second electrode CAT can be a continuous solid layer structure, and the second electrode CAT can extend to the peripheral area and receive the first power signal VSS. The first electrodes ANO are arrayed to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light emission range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL can be disposed on the surface where the first electrode ANO is disposed. It can have openings that expose each first electrode ANO, and the light-emitting layer EL is stacked with the first electrode ANO within the openings.

[0113] Each light-emitting device (LD) can share at least one light-emitting material layer, ensuring that all LDs emit the same color. In this case, to achieve color display, a color filter layer can be placed on the side of the LD away from the substrate (SU). Color display is achieved through the filter portion in the color filter layer corresponding to each LD. Alternatively, each LD can have an independent light-emitting material layer, allowing the LD to directly emit monochromatic light, and different LDs can emit different colors, thus achieving color display.

[0114] In addition, such as Figure 3 As shown, the display panel may further include a TFE encapsulation layer covering each light-emitting device (LD). This TFE may be a thin-film encapsulation layer and may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers each light-emitting device, specifically the surface of the second electrode (CAT) away from the substrate (SU). The material of the first inorganic layer may include inorganic insulating materials such as silicon nitride or silicon oxide. The organic layer may be disposed on the surface of the first inorganic layer away from the substrate (SU), and its boundary may be defined within the boundary of the first inorganic layer by a barrier dam located in the peripheral region (WA). The material of the organic layer may be an organic material such as resin.

[0115] The second inorganic layer can cover both the organic layer and the first inorganic layer that is not covered by the organic layer. The second inorganic layer can block the intrusion of water and oxygen, while the organic layer, which has fluidity (during the manufacturing process), can achieve planarization. The material of the second inorganic layer can include inorganic insulating materials such as silicon nitride and silicon oxide.

[0116] In addition, such as Figure 3 As shown, the display panel may also include other film layers such as a touch layer TSP and a transparent cover plate disposed on the side of the encapsulation layer TFE away from the substrate SU, which will not be described in detail here.

[0117] Taking a mutual capacitance touch structure as an example, the touch layer TPS may include multiple first touch electrodes Tx and multiple second touch electrodes Rx. Each first touch electrode Tx may be spaced apart along the row direction X. Each first touch electrode Tx may include multiple first electrode blocks Txc spaced apart along the column direction Y and a transition bridge BR connecting two adjacent first electrode blocks Txc. Each second touch electrode Rx may be spaced apart along the column direction Y. Each second touch electrode Rx includes multiple second electrode blocks Rxc connected in series along the row direction X. A transition bridge BR intersects with a second touch electrode Rx and is insulated from it. One of the first touch electrode Tx and the second touch electrode Rx may serve as a transmitting electrode and the other as a receiving electrode, and both are connected to the peripheral touch driving circuit.

[0118] Furthermore, the touch layer may include a barrier layer (TLD), a bridging layer, an isolation layer (SEP), a touch electrode layer (TMB), and a protective layer (TOC), wherein:

[0119] The barrier layer TLD can be disposed on the surface of the encapsulation layer TFE away from the driving backplane BP. Its material can be insulating materials such as silicon nitride or silicon oxide, without special limitation. The transition layer can be disposed on the surface of the barrier layer TLD away from the driving backplane BP, and includes multiple arrayed transition bridges BR. The bridging layer can be made of metal or other conductive materials, and includes each transition bridge BR. The isolation layer SEP can cover the bridging layer, and the material of the isolation layer SEP can be insulating materials such as silicon nitride or silicon oxide, without special limitation. The touch electrode layer TMB can be disposed on the surface of the isolation layer SEP away from the driving backplane BP, and includes the aforementioned first electrode block Txc and second touch electrode Rx.

[0120] Furthermore, such as Figure 25 As shown, the touch electrode layer TMB of the touch layer TSP can adopt a mesh structure with multiple mesh holes to improve light transmittance. Each mesh hole is surrounded by multiple channel lines TL, and one mesh hole can correspond to one or more light-emitting devices LD. That is, the orthogonal projection of the mesh hole on the substrate SU can have the orthogonal projection of one or more light-emitting devices LD on the substrate SU, so as to prevent the channel lines TL from blocking the light-emitting devices LD.

[0121] like Figure 3 As shown, it can be connected to a light-emitting device (LD), thereby driving each LD to emit light independently. Specifically, the driving backplate BP may include a substrate SU and a driving circuit located on one side of the substrate SU. The driving circuit may include multiple pixel circuits PC and peripheral circuits. Each pixel circuit PC may be located within the display area AA and connected to the first electrode ANO of the light-emitting device LD. Of course, a portion of a portion of the pixel circuit PC may be located in the peripheral area WA.

[0122] like Figure 2 As shown, the peripheral circuit is located within the peripheral area WA, and may include a first power bus VSL and a second power bus BVDL. The second power bus BVDL can be connected to the first electrode ANO of the light-emitting device LD via the pixel circuit PC, applying a second power signal VDD to the pixel circuit PC. The first power bus VSL can be connected to the second electrode CAT of the light-emitting device LD, applying a first power signal VSS to the second electrode CAT. By controlling the pixel circuit PC, the current through the light-emitting device LD can be controlled, thereby controlling the brightness of the light-emitting device LD. The peripheral circuit may include a gate driving circuit and a light-emitting control circuit, etc., and may also include other circuits. No specific limitations are made on the specific structure of the peripheral circuit here.

[0123] Each pixel circuit PC may include multiple transistors and capacitors. The channels of each transistor can be arranged on the same layer and are all made of semiconductor materials such as polysilicon. It can be a 3T1C, 7T1C, 8T1C, etc. pixel circuit. nTmC indicates that one pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). There can be multiple pixel circuit PCs, and they can be arranged in multiple rows and columns. One pixel circuit PC can be connected to one light-emitting device (LD). Of course, it is also possible for one pixel circuit PC to be connected to multiple light-emitting devices (LDs). This article only illustrates the example of a one-to-one connection between pixel circuit PCs and light-emitting devices (LDs).

[0124] The following explanation uses an 8T1C pixel circuit as an example:

[0125] like Figures 4-11 As shown, the transistors in the pixel circuit PC may include a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst. Each transistor includes a gate, a first electrode, and a second electrode. By applying a control signal to the gate, the first and second electrodes can be turned on or off. The storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0126] like Figure 4 As shown, the gate of the first light-emitting control transistor T5 is used to input the light-emitting control signal EM, its first electrode is used to input the second power supply signal VDD, and its second electrode is connected to the first electrode of the driving transistor T3. The gate of the driving transistor T3 is connected to the first node N1, and its second electrode is connected to the first electrode of the second light-emitting control transistor T6 at the second node N2. The second electrode of the second light-emitting control transistor T6 is connected to the first electrode ANO of a light-emitting device LD, and its gate is used to input the light-emitting control signal EM.

[0127] The gate of the first reset transistor T1 is used to input the first reset control signal RE1, the first terminal is used to input the first reset signal VI1, and the second terminal is connected to the first node N1.

[0128] The gate of the write transistor T4 is used to input the first scan signal Gate1, the first terminal is used to input the data signal DA, and the second terminal is connected to the third node N3 along with the first terminal of the drive transistor T3 and the second terminal of the first light-emitting control transistor T5.

[0129] The gate of the compensation transistor T2 is used to input the second scan signal Gate2. The first terminal is connected to the second node N2, and the second terminal is connected to the first node N1.

[0130] The gate of the second reset transistor T7 is used to input the second reset control signal RE2, the first electrode is used to input the second reset signal VI2, and the second electrode, along with the second electrode and the first electrode ANO of the second light-emitting control transistor T6, are connected to the fourth node N4.

[0131] The gate of the third reset transistor T8 is used to input the second reset control signal RE2, the first terminal is used to input the third reset signal VI3, and the second terminal is connected to the third node N3.

[0132] The first plate Cst1 of the storage capacitor Cst is used to input the second power supply signal VDD, and the second plate Cst2 is connected to the first node N1.

[0133] The working principle of the pixel circuit described above is explained below:

[0134] During the reset phase t1: the first reset control signal RE1 turns on the first reset transistor T1, writing the first reset signal VI1 to the first node N1. Simultaneously, the second reset control signal RE2 turns on the second reset transistor T7 and the third reset transistor T8, writing the second reset signal VI2 to the fourth node N4 and the third reset signal VI3 to the third node N3. This resets the gate, first electrode, and first electrode ANO of the driving transistor T3.

[0135] During the write phase t2: the write transistor T4 and the compensation transistor T2 are turned on by the first scan signal Gate1 and the second scan signal Gate2. Data signal DA is written to the first node N1 through the third node N3 and the second node N2 until the potential reaches Vdata + vth, where Vdata is the voltage of data signal DA and Vth is the threshold voltage of the driving transistor T3. The first scan signal Gate1 and the second scan signal Gate2 can be the same signal or two synchronized signals. Furthermore, the first scan signal Gate1 and the second scan signal Gate2 can be high-frequency signals, which helps to reduce the load on the source signal of the driving transistor T3.

[0136] During the light-emitting stage t3: the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on by the light-emitting control signal EM. Drive transistor T3 is then turned on under the influence of the voltage Vdata+Vth stored in the storage capacitor Cst and the second power supply signal VDD. Under the influence of the second power supply signal VDD and the first power supply signal VSS, the light-emitting device LD emits light. In this process, the first terminal of drive transistor T3 acts as the source, and the second terminal acts as the drain.

[0137] The output current of driving transistor T3 satisfies the following formula:

[0138] I = (μWCox / 2L)(Vgs-Vth) 2

[0139] Where I is the output current of driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the channel width of driving transistor T3; L is the channel length of driving transistor T3; Vgs is the gate-source voltage difference of driving transistor T3 (the voltage difference between the gate and the source); and Vth is the threshold voltage of driving transistor T3.

[0140] Based on the formula for the output current of the driving transistor T3, substituting the gate voltage Vdata+Vth and source voltage VDD of the driving transistor T3 in the pixel circuit of this disclosure into the formula, we can obtain: the output current of the driving transistor T3 I=(μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of this pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, but only related to Vdata. This eliminates the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled solely by the voltage Vdata of the data signal DA, so as to control the brightness of the light-emitting device LD.

[0141] It should be noted that the third reset transistor T8 and the first reset transistor T1 can be turned on and off synchronously. That is, the third reset signal VI3 and the first reset signal VI1 can be input synchronously. Therefore, during the reset phase t1, the gate and first terminal of the driving transistor T3 can be reset using the first reset signal VI1 and the third reset signal VI3, i.e., the gate-source voltage difference of the driving transistor T3 can be reset. This helps reduce the impact of the hysteresis effect of the driving transistor T3 on its current, thereby improving the image retention phenomenon. Of course, the third reset signal VI3 and the first reset signal VI1 can also be input asynchronously, but the reset should be completed before the write phase t2.

[0142] Each transistor in the aforementioned pixel circuit can be a polysilicon transistor, meaning the transistor channel is polysilicon, such as a P-type or N-type low-temperature polysilicon transistor. Alternatively, a metal-oxide-semiconductor (MOD) transistor can be used, meaning the transistor channel is made of metal oxides such as indium gallium zinc oxide (IGNOS). Specifically, the P-type MOD transistor is turned off when a high-level signal is input to its gate and turned on when a low-level signal is input; the N-type MOD transistor is turned off when a low-level signal is input to its gate and turned on when a high-level signal is input. The MOD transistor can be an N-type MOD transistor, which can turn on when a high-level signal is input to its gate and turn off when a low-level signal is input.

[0143] In some embodiments of this disclosure, the pixel circuit of the aforementioned 8T1C can employ LTPO (LTPS+Oxide) technology. Specifically, the driving transistor T3, writing transistor T4, second reset transistor T7, third reset transistor T8, first light-emitting control transistor T5, and second light-emitting control transistor T6 can be P-type low-temperature polysilicon transistors; the first reset transistor T1 and compensation transistor T2 can be N-type metal-oxide transistors. Since P-type low-temperature polysilicon transistors have higher carrier mobility, this is beneficial for achieving high-resolution, high-response-speed, high-pixel-density, and high-aperture-ratio display panels, thereby obtaining higher carrier mobility and improving response speed. Simultaneously, N-type metal-oxide transistors can reduce leakage current.

[0144] All the signals input to the pixel circuit described above can be transmitted via traces. The traces for transmitting each of these signals are explained below:

[0145] like Figures 5-11 As shown, the driving backplane BP may include multiple travel lines that extend at least partially along the row direction X. Any travel line may be connected to a row pixel circuit. These travel lines may include a first reset control line REL1, a first reset signal line VIL1, a second reset control line REL2, a second reset signal line VIL2, a third reset signal line VIL3, a first scan line GAL1, a second scan line GAL2, and a light emission control line EML, wherein:

[0146] For a pixel circuit PC:

[0147] The first reset control line REL1 can be connected to the gate of the first reset transistor T1 to transmit the first reset control signal RE1. The first reset signal line VIL1 can be connected to the first terminal of the first reset transistor T1 to transmit the first reset signal VI1.

[0148] The second reset control line REL2 can be connected to the gate of the second reset transistor T7 and the gate of the third reset transistor T8, and is used to transmit the second reset control signal RE2. The second reset signal line VIL2 is connected to the first terminal of the second reset transistor T7, and is used to transmit the second reset signal VI2. The third reset signal line VIL3 can be connected to the first terminal of the third reset transistor T8, and is used to transmit the third reset signal VI3.

[0149] The first scan line GAL1 can be connected to the gate of the write transistor T4 to transmit the first scan signal Gate1. The second scan line GAL2 can be connected to the gate of the compensation transistor T2 to transmit the second scan signal Gate2.

[0150] The light-emitting control line EML can be connected to the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 to transmit light-emitting control signals.

[0151] In addition to the aforementioned routing lines, the drive backplane BP also includes column routing lines extending along the column direction Y, including a data line DAL and a power line VDL. The data line DAL is connected to the first terminal of the write transistor T4 of each pixel circuit in a column of pixel circuits, used to transmit the data signal DA. The power line VDL can be connected to the second electrode Cst2 of each pixel circuit in a column of pixel circuits and the first terminal of the first light-emitting control transistor T5, used to transmit the second power signal VDD.

[0152] like Figure 5 As shown, in some embodiments of this disclosure, the pixel circuits PCs driving the backplane BP can be divided to obtain multiple circuit units CUs distributed in an array, and one circuit unit CU may include two adjacent pixel circuit PCs distributed along the row direction X. Correspondingly, a column of circuit units CU may include two adjacent columns of pixel circuit PCs distributed along the row direction X. Simultaneously, the two pixel circuit PCs of the same circuit unit CU are symmetrically arranged, that is, the two pixel circuit PCs of the same circuit unit CU are mirror images of each other about a straight line extending along the column direction Y. Correspondingly, the data line DAL and power line VDL connected to the two columns of pixel circuit PCs of a column of circuit units CU are also symmetrically arranged. Furthermore, two adjacent circuit units CUs in the row direction X can be symmetrically arranged about a straight line extending along the column direction Y, that is, the pixel circuits of the two circuit units CU are symmetrically arranged about this straight line.

[0153] It should be noted that "symmetrical arrangement" of two pixel circuits can refer to the patterns of all film layers in the driving backplane (BP) of the two pixel circuits being symmetrical about a straight line; it can also refer to the patterns of some film layers in the driving backplane of the two pixel circuits, including semiconductor layers (e.g., the first semiconductor layer POL and the second semiconductor layer IGL), being symmetrical about a straight line; or it can refer to the patterns of each film layer in the driving backplane of the two pixel circuits being symmetrical overall, but with some local patterns of some film layers exhibiting local asymmetry due to process or space limitations. Similarly, "symmetrical arrangement" of two data lines (DAL) and two power lines (VDL) is not limited to the patterns of the two data lines (DAL) or power lines (VDL) being completely symmetrical; it can also refer to the patterns of each film layer in the driving backplane of the two data lines (DAL) or power lines (VDL) being symmetrical overall, but with local asymmetry due to process or space limitations.

[0154] like Figure 5As shown, in some embodiments, the power line VDL connected to a column of circuit units CU is located between two data lines DAL, and the two power lines VDL can be a single structure. Alternatively, it can be considered that the two columns of pixel circuits PC of a column of circuit units CU share the same power line VDL. Further, the data lines DAL can be divided into multiple line groups DU distributed along the row direction X. Each line group DU includes two data lines DAL distributed along the row direction X, and the two data lines DAL of one line group DU are respectively connected to the two columns of pixel circuits PC of a column of circuit units CU. Each transistor and capacitor of a column of circuit units CU can be located between the two data lines DAL to which it is connected.

[0155] In addition, such as Figure 2 As shown, the second electrode CAT of each light-emitting device (LD) can be connected to the first power bus VSL within the peripheral area WA. The first power bus VSL can be connected to the bonding part PA, thereby inputting a first power signal VSS to the second electrode CAT of the light-emitting device LD through the first power bus VSL. Simultaneously, the power line VDL can be connected to the second power bus BVDL of the peripheral area WA. The second power bus BVDL can be connected to the bonding part PA, so that a second power signal VDD can be input to each power line VDL through the second power bus BVDL.

[0156] Each data line DAL can be connected to the bonding unit PA to input data signals DA to each data line DAL. The data line DAL located in the main display area MA can be defined as the first data line DAL1, which extends from the main display area MA to the lead-out area FA and connects to the bonding unit PA. The portion extending into the lead-out area FA can form a certain angle with the portion in the main display area MA to converge towards the bonding unit PA. Simultaneously, the data line DAL located in the sub-display area SA can be defined as the second data line DAL2, which can directly extend into the lead-out area FA and connect to the bonding unit PA. However, because the second data line DAL2 requires sufficient width in the corner area of ​​the peripheral area WA when extending to the lead-out area FA, the width of the peripheral area WA in that area is relatively large, which is not conducive to reducing the size of the peripheral area WA.

[0157] like Figure 2As shown, to reduce the width of the outer area WA, an adapter cable CL can be used to connect the second data line DAL2 to the bonding part PA. The adapter cable CL can extend from the sub-display area SA to the main display area MA, and then from the main display area MA to the lead-out area FA, and connect to the bonding part PA, thereby avoiding the second data line DAL2 extending directly to the lead-out area FA. A second data line DAL2 can be connected to the bonding part PA through at least one adapter cable CL. The adapter cable CL can include a first adapter cable CL1 and a second adapter cable CL2. The first adapter cable CL1 can extend along the row direction X from the sub-display area SA to the main display area MA, and the first adapter cable CL1 can be connected to a second data line DAL2. The second adapter cable CL2 can be connected to the first adapter cable CL1, and extends along the column direction Y from the main display area MA to the lead-out area FA, and connect to the bonding part PA, thereby connecting the second data line DAL2 to the bonding part PA through the first adapter cable CL1 and the second adapter cable CL2.

[0158] Furthermore, such as Figure 2 , Figures 21-23 As shown, to improve the uniformity of the membrane layer where the adapter cable is located, the drive backplane BP may include multiple first connection lines BL1 and multiple second connection lines BL2, wherein:

[0159] The first connecting line BL1 may extend along the row direction X and be spaced apart along the column direction Y. At least a portion of the first connecting lines BL1 may include first transition lines CL1 and first dummy lines DL1 spaced apart. For example, adjacent first transition lines CL1 and first dummy lines DL1 in the same first connecting line BL1 are located on the same side and are separated by a gap. A first connecting line BL1 may have at most two gaps and a first transition line CL1 and at least one first dummy line DL1 divided by the gaps.

[0160] The second connecting line BL2 may extend along the column direction Y and be spaced apart along the row direction X. At least some of the second connecting lines BL2 may include intermittently arranged second adapter lines CL2 and second dummy lines DL2. For example, adjacent second adapter lines CL2 and second dummy lines DL2 in the same second connecting line BL2 are located on the same layer and are separated by a gap. A second connecting line BL2 may have a gap and a second adapter line CL2 and a second dummy line DL2 separated by the gap. The second adapter line CL2 extends from the main display area MA to the lead-out area FA and is connected to the bonding part PA.

[0161] Each gap of the second connection line BL2 connected to each second data line DAL2 located in the same sub-display area SA can be distributed at intervals along a straight line trajectory, and the extension direction of the straight line trajectory intersects the row direction X and the column direction Y.

[0162] It should be noted that some of the first connection lines BL1 may not have a gap, but are continuous traces extending to the peripheral area WA, and are not connected to the data line DAL. Their function is to improve the uniformity of the second source / drain layer SD2. These first connection lines BL1 without gaps are the first dummy lines DL1. Simultaneously, some of the second connection lines BL2 may not have a gap, but are continuous traces extending to the lead-out area FA, and are not connected to the first adapter line CL1, but can be connected to the first dummy line DL1 and the first connection lines BL1 without gaps. While improving the uniformity of the third source / drain layer SD3, they can reduce the uniformity of the voltage drop of the first power signal VSS. These second connection lines BL2 without gaps are the second dummy lines DL2.

[0163] In the column direction Y, the first connecting line BL1 with a gap on the side away from the lead-out area FA can be a first connecting line BL1 without a gap. In the row direction X, the second connecting line BL2 with a gap is divided into two parts distributed along the row direction X. One part is connected to the second data line DAL2 in one sub-display area SA, and the other part is connected to the second data line DAL2 in another sub-display area SA. The two parts can be symmetrically arranged about the central axis of the main display area MA along the column direction Y, and there can be a second connecting line BL2 without a gap between the two parts.

[0164] The aforementioned second connection line BL2 is located on a different layer from the first connection line BL1, thus crossing within the space. Simultaneously, the first connection line BL1 is located on a different layer from the data line DAL, and the second connection line BL2 is insulated from the data line DAL, ensuring that any adapter line CL connects only to one second data line DAL2 and not to any other second data lines DAL2 or first data lines DAL1. For example, the second connection line BL2 can be located on the same layer as the data line DAL and the power line VDL, and on the side of the first connection line BL1 furthest from the substrate SU. A second connection line BL2 can be located between two adjacent line groups DU, spaced apart from the two data lines DAL of the line group DU.

[0165] Since the first dummy line DL1 and the second dummy line DL2 are respectively spaced apart from the first adapter line CL1 and the second adapter line CL2, the first dummy line DL1 and the second dummy line DL2 are not connected to the data signal DA. Based on this, the inventors propose that at least a portion of the first dummy line DL1 and at least a portion of the second dummy line DL2 can be connected to form a mesh structure, and this mesh structure can be connected to the first power bus VSL, thereby connecting to the first power signal VSS. This ensures that there are traces for transmitting the first power signal VSS within the display area AA, making the voltage drop distribution of the first power signal VSS more uniform, reducing the cross voltage of the display panel, and thus reducing power consumption.

[0166] Furthermore, in some embodiments of this disclosure, the first connecting line BL1 and the second connecting line BL2 can be arranged in layers, that is, the first adapter line CL1 and the first dummy line DL1 can be located on different layers, thereby separating them; the second adapter line CL2 and the second dummy line DL2 can be located on different layers, thereby separating them. The first adapter line CL1 and the second adapter line CL2 can be located on the same layer or on different layers, as long as they can be connected to form an adapter line CL. The first dummy line DL1 and the second dummy line DL2 can be located on the same layer or on different layers, as long as they can be connected to the first power bus VSL.

[0167] The wiring method of the first connecting line BL1 and the second connecting line BL2 is illustrated below:

[0168] like Figures 21-23 As shown, in some embodiments of this disclosure, the drive backplane BP further includes an array-distributed first adapter CP1 and an array-distributed second adapter CP2. The first adapter CP1, the second adapter CP2, and the first connecting line BL1 can be disposed on the same layer and can be located on the side of the data line DAL close to the substrate SU. The shapes of the first adapter CP1 and the second adapter CP2 can be circular, elliptical, polygonal, or other regular or irregular shapes.

[0169] like Figure 22 As shown, the number of first adapter sections CP1 in a column can be the same as the number of pixel circuits PC in a column of pixel circuits PC, and the first terminals of each write transistor T4 in the column of pixel circuits PC are connected in a one-to-one correspondence. Simultaneously, each column of first adapter sections CP1 can overlap with a data line DAL, and the data line DAL and each overlapping first adapter section CP1 are connected through contact holes. This allows a data line DAL to be connected to a column of pixel circuits PC via the first adapter sections CP1, enabling simultaneous input of data signals DA to the column of pixel circuits PC. Since a second data line DAL2 can be connected to a first adapter cable CL1, a first adapter part CP1 connecting the second data line DAL2 can be connected to the first adapter cable CL1, making the first adapter cable CL1 and the first adapter part CP1 an integral structure. Thus, the second data line DAL2 and the first adapter cable CL1 can be connected through the first adapter part CP1, and the interconnection of the second data line DAL2 and the first adapter cable CL1 can be achieved through the connection of the first adapter part CP1 and the first adapter cable CL1.

[0170] A second adapter section CP2 can overlap with a second connecting line BL2, and a second adapter line CL2 can be connected to a first adapter line CP1 as a single unit, overlapping and connecting with the second adapter section CP2. This allows the first adapter line CL1 and the second adapter line CL2 to be connected via the second adapter section CP2. In other words, an adapter line CL can include a first adapter section CP1 connecting the second data line DAL2, a first adapter line CL1, a second adapter section CP2 connecting the first adapter line CL1 and the second adapter line CL2, and a second adapter line CL2. This path allows the second data line DAL2 to be connected to the bonding section PA without passing through the corner of the outer perimeter area WA.

[0171] The mesh structure formed by the first dummy line DL1 and the second dummy line DL2 mentioned above can also be connected via the second adapter CP2. Specifically, at least a portion of the second adapter CP2 can be connected to the first dummy line DL1 as a single unit, and then at least a portion of the second dummy line DL2 can be connected to the second adapter CP2 connecting the first dummy line DL1. Thus, the first dummy line DL1 and the second dummy line DL2 are connected via a portion of the second adapter CP2, forming a mesh structure. Of course, the second adapter CP2 connecting the first dummy line DL1 and the second dummy line DL2 is a different second adapter CP2 from the second adapter CP2 in the adapter cable CL. Furthermore, a portion of the second adapter CP2 may not be connected to the first adapter cable CL1 and the first dummy line DL1. This portion of the second adapter CP2 can be spaced apart from the first connecting line BL1, as long as it does not affect the formation of the adapter cable CL and the aforementioned mesh structure that can access the first power signal VSS.

[0172] like Figures 22-23 As shown, the distribution of the first adapter CP1 and the second adapter CP2 will be described in detail below:

[0173] like Figure 22 As shown, in some embodiments of this disclosure, each first transition section CP1 and second transition section CP2 can be divided into multiple array-distributed transition groups CP, and a column of transition groups CP is located between two adjacent line groups DU, and a first connecting line BL1 can pass through a row of transition groups CP. A transition group CP may include two first transition sections CP1 and one second transition section CP2 arranged in a triangular distribution. Here, the triangular distribution means that the center line connecting the two first transition sections CP1 and the second transition section CP2 forms a triangle, which can be an isosceles triangle, etc., and is not specifically limited here. The two second transition sections CP2 can be symmetrically arranged about the center line extending along the column direction Y between two adjacent line groups DU.

[0174] For a transition group CP and a first connecting line BL1 passing through it, the two first transition parts CP1 are located on the side of the first connecting line BL1 closer to the lead-out area FA, and the second transition part CP2 is located on the side of the first connecting line BL1 away from the lead-out area FA.

[0175] Based on the above-described implementation method, the inventors discovered that the presence of the aforementioned gap would affect the uniformity of the display panel's image. Therefore, they proposed a solution to block at least part of the gap. The solution for blocking the gap is described in detail below:

[0176] like Figure 21 As shown, in some embodiments of this disclosure, the data line DAL and the power line VDL are located on the side of the first connection line BL1 away from the substrate SU. The data line DAL and the power line VDL can be used to shield at least a portion of the gap. For example, the gaps can be classified, with the gap located on the first connection line BL1 defined as the first gap 1, and the gap on the second connection line BL2 defined as the second gap 2.

[0177] Part of the first break gap 1 can overlap with the second connecting line BL2, thus being blocked by the second connecting line BL2; part of the first break gap 1 can overlap with the power line VDL, thus being blocked by the power line VDL. Simultaneously, if there are two first break gaps 1 on the same first connecting line BL1, both first break gaps 1 can be blocked by the second connecting line BL2, or both can be blocked by the power line VDL. The second break gap 2 is on the same layer as the second connecting line BL2 and the power line VDL, and therefore is not blocked by the second connecting line BL2 and the power line VDL. Alternatively, part of the data line DAL can overlap with part of the first break gap 1, thus using the data line DAL to block the first break gap 1.

[0178] Furthermore, the orthographic projection of the first break Gap1 on the substrate SU can be located within the orthographic projection of the power line VDL, the second connection line BL2, or the data line DAL that blocks it on the substrate SU, thereby completely blocking the first break Gap1.

[0179] Furthermore, the second gap, Gap2, can be blocked using the first electrode ANO of the light-emitting device or the channel line TL of the touch layer TSP. An example is given below:

[0180] like Figure 24As shown, in some embodiments of this disclosure, at least a portion of the second break gap 2 may overlap with a portion of the first electrode ANO, thereby being shielded by the first electrode ANO. The orthogonal projection of the second break gap 2 onto the substrate SU may lie within the orthogonal projection of the first electrode ANO that shields it onto the substrate SU, thereby completely shielding the second break gap 2. However, since the distribution of the first electrode ANO needs to meet certain pixel arrangement requirements, the structure of the first electrode ANO can be improved by providing an extension specifically designed to shield the second break gap 2. Specifically:

[0181] The first electrode ANO can be a single-layer or multi-layer structure and is a light-shielding structure. The first electrode ANO can include an electrode portion A0 and a first extension portion A1 and a second extension portion A2 extending outward from the edge of the electrode portion A0. That is, the first extension portion A1 and the second extension portion A2 can be radially connected to the edge of the electrode portion A0. The first extension portion A1 can be connected to the second electrode of the second light-emitting control transistor T6 and the second electrode of the second reset transistor T7 of the pixel circuit through a contact hole. The second extension portion A2 can overlap with the second break gap 2, thereby shielding the second break gap 2 through the second extension portion A2.

[0182] like Figure 25 As shown, in some other embodiments of this disclosure, at least a portion of the gap may overlap with a portion of the channel line TL of the touch electrode layer TMB. For example, the channel line TL may overlap with at least a portion of the second gap 2, thereby shielding the second gap 2 through the channel line TL. The orthographic projection of the second gap 2 on the substrate SU may be located within the orthographic projection of the channel line TL that shields it on the substrate SU, thereby completely shielding the second gap 2.

[0183] For example, the intersection of adjacent channel lines TL can be used to shield the second break Gap2. In order to increase the shielding range, an intersection TLs can be formed at the intersection of channel lines TL, that is, the interconnected channel lines TL can converge at the intersection TLs, and the width of the intersection is greater than the width of the channel line TL, so that the orthographic projection of the second break Gap2 on the substrate SU is located within the orthographic projection of the intersection TLs on the substrate SU.

[0184] In other embodiments of this disclosure, the above-described methods for blocking the gap can be combined in ways other than those described above. For example, in addition to being blocked by one of the second connection line BL2, the data line DAL, and the power line VDL, the same gap can also be blocked by at least one of the first electrode ANO and the channel line TL. The first electrode ANO and the channel line TL can block not only the second gap 2, but also the first gap 1.

[0185] like Figures 5-11, Figure 19 and Figure 22 As shown, based on the above embodiments, in some embodiments of this disclosure, the driving backplane BP further includes multiple shielding portions SL disposed on the same layer. The shielding portions SL can be located on the side of the pixel circuit PC away from the substrate SU, and can be located on the side of the data line DAL and power line VDL close to the substrate SU, and can be disposed on the same layer as the first connection line BL1. In the direction perpendicular to the substrate SU, the shielding portions SL can be disposed one-to-one with each pixel circuit PC, and one shielding portion SL overlaps with the channel of the first node N1 and the compensation transistor T2 of a pixel circuit PC, thereby blocking the channel of the first node N1 and the compensation transistor T2. At the same time, the shielding portion SL can be connected to the power line VDL connected to its corresponding pixel circuit PC, so that a second power signal VDD can be input to the shielding portion SL. Thus, by shielding the signal of the channel of the first node N1 and the compensation transistor T2 away from the substrate SU through the shielding portion SL, it is prevented from interfering with the signal of the gate of the driving transistor T3 and the compensation transistor T2. Therefore, shielding the first node N1 and the compensation transistor T2 by widening the power line VDL can be avoided, thereby reducing the parasitic capacitance between the power line VDL and the data line DAL. This helps to reduce the spacing between the data line DAL and the power line VDL, thus reducing the space occupied and improving resolution. In addition, the shielding part SL can also block light from the compensation transistor T2, which helps to ensure the stability of the electrical characteristics of the compensation transistor T2.

[0186] The following section provides a detailed explanation of the film layer driving the backplane BP using the pixel circuit mentioned above:

[0187] like Figure 3 , Figure 5 , Figures 13-20 As shown, in addition to the substrate SU, the driving backplane BP may also include a first semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a first insulating layer ILD0, a second gate layer GA2, a second insulating layer IL1, a second semiconductor layer IGL, a second gate insulating layer GI2, a third gate layer GA3, a third insulating layer IL2, a first source / drain layer SD1, a first planarization layer PLN1, a second source / drain layer SD2, a second planarization layer PLN2, a third source / drain layer SD3, and a third planarization layer PLN3, wherein:

[0188] The first semiconductor layer POL may be disposed on one side of the substrate SU, and includes the channel of the driving transistor T3, the writing transistor T4, the second reset transistor T7, the third reset transistor T8, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 in the pixel circuit PC. The material of the first semiconductor layer POL may be polycrystalline silicon.

[0189] The first gate insulating layer GI1 can cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 can be insulating materials such as silicon nitride and silicon oxide.

[0190] The first gate layer GA1 may be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU, and includes a second reset control line REL2, a light emission control line EML, a first scan line GAL1, and a first electrode Cst1 of the storage capacitor Cst, wherein:

[0191] The first electrode plate Cst1 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel for the driving transistor T3, and the first electrode plate Cst1 is reused as the gate for the driving transistor T3. The second reset control line REL2 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel for the second reset transistor T7 and the third reset transistor T8, and the overlapping portion of the second reset control line REL2 forms the gate for the second reset transistor T7 and the third reset transistor T8. The first scan line GAL1 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel for the writing transistor T4, and the overlapping portion of the first scan line GAL1 forms the gate for the writing transistor T4. The light emission control line EML overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel for the first light emission control transistor T5 and the second light emission control transistor T6, and the overlapping portion of the light emission control line EML forms the gate for the first light emission control transistor T5 and the second light emission control transistor T6.

[0192] The first insulating layer ILD0 can cover the first gate layer GA1, and its material can be insulating materials such as silicon nitride and silicon oxide.

[0193] The second gate layer GA2 may be disposed on the surface of the first insulating layer ILD0 away from the substrate SU, and includes a second electrode Cst2, which overlaps with the first electrode Cst1 to form a storage capacitor Cst.

[0194] The second insulating layer IL1 covers the second gate layer GA2. It can be a single-layer or multi-layer structure, and the material can include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin. For example, the second insulating layer IL1 can include a dielectric layer and a buffer layer stacked sequentially along the direction away from the substrate SU.

[0195] The second semiconductor layer IGL may be disposed on the surface of the second insulating layer IL1 away from the substrate SU, and includes the channel of the first reset transistor T1 and the compensation transistor T2. The material of the second semiconductor layer IGL may include semiconductor metal oxides such as indium gallium zinc oxide (IGZO).

[0196] The second gate insulating layer GI2 can cover the second semiconductor layer IGL, and its material can be insulating materials such as silicon nitride and silicon oxide.

[0197] The third gate layer GA3 may be disposed on the surface of the third gate insulating layer GI3 away from the substrate SU, and includes a first reset control line REL1, a first reset signal line VIL1, a second scan line GAL2, and at least a portion of the third reset signal line VIL3.

[0198] The first reset control line REL1 overlaps with a portion of the second semiconductor layer IGL. The overlapping portion of the second semiconductor layer IGL forms the channel of the first reset transistor T1, and the overlapping portion of the first reset control line REL1 forms the gate of the first reset transistor T1. The second scan line GAL2 overlaps with a portion of the second semiconductor layer IGL. The overlapping portion of the second scan line GAL2 forms the channel of the compensation transistor T2, and the overlapping portion of the second scan line GAL2 forms the gate of the compensation transistor T2.

[0199] The third insulating layer IL2 may cover the third gate layer GA3. It may be a single-layer or multi-layer structure, and the material may include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin. For example, the third insulating layer IL2 may include a dielectric layer and multiple inorganic insulating layers stacked sequentially along the direction away from the substrate SU.

[0200] The first source / drain layer SD1 may be disposed on the surface of the third insulating layer IL2 away from the substrate SU, and includes a second reset signal line VIL2 and at least a portion of the third reset signal line VIL3, that is, different regions of the third reset signal line VIL3 may be located in different layers.

[0201] The first planarization layer PLN1 can be disposed on the side of the first source / drain layer SD1 away from the substrate SU, and its material can be an insulating material such as resin. For example, the first source / drain layer SD1 can be covered with a passivation layer made of an insulating material such as silicon nitride, and then the passivation layer can be covered with the first planarization layer PLN1.

[0202] The second source / drain layer SD2 may be disposed on the surface of the first planarization layer PLN1 away from the substrate, and includes a first connection line BL1, a shielding portion SL, a first transition portion CP1, and a second transition portion CP2.

[0203] The second planarization layer PLN2 can cover the second source / drain layer SD2, and its material can be an insulating material such as resin.

[0204] The third source / drain layer SD3 may be disposed on the surface of the second planarization layer PLN2 away from the substrate SU, and includes a data line DAL, a power line VDL, and a second connection line BL2.

[0205] The third planarization layer PLN3 can cover the third source / drain layer SD3, and its material can be an insulating material such as resin. The first electrode ANO can be disposed on the surface of the third planarization layer PLN3 away from the substrate SU.

[0206] In addition, such as Figure 5 and Figure 12 As shown, a light-shielding layer BSM can be disposed between the substrate SU and the first semiconductor layer POL. This layer can be made of a light-shielding metal or other materials and can be a single-layer or multi-layer structure. At least a portion of the light-shielding layer BSM can overlap with at least a portion of the channel region of the transistors to block light illuminating the transistors, thereby stabilizing the electrical characteristics of the transistors. For example, the light-shielding layer BSM can include multiple arrayed light-shielding units BSM1, each of which can block the channel of a driving transistor T3. Simultaneously, each light-shielding unit BSM1 can be connected to the light-shielding layer BSM2, making the light-shielding layer BSM a single structure. The light-shielding layer BSM can also be connected to a first power bus VSL or a second power bus BVDL, thereby inputting a first power signal VSS or a second power signal VDD to the light-shielding layer BSM, thus achieving electrostatic shielding.

[0207] Furthermore, such as Figure 3 As shown, the light-shielding layer BSM can be covered by an insulating buffer layer BUF, and the first semiconductor layer POL can be disposed on the surface of the buffer layer BUF facing away from the substrate SU. The buffer layer BUF can be a single-layer or multi-layer structure, and its material can include insulating materials such as silicon nitride and silicon oxide.

[0208] In other embodiments of this disclosure, based on the various film layers of the drive backplane BP described above, the first connection line BL1 may also be located in the first source / drain layer SD1, and the second connection line BL2 may be located in the second source / drain layer SD2. Alternatively, the first connection line BL1 may be located in the third source / drain layer SD3, the second connection line BL2 may be located in the second source / drain layer SD2, and the data line DAL and power line VDL may be located in either the first source / drain layer SD1 or the second source / drain layer SD3. Furthermore, the first connection line BL1 may also be located in the third source / drain layer SD3, and the second connection line BL2 may be located in either the first source / drain layer SD1 or the second source / drain layer SD2. Wherein, if the first connection line BL1 and the second connection line BL2 intersect with other traces in the same layer, these traces can be disconnected, and the disconnected portions can be connected using connection units located in other film layers.

[0209] The patterns of each film layer on the drive backplane (BP) are described in detail below:

[0210] Taking the layers of a pixel circuit PC as an example:

[0211] like Figures 5-11 as well as Figure 13As shown, the first semiconductor layer POL may include an integrally structured first active portion ACT1, a second active portion ACT2, a third active portion ACT3, a fourth active portion ACT4, and a separate fifth active portion ACT5, wherein:

[0212] The first active section ACT1 can be arranged along the row direction X. The channel T31 of the driving transistor T3 is located in the first active section ACT1, and a portion of the channel T31 can be bent along the column direction Y in a direction away from the lead-out region FA. The channel T31 can be in the shape of "S", "n" or "I". The first plate Cst1 overlaps with the channel T31 to form the driving transistor T3.

[0213] The second active section ACT2 can extend along the column direction Y, with one end connected to one end of the first active section ACT1, and the other end extending away from the lead-out region FA of the first active section ACT1. The first scan line GAL1 can intersect the second active section ACT2 along the row direction X, and the first active section ACT1 corresponding to the intersection is the channel T41 of the write transistor T4.

[0214] The third active section ACT3 can extend along the column direction Y, with one end connected to the first active section ACT1 and one end connected to the second active section ACT2, and the other end extending towards the first active section ACT1 in a direction close to the lead-out area FA. The light-emitting control line EML can intersect with the third active section ACT3 along the row direction X, and the third active section ACT3 corresponding to the intersection is the channel T51 of the first light-emitting control transistor T5.

[0215] The fourth active section ACT4 can be arranged along the column direction Y, and one end is connected to the first active section ACT1. The second active section ACT2 and the fourth active section ACT4 are connected to the two ends of the first active section ACT1. The light-emitting control line EML can cross the fourth active section ACT4 along the row direction X. The fourth active section ACT4 corresponding to the crossing point is the channel T61 of the second light-emitting control transistor T6. The second reset control line REL2 is located on the side of the light-emitting control line EML near the lead-out area FA, and can cross the fourth active section ACT4 along the row direction X. The fourth active section ACT4 corresponding to the crossing point is the channel T71 of the second reset transistor T7.

[0216] The fifth active section ACT5 and the third active section ACT3 are distributed along the column direction Y and are located on the side of the first active section ACT1 near the lead-out region FA. The second reset control line REL2 can intersect the fifth active section ACT5 along the row direction X, and the fifth active section ACT5 corresponding to the intersection is the channel T81 of the third reset transistor T8.

[0217] In the first semiconductor layer POL, all regions except the channels of each transistor are doped regions. These doped regions are used to form the first and second electrodes of each transistor. The specific locations of the first and second electrodes are not specifically limited here, as long as they can be used to realize the connection relationship of the pixel circuit of 8T1C mentioned above.

[0218] like Figure 14 As shown, the first gate layer GA1 includes a first scan line GAL1, a light emission control line EML, and a second reset control line REL2, all of which extend along the row direction X and are distributed along the column direction Y with the first electrode Cst1. The first electrode Cst1 is located between the first scan line GAL1 and the light emission control line EML. The first scan line GAL1 is located on the side of the first electrode Cst1 away from the lead-out region FA, and the second reset control line REL2 is located on the side of the light emission control line EML close to the lead-out region FA.

[0219] like Figure 15 As shown, the second electrode plate Cst2 of the second gate layer GA2 overlaps with the first electrode plate Cst1 to form a storage capacitor Cst. In some embodiments of this disclosure, two adjacent circuit units CU are symmetrically arranged in the row direction X, and their second electrode plates Cst2 are also symmetrically arranged. The two middle adjacent second electrode plates Cst2 of each of the two adjacent circuit units CU can be connected by a protruding extension Cst21 extending along the row direction X. The second connecting line BL2 can cross the protruding extension Cst21 and can be connected through a contact hole, thereby connecting to both second electrode plates Cst2 simultaneously. There can be one or more contact holes. Where space permits, providing multiple contact holes is beneficial to reducing resistance.

[0220] like Figure 16 As shown, the second semiconductor layer IGL may include an oxide active portion ACT6 extending along the column direction Y. The oxide active portion ACT6 is located between the first reset control line REL1 and the third reset signal line VIL3, that is, the orthogonal projection of the oxide active portion ACT6 on the substrate SU is located between the orthogonal projections of the first reset signal line VIL1 and the third reset signal line VIL3 on the substrate SU.

[0221] like Figure 17As shown, the first reset control line REL1 of the third gate layer GA3 intersects with the oxide active portion ACT6 along the row direction X, and the oxide active portion ACT6 corresponding to the intersection is the channel T11 of the first reset transistor T1. The second reset control line REL2 is located on the side of the first reset control line REL1 near the lead-out region FA, and is spaced apart from the first reset control line REL1 along the column direction Y. The second reset control line REL2 intersects with the oxide active portion ACT6 along the row direction X, and the oxide active portion ACT6 corresponding to the intersection is the channel T21 of the compensation transistor T2. The first scan line GAL1 is located between the first reset control line REL1 and the second reset control line REL2, and intersects with the region of the oxide active portion ACT6 located between channels T11 and T21.

[0222] like Figure 16 As shown, the oxide active parts ACT6 of the two pixel circuits PC in the same circuit unit CU are arranged in parallel, and the ends of the two circuits far from the lead-out area FA are connected, so that the first pole of the first reset transistor T1 of the two pixel circuits PC is connected.

[0223] like Figure 15 and Figure 9 As shown, in some embodiments of this disclosure, the second gate layer GA2 may further include an auxiliary reset line REL1s and an auxiliary scan line GAL2s extending along the row direction X. The auxiliary reset line REL1s may overlap with the first reset control line REL1. For example, the orthogonal projection of the auxiliary reset line REL1s on the substrate SU is within the orthogonal projection of the first reset control line REL1 on the substrate SU, and their extension trajectories are the same. The first reset control line REL1 also intersects with the oxide active portion ACT6, and the oxide active portion ACT6 corresponding to the intersection is still the channel T11 of the first reset transistor T1. The auxiliary reset line REL1s at the intersection is also the gate of the first reset transistor T1. At the same time, the auxiliary reset line REL1s may be connected to the first reset control line REL1 through a contact hole in the display area AA, or they may be connected after extending them to the peripheral area WA, thereby increasing the area of ​​the gate of the first reset transistor T1.

[0224] The auxiliary scan line GAL2s can overlap with the second scan line GAL2. For example, the orthogonal projection of the auxiliary scan line GAL2s onto the substrate SU lies within the orthogonal projection of the second scan line GAL2 onto the substrate SU, and their extension trajectories are the same. The second scan line GAL2 also intersects with the oxide active portion ACT6, and the oxide active portion ACT6 corresponding to the intersection is still the channel T21 of the compensation transistor T2. The auxiliary scan line GAL2s at the intersection is also the gate of the compensation transistor T2. Simultaneously, the auxiliary scan line GAL2s can be connected to the second scan line GAL2 within the display area AA via a contact hole, or they can be extended to the peripheral area WA before being connected, thereby increasing the gate area of ​​the compensation transistor T2.

[0225] Furthermore, in some embodiments of this disclosure, such as Figure 7 As shown, to increase the channel length of the first reset transistor T1, the auxiliary reset line REL1s has a first auxiliary overlapping portion REL1s1 protruding in the column direction Y away from the auxiliary scan line GAL2s. The first auxiliary overlapping portion REL1s1 overlaps with the oxide active portion ACT6, and the area where the first auxiliary overlapping portion REL1s1 overlaps with the oxide active portion ACT6 is the gate of the first reset transistor T1. Simultaneously, to increase the channel length of the compensation transistor T2, the second auxiliary scan line GAL2s has a second auxiliary overlapping portion GAL2s1 protruding in the column direction Y toward the auxiliary reset line REL1s. The second auxiliary overlapping portion GAL2s1 overlaps with the oxide active portion ACT6, and the area where the second auxiliary overlapping portion GAL2s1 overlaps with the oxide active portion ACT6 is the gate of the compensation transistor T2.

[0226] like Figure 14 As shown, due to the presence of the second auxiliary overlapping portion GAL2s1, the first scan line GAL1 can form a notch GAL12 to avoid the second auxiliary scan line GAL2s1. The orthogonal projection of the second auxiliary overlapping portion GAL2s1 on the substrate SU is at least partially located within the orthogonal projection of the notch GAL12 on the substrate SU. Figure 16 As shown, a notch C11 can also be formed in the capacitor section C1 at the position corresponding to the notch GAL12.

[0227] In addition, such as Figure 9 and Figure 16As shown, the oxide active portion ACT6 can form a capacitor portion C1 extending in the row direction X in the region between channel T11 and channel T21. This capacitor portion C1 can overlap with the first scan line GAL1, thereby forming a capacitor with the first scan line GAL1. At the same time, this capacitor portion C1 can overlap with and connect to the first node N1. Through this capacitor, when the display panel is in a black state, the voltage of the data signal DA can be lowered to prevent it from exceeding the maximum voltage of the chip in the peripheral circuit or control circuit board. For a circuit unit CU, the capacitor portions C1 of the oxide active portion ACT6 of the two pixel circuits can extend in opposite directions.

[0228] The first reset control line REL1 in the third gate layer GA3 overlaps with a portion of the oxide active portion ACT6. The overlapping portion of the oxide active portion ACT6 forms the channel of the first reset transistor T1, and the overlapping portion of the first reset control line REL1 forms the gate of the first reset transistor T1. The second scan line GAL2 overlaps with a portion of the oxide active portion ACT6. The overlapping portion of the second scan line GAL2 forms the channel of the compensation transistor T2, and the overlapping portion of the second scan line GAL2 forms the gate of the compensation transistor T2. The first scan line GAL1 is located between the first reset control line REL1 and the second scan line GAL2, and the first reset signal line VIL1 is located on the side of the first reset control line REL1 furthest from the second scan line GAL2.

[0229] Furthermore, in some embodiments of this disclosure, such as Figure 9 and Figure 17 As shown, in order to increase the channel length of the first reset transistor T1, the first reset control line REL1 has a first overlapping portion REL11 that protrudes in the column direction Y away from the second scan line GAL2. The first overlapping portion REL11 overlaps with the oxide active portion ACT6, and the area where the first overlapping portion REL11 overlaps with the oxide active portion ACT6 is the gate of the first reset transistor T1. The first overlapping portion REL11 overlaps with the first auxiliary overlapping portion REL1s1, and the orthogonal projection of the first overlapping portion REL11 on the substrate SU is located within the orthogonal projection of the first auxiliary overlapping portion REL1s1 on the substrate SU. Meanwhile, in order to increase the channel length of the compensation transistor T2, the second scan line GAL2 has a second overlapping portion GAL21 that protrudes along the column direction Y toward the first reset control line REL1. The second overlapping portion GAL21 overlaps with the oxide active portion ACT6, and the area where the second overlapping portion GAL21 overlaps with the oxide active portion ACT6 is the gate of the compensation transistor T2. The second overlapping portion GAL21 overlaps with the second auxiliary overlapping portion GAL2s1, and the orthogonal projection of the second overlapping portion GAL21 on the substrate SU is located within the orthogonal projection of the second auxiliary overlapping portion GAL2s1 on the substrate SU.

[0230] like Figure 10 and Figure 18 As shown, the first source / drain layer SD1 may include a first connection portion SDL1, a second connection portion SDL2, a third connection portion SDL3, a fourth connection portion SDL4, a fifth connection portion SDL5, a sixth connection portion SDL6, a seventh connection portion SDL7, and a second reset signal line VIL2, wherein:

[0231] The second connecting part SDL2 can extend along the row direction X and overlap with the two second plates Cst2 of the two pixel circuits of the same circuit unit CU. It is connected to the two second plates Cst2 through contact holes, thereby connecting the two second plates Cst2 of the same circuit unit CU into a conductive whole.

[0232] The third connection part SDL3 can extend along the column direction Y. One end of the third connection part SDL3 can be connected to a second electrode plate Cst2 through a contact hole, and the other end can be connected to the area in the third active part ACT3 used to form the first electrode of the first light-emitting control transistor T5 through a contact hole.

[0233] Furthermore, in some embodiments of this disclosure, two adjacent circuit units CU are symmetrically arranged in the row direction X, and the two middle adjacent second pole plates Cst2 of each of the two adjacent circuit units CU can be connected by a protruding extension Cst21 extending along the row direction X. The protruding extension Cst21 connecting the two second pole plates Cst2 can be connected to the same third connection part SDL3 through a contact hole, so that the first power signal VDD can be transmitted to the two second pole plates Cst2 simultaneously through the same third connection part SDL3. That is to say, the pixel circuit PC to which the two second pole plates Cst2 belong share the same third connection part SDL3.

[0234] Of course, in other embodiments of this disclosure, the above-mentioned protruding extension Cst21 can also be disconnected. That is, the two second plates Cst2 extend outwards with protruding extensions Cst21, but the protruding extensions Cst21 are not directly connected. The two protruding extensions Cst21 are respectively connected to a third connecting part SDL3 through a contact hole, so that they do not share the third connecting part SDL3.

[0235] The first connecting part SDL1 can extend along the column direction Y and is located between the second connecting part SDL2 and the third connecting part SDL3. One end of the first connecting part SDL1 overlaps with the capacitor part C1 and is connected through a contact hole. The other end of the first connecting part SDL1 can overlap with the first electrode plate Cst1 and is connected through a contact hole passing through the second electrode plate Cst2. In order to facilitate the connection between the first connecting part SDL1 and the first electrode plate Cst1, a through hole Hc can be opened on the second electrode plate Cst2. The contact hole connecting the first connecting part SDL1 and the first electrode plate Cst1 passes through the through hole Hc.

[0236] The fourth connection portion SDL4 extends along the column direction Y and is located between the third connection portion SDL3 and the first connection portion SDL1. One end of the fourth connection portion SDL4 is connected to the region in the third active portion ACT3 that serves as the second electrode of the write transistor T4 through a contact hole, and the other end is connected to the region in the fifth active portion ACT5 that serves as the second electrode of the third reset transistor T8 through a contact hole. In some embodiments of this disclosure, in the scheme where the pixel circuit PCs belonging to the second electrode plate Cst2 mentioned above share the same first connection portion SDL1, the fourth connection portions SDL4 of the two pixel circuit PCs can be symmetrical about the third connection portion SDL3 to save space and facilitate high resolution.

[0237] The fifth connection portion SDL5 extends along the column direction Y, with one end connected to the first reset signal line VIL1 through contact hole h1, and the other end connected to the oxide active portion ACT6, which serves as the first electrode of the first reset transistor T1, through contact hole h2. Since the two oxide active portions ACT6 of the same circuit unit CU are connected at one end as the first electrode of the first reset transistor T1, a first reset signal line VIL1 can be simultaneously connected to the first reset transistor T1 of two pixel circuits in a circuit unit CU through one fifth connection portion SDL5. The fifth connection portion SDL5 is symmetrical about the axis of symmetry of the two pixel circuits of a circuit unit CU.

[0238] Furthermore, in some embodiments of this disclosure, two oxide active portions ACT6 of the same circuit unit CU are connected by an oxide connection portion ACT61. The oxide connection portion ACT61 can protrude along the column direction Y in a direction away from the oxide active portion ACT6, thereby allowing the contact hole h2 to correspond to the oxide connection portion ACT61 and preventing the contact hole h2 from exceeding the boundary of the oxide connection portion ACT61. Simultaneously, the area of ​​the first reset signal line VIL1 corresponding to the oxide connection portion ACT61 in the column direction Y is bent away from the oxide connection portion ACT61, forming a bent portion VIL11. The contact hole h1 is connected to this bent portion VIL11. By setting this bent portion VIL11, overlap with the oxide connection portion ACT61 can be avoided, while the area of ​​the first reset signal line VIL1 other than the bent portion VIL11 is closer to the oxide active portion ACT6 and the first reset control line REL1 in the column direction Y, which is beneficial for making the wiring and pixel circuit more compact and saving space. At the same time, the bent portion VIL11 can connect to the contact hole h1 while avoiding the contact hole h2.

[0239] The sixth connection part SDL6 can extend along the column direction Y and is located on the side of the first connection part SDL1 away from the fourth connection part SDL4. One end of the sixth connection part SDL6 can be connected to the region of the oxide active part ACT6 as the first electrode of the compensation transistor T2 through a contact hole, and the other end can be connected to the region of the first active part ACT1 as the second electrode of the driving transistor T3 through a contact hole.

[0240] The seventh connection portion SDL7 can be connected to the area of ​​the second active portion ACT2, which serves as the first electrode of the write transistor T4, via a contact hole. The shape of the seventh connection portion SDL7 can be circular, elliptical, polygonal, or other regular or irregular shapes, and is not specifically limited here.

[0241] Furthermore, in some embodiments of this disclosure, the capacitor portion C1 may extend toward the contact hole connecting the seventh connection portion SDL7 and the second active portion ACT2. However, to avoid the contact hole, the contour of the end of the capacitor portion C1 near the contact hole may be arc-shaped and not overlap with the seventh connection portion SDL7. This facilitates maximizing the area of ​​the capacitor portion C1 without overlapping with the contact hole. Correspondingly, to match the shape of the first capacitor C1 and form a capacitor, the first scan line GAL1 has a second capacitor portion GAL11 protruding along the column direction Y in a direction away from the second scan line GAL2. The second capacitor portion GAL11 overlaps with the capacitor portion C1 to form a capacitor, and the orthographic projection of the capacitor portion C1 on the substrate SU is located within the orthographic projection of the second capacitor portion GAL11 on the substrate SU. The side of the second capacitor portion GAL11 near the second active portion ACT2 may also be arc-shaped, thus having the same shape as the capacitor portion C1. Of course, the first capacitor C1 may also be rectangular or other shapes, and the second capacitor portion GAL11 may have the same shape as the first capacitor C1.

[0242] The eighth connection portion SDL8 can be connected to the area between channels T61 and T71 in the fourth active portion ACT4 via a contact hole, thereby connecting to the second electrode of the second reset transistor T7 and the second light-emitting control transistor T6. The shape of the eighth connection portion SDL8 can be circular, elliptical, polygonal, or other regular or irregular shapes, and is not specifically limited here.

[0243] like Figure 11 and Figure 19 As shown, in the second source / drain layer SD2, the shielding portion SL overlaps with one end (first node N1) where the first connecting portion SDL1 and the capacitor portion C1 are connected, and also overlaps with the channel T21 of the compensation transistor T2. Simultaneously, in the circuit unit CU where the shielding portion SL and the overlapping first connecting portion SDL1 are located, the shielding portion SL overlaps with the second connecting portion SDL2 and is connected through a contact hole. The second connecting portion SDL2 can simultaneously connect to the two second plates Cst2 of the same circuit unit CU through the contact hole, thereby connecting the shielding portion SL and the two second plates Cst2 of the circuit unit CU into a conductive whole. The first transition portion CP1 is located between the first connecting line BL1 and the shielding portion SL.

[0244] In the circuit unit CU where a shielding part SL and a third connecting part SDL3 overlapping with it are located, the two data lines DAL connected to the circuit unit CU are located on both sides of the shielding part SL, and the power line VDL connected to the circuit unit CU is located between the two data lines DAL and overlaps with the shielding part SL.

[0245] The second source / drain layer SD2 may further include a first electrode transition portion CP3 connected to the eighth connection portion SDL8, which can be connected to the first electrode ANO through the second electrode transition portion CP4 in the third source / drain layer SD3. The first electrode transition portion CP3 may include a body portion CP31 and a transition extension portion CP32 connected to the edge of the body portion CP31. The transition extension portion CP32 may extend in a straight line, and its direction may be the row direction X or the column direction Y, or it may be a direction different from the row direction X and the column direction Y. The body portions CP31 of the two first electrode transition portions CP3 connected to the two eighth connection portions SDL8 of the two pixel circuits PC of the same pixel unit CU may extend in the row direction X. The extension directions of the transition extension portions CP32 of the two first electrode transition portions CP3 may be different. For example, one transition extension portion CP32 may extend in the row direction X, and the other may extend at an angle of less than 90° to both the row direction X and the column direction Y. That is to say, the two first electrode transition portions CP3 may be asymmetrical, or they may be symmetrical.

[0246] like Figure 5 and Figure 20 As shown, the data line DAL located in the third source-drain layer SD3 can be connected to the seventh connection part SDL7 through a contact hole, thereby connecting the data line DAL to the first terminal of the write transistor T4. In a power line VDL and its connected circuit unit CU, the power line VDL has protrusions VDL1 that bulge outwards in the row direction X. The two protrusions VDL1 overlap with the channels T11 of the first reset transistors of the two pixel circuits PC, thereby providing shielding and light-blocking functions through the protrusions VDL1. The first power bus VSL can be located at least partially in the third source-drain layer SD3, and the second power bus BVDL can be located in the lead-out area FA, between the bonding part PA and the display area AA. The second power bus BVDL can extend in the row direction. The third source-drain layer SD3 is located on the side close to the substrate SU and can be connected to the portion of each power line VDL extending into the lead-out area FA through a contact hole, thus avoiding short circuit with the data line DAL.

[0247] Furthermore, the power line VDL can be connected to the shielding part SL through the contact hole, thereby connecting to the first electrode (part of the fifth active part ACT5) of the first light-emitting control transistor T5 through the shielding part SL, the second connecting part SDL2, the second electrode plate Cst2, and the third connecting part SDL3. The first power signal VDD is transmitted using the second electrode plate Cst2. The third connecting part SDL3 only needs to connect the second electrode plate Cst2 to the fifth active part ACT5, instead of transmitting the first power signal VDD in the horizontal direction X. This reduces the width of the third connecting part SDL3 in the horizontal direction X, which can be twice the width of the data line DAL. This minimizes the width of the third connecting part SDL3 while ensuring the size requirements of the contact hole, thus saving space. Simultaneously, the power line VDL is connected to the two second electrodes Cst2 of the same circuit unit CU through the shielding part SL and the second connecting part SDL2, forming a network for transmitting the first power signal VDD, which helps reduce resistive-capacitive loading (RC loading).

[0248] Furthermore, in some embodiments of this disclosure, for the data line DAL and power line VDL connected to the same circuit unit CU, a data line bending portion DAL11 may be bent in the row direction X away from the power line VDL. The data line bending portion DAL11 and the capacitor portion C1 are linearly distributed in the row direction X to avoid overlapping with the capacitor portion C1. At the same time, bending the data line bending portion DAL11 away from the first connection portion SDL1 helps to increase the distance with the first connection portion SDL1, which can prevent the data signal DA from causing crosstalk to the first node N1 of the pixel circuit PC.

[0249] Furthermore, the third source / drain layer SD3 may also include a second electrode transition portion CP4 connected to the first electrode transition portion CP3 through a contact hole, and the second electrode transition portion CP4 may be connected to the first electrode ANO through the contact hole, thereby connecting through the area between the second electrode transition portion CP4, the first electrode transition portion CP3, the eighth connection portion SDL8 and the channel T71 of the second reset transistor T7 and the channel T61 of the second light-emitting control transistor T6 in the fourth active portion ACT4, that is, connecting with the second electrode of the second reset transistor T7 and the second electrode of the second light-emitting control transistor T6.

[0250] In addition, such as Figure 24 As shown, in some embodiments of this disclosure, adjacent shielding portions SL in the same row of pixel circuit PC can be connected by connecting segment SL1, further increasing the range of conductive network that can access the first power signal VDD, which is beneficial to reducing resistive-capacitive loading (RC loading).

[0251] The following is a detailed explanation of the routing method for the PC connection of a row pixel circuit:

[0252] like Figure 27 As shown, the first reset control line REL1, the first reset signal line VIL1, the second reset control line REL2, the second reset signal line VIL2, the third reset signal line VIL3, the first scan line GAL1, the second scan line GAL2, and the light emission control line EML, which are connected to the same row pixel circuit PC, all extend along the row direction X and are distributed along the column direction Y.

[0253] The first reset control line REL1, the first scan line GAL1, the second scan line GAL2, the third reset signal line VIL3, the light emission control line EML, and the second reset control line REL2 are located between the first reset signal line VIL1 and the second reset signal line VIL2; the first scan line GAL1, the second scan line GAL2, at least a portion of the third reset signal line VIL3 (line body VIL31) and the light emission control line EML are located between the first reset control line REL1 and the second reset control line REL2; the second scan line GAL2 is located between the first scan line GAL1 and the light emission control line EML; the second electrode Cst2 is located between the second scan line GAL2 and at least a portion of the third reset signal line VIL3 (line body VIL31); the light emission control line EML overlaps with at least a portion of the third reset signal line VIL3 (line branch VIL32).

[0254] To save space and improve resolution, some traces of different film layers can overlap. For example:

[0255] In some embodiments of this disclosure, a first reset signal line VIL1 connecting the (n+1)th row pixel circuit PC overlaps with a second reset control line REL2 connecting the nth row pixel circuit PC, and their orthogonal projections on the substrate SU at least partially coincide along the row direction X. Furthermore, a first reset signal line VIL1 overlaps with a first connection line BL1.

[0256] In some embodiments of this disclosure, the second reset signal line VIL2 connected to the (n+1)th row pixel circuit PC overlaps with both the first reset control line REL1 and the first scan line GAL1 connected to the nth row pixel circuit PC, meaning that their orthogonal projections on the substrate SU at least partially coincide along the row direction X.

[0257] In some embodiments of this disclosure, the second reset signal line VIL2 may have a bent portion VIL21 that bends along the column direction Y. A portion of the shielding portion SL connecting the (n+1)th row pixel circuit PC may be located within the bent portion VIL21 connecting the second reset signal line VIL2 to the nth row pixel circuit PC. That is, the orthographic projection of a portion of the shielding portion SL on the substrate SU lies within the orthographic projection of the bent portion VIL21 on the substrate SU, thereby allowing the shielding portion SL to be avoided by the bent portion VIL21. The fourth active portion ACT4 of the two pixel circuit PCs in the same circuit unit CU is connected to the bent portion VIL21 of the second reset signal line VIL2 through contact holes.

[0258] The structure of the third reset signal line VIL3 is described in detail below:

[0259] like Figures 9-11 and Figure 18 As shown, the third reset signal line VIL3 may include a line body VIL31 extending along the row direction X and a line branch VIL32 connected to the side of the line body VIL31 near the second reset signal line VIL2. The line body VIL31 and the line branch VIL32 are located on different layers. The line body VIL31 is located between the second scan line GAL2 and the second reset control line REL2, and overlaps with the light emission control line EM. The line branch VIL32 may extend between the second reset control line REL2 and the second reset signal line VIL2, and is connected to the first terminal of the third reset transistor T8. The line body VIL31 is located in the third gate layer GA3, and the line branch VIL32 is located in the first source / drain layer SD1.

[0260] Furthermore, the line branch VIL32 may include a first segment VIL321, a second segment VIL322, and a third segment VIL323. The first segment VIL321 may extend along the column direction Y, and the third segment VIL323 may extend along the row direction X. The second segment VIL322 forms a certain angle with both the first segment VIL321 and the third segment VIL323, and the second segment overlaps with the second reset control line REL2. The third segment VIL323 is located on the side of the second reset control line REL2 away from the first segment VIL321 and the line body VIL31.

[0261] One end of the first segment VIL321 is connected to the line body VIL31 through a contact hole, and the other end is connected to one end of the second segment VIL322. The other end of the second segment VIL322 is connected to one end of the third segment VIL323. The other end of the second segment VIL323 is partially connected to the fifth active section ACT5 through a contact hole, thereby connecting the line body VIL31 to the third reset transistor T3 for transmitting the third reset signal VI3. The second segment VIL322 forms an angle greater than 90° with both the first segment VIL321 and the third segment VIL323 to avoid the bend in the second reset signal line VIL21 and the contact hole connecting the fourth connecting section SDL4 to the fifth active section ACT5. The fifth active section ACT5 may have a region extending along the X direction, which serves as the first electrode of the third reset transistor T3, and the third segment VIL323 may overlap with this region. The first segment VIL321 may overlap with a portion of the fourth active section ACT4 that forms the second reset transistor T7.

[0262] Furthermore, the angle between the second segment VIL322 and the first segment VIL321 and the third segment VIL323 can be the same, and can be 120°, 125°, 130°, 135°, etc., without special limitation. Of course, the angle between the second segment VIL322 and the first segment VIL321 and the third segment VIL323 can also be different.

[0263] The distribution of the first adapter CP1, the second adapter CP2, the first electrode adapter CP3, and the second electrode adapter CP4 will be explained below:

[0264] like Figure 19 , Figure 21 , Figure 22 and Figure 25 As shown, in addition to the first adapter CP1 and the second adapter CP2, the adapter group CP may also include two first electrode adapters CP3. The two first electrode adapters CP3 belong to two adjacent circuit units CU in the row direction X, but the first adapter CP1 is connected to the write transistor T4 of the (n+1)th row pixel circuit PC. At the same time, the first electrode adapter CP3 is connected to the second electrode of the second light-emitting control transistor T6 and the second reset transistor T7 of the nth row pixel circuit PC.

[0265] Two first electrode adapters CP3 can be located on either side of a second adapter CP2, and are connected to two second electrode adapters CP4 through a third contact hole H3; the first adapter CP1 in the adapter group CP can be connected to the data line DAL through the first contact hole H1, and the second adapter CP2 can be connected to the second connecting line BL2 (second adapter line CL2 or second dummy line DL2) through the second contact hole H2. The two first electrode adapters CP3 are asymmetrical about the second adapter CP2.

[0266] Furthermore, such as Figure 21 and Figure 22 As shown, each first contact hole H1 and second contact hole H2 can be divided into multiple arrayed hole groups H, and a row of hole groups H is located between the power lines VDL connected to two adjacent circuit units CU. It should be noted that since the power lines VDL connected to the same circuit unit CU are the same as the power lines VDL connected to the two pixel circuits PC of that circuit unit CU, the power lines VDL connected to the same circuit unit CU can be regarded as a whole, and a row of hole groups H is actually located between two wholes. Of course, if the power lines VDL connected to the same circuit unit CU are a single structure, then a row of hole groups H is located between two power lines VDL. A hole group H includes two first contact holes H1, one second contact hole H2, and two third contact holes H3, and the two first contact holes H1 and one second contact hole H2 can be triangularly distributed; a first connecting line BL1 passes through a row of hole groups H, and divides the two first contact holes H1 on the same side of the first connecting line BL1, and divides the two third contact holes H3 and the second contact hole H2 on the other side of the first connecting line BL1.

[0267] In the same hole group H, the first contact hole H1 is connected to the (n+1)th row pixel circuit, and the third contact hole H3 is connected to the nth row pixel circuit. The two third contact holes H3 are located on either side of the second contact hole H2 and are distributed along the column direction Y. The distance between the two third contact holes H3 in the row direction is approximately equal. The two third contact holes H3 and the first contact hole H1 are also triangularly distributed, thus blurring the visual effect and making the first contact hole H1 less noticeable, which helps improve the uniformity of the display. Furthermore, the two first contact holes H1 can be symmetrically arranged about the second contact hole H2.

[0268] In addition, such as Figure 21 As shown, the power line VDL connected to the same circuit unit CU is connected via a fourth contact hole H4 and a shielding portion SL overlapping with the circuit unit CU, with each fourth contact hole arrayed. Two adjacent fourth contact holes H4 in the row direction X can be distributed along the column direction Y, thereby further blurring the visual effect and helping to improve the uniformity of the display. Alternatively, two adjacent fourth contact holes H4 in the row direction X can also be symmetrically arranged about a second contact hole H2 between the power lines VDL to which they are connected.

[0269] For example, the second contact hole H2 can be located between the first scan line GAL1 and the first reset signal line VIL1; the third contact hole H3 can be located between the light emission control line EML and the second reset signal line REL2; and the fourth contact hole H4 can be located between the second scan line GAL2 and the light emission control line EML.

[0270] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. Its specific structure and beneficial effects can be referred to the embodiments of the display panel described above, and will not be repeated here. The display device of this disclosure can be a mobile phone, television, tablet computer, or, of course, can also be used in electronic devices with display functions such as watches and bracelets, which will not be listed here.

[0271] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a display area and a peripheral area outside the display area, the peripheral area including a lead-out area extending in a direction away from the display area, the lead-out area having a binding portion, the display area and the lead-out area being distributed along a column direction; the display area including a main display area and sub-display areas disposed on both sides of the main display area along a row direction; The display panel includes a driving backplate and a plurality of light-emitting devices disposed on one side of the driving backplate. The driving backplate includes a substrate and a plurality of circuit units located on one side of the substrate. Each circuit unit includes two pixel circuits distributed along the row direction, and the two pixel circuits of the same circuit unit are symmetrically arranged. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked in a direction away from the driving backplate, wherein the first electrode is connected to a pixel circuit. The drive backplate includes: A first power bus is located in the peripheral area and connected to the second electrode; Multiple data lines extend along the column direction and are divided into multiple line groups distributed along the row direction. Each line group includes two data lines distributed along the row direction. The two data lines of one line group are respectively connected to two columns of pixel circuits of one column of circuit units. Each data line includes multiple first data lines and second data lines. The first data lines extend from the main display area to the lead-out area and are connected to the binding part. The second data lines are located in the sub-display area. Multiple power lines extend from the display area to the lead-out area along the column direction; two columns of pixel circuits of one column of the circuit unit are connected to one of the power lines; Multiple first connecting lines extend along the row direction, and at least some of the first connecting lines include first adapter lines and first dummy lines spaced apart; the first adapter lines extend from the sub-display area to the main display area. Multiple second connecting lines extend along the column direction, one second connecting line is located between two adjacent line groups, and the data lines of the two adjacent line groups are symmetrically arranged with respect to the second connecting line between the two line groups; at least a portion of the second connecting lines include second adapter lines and second dummy lines arranged at intervals; the second adapter lines extend from the main display area to the lead-out area and are connected to the binding part; A first adapter cable and a second adapter cable are connected to form an adapter cable; a second data cable is connected to the bonding part through at least one of the adapter cables; The first connecting line is insulated from the data line; at least a portion of the first dummy line and at least a portion of the second dummy line are connected, and are connected to the first power bus.

2. The display panel according to claim 1, wherein, The first adapter line and the first dummy line are disposed on the same layer on the side of the power line closer to the substrate; the second adapter line and the second dummy line are disposed on the same layer on the side of the first connecting line away from the substrate. In the same first connecting line, adjacent first adapter wires and first dummy wires are separated by a break; in the same second connecting line, adjacent second adapter wires and second dummy wires are separated by a break. At least a portion of the break in the first connecting line overlaps with the second connecting line or the power line.

3. The display panel according to claim 2, wherein, The first connection line is located on the side of the data line closer to the substrate.

4. The display panel according to claim 3, wherein, At least a portion of the fracture overlaps with a portion of the first electrode.

5. The display panel according to claim 2, wherein, The display panel also includes: A touch layer is disposed on the side of the light-emitting device away from the substrate, and includes a touch electrode layer, wherein the touch electrode layer is a mesh structure surrounded by multiple channel lines, and at least part of the break overlaps with part of the channel lines.

6. The display panel according to claim 5, wherein, The break in the first connecting line is the first break, and the break in the second connecting line is the second break; A portion of the first break overlaps with the second connecting line, and another portion of the first break overlaps with the power line; The second break overlaps with the first electrode or the channel line.

7. The display panel according to claim 1, wherein, A portion of the first adapter wire extends continuously along the row direction to the outer perimeter area, and a portion of the second adapter wire extends continuously along the column direction to the lead-out area.

8. The display panel according to claim 3, wherein, The second connecting line is disposed on the same layer as the data line and the power line, and is located on the side of the first connecting line away from the substrate; The drive backplane also includes an array of first adapters and an array of second adapters, wherein the first adapter, the second adapter, and the first connecting line are arranged on the same layer. A column of first adapter sections overlaps with a data line, and the data line is connected to each pixel circuit in a column of pixel circuits through each of the overlapping first adapter sections; a first adapter line is connected to a second data line through a first adapter section; A second adapter section overlaps with a second connecting line, and a second adapter line is connected to a first adapter line through a second adapter section.

9. The display panel according to claim 8, wherein, At least a portion of the second dummy line is connected to at least a portion of the first dummy line via at least a portion of the second adapter.

10. The display panel according to claim 9, wherein, The first adapter is connected to the data cable through a first contact hole; the second adapter is connected to the second connecting cable through a second contact hole. Each of the first contact holes and the second contact holes can be divided into multiple arrayed hole groups, and a column of the hole groups is located between the power lines connected to two adjacent circuit units; One of the hole groups includes two first contact holes and one second contact hole, with the two first contact holes symmetrically arranged about the second contact hole.

11. The display panel according to claim 10, wherein, The two first contact holes and one second contact hole in the same hole group are arranged in a triangular pattern.

12. The display panel according to claim 11, wherein, The driving backplane further includes an array of first electrode adapters and an array of second electrode adapters. The first electrode adapters are disposed on the same layer as the first and second electrode adapters. The second electrode adapters are located on the side of the first electrode adapters away from the substrate, and one first electrode adapter and one second electrode adapter overlap and are connected through a third contact hole. The first electrode is connected to the pixel circuit through the second electrode adapter, the third contact hole, and the first electrode adapter. The hole group further includes the third contact hole. In the same group of holes, the first contact hole is connected to the (n+1)th row pixel circuit, and the third contact hole is connected to the nth row pixel circuit; the two third contact holes are located on both sides of the second contact hole and are distributed along the column direction.

13. The display panel according to any one of claims 1-12, wherein, The pixel circuit includes a driving transistor, a writing transistor, a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor; the driving backplane also includes a first reset control line, a first reset signal line, a second reset control line, a second reset signal line, a third reset signal line, a first scan line, a second scan line, and a light-emitting control line; The gate of the driving transistor is connected to the first node, the first electrode is connected to a power line through the first light-emitting control transistor, and the second electrode is connected to the first electrode of the light-emitting device through the second light-emitting control transistor; the gates of the first light-emitting control transistor and the second light-emitting control transistor are connected to the light-emitting control line. The gate of the first reset transistor is connected to the first reset control line, the first terminal is connected to the first reset signal line, and the second terminal is connected to the first node; The gate of the write transistor is connected to the first scan line, the first electrode is connected to a data line, and the second electrode is connected to the first electrode of the drive transistor. The gate of the compensation transistor is connected to the second scan line, the first terminal is connected to the second terminal of the driving transistor, and the second terminal is connected to the first node; The gate of the two reset transistors is connected to the second reset control line, the first electrode is connected to the second reset signal line, and the second electrode is connected to the first electrode. The gate of the third reset transistor is connected to the second reset control line, the first terminal is connected to the third reset signal line, and the second terminal is connected to the first terminal of the driving transistor. The first plate of the storage capacitor is connected to the power line, and the second plate is connected to the first node. The first reset transistor and the compensation transistor are metal-oxide transistors; the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor are polysilicon transistors.

14. The display panel according to claim 13, wherein, The drive backplate also includes: A first semiconductor layer is disposed on one side of the substrate and includes the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light-emitting control transistor, and the channel of the second light-emitting control transistor. A first gate insulating layer covers the first semiconductor layer; A first gate layer is disposed on the surface of the first gate insulating layer away from the substrate and overlaps with at least a portion of the first semiconductor layer. The first gate layer includes a second reset control line, the light emission control line, the first scan line, and the first electrode plate. A first insulating layer covers the first gate layer; The second gate layer is disposed on the surface of the first insulating layer away from the substrate, and includes a second electrode plate overlapping the first electrode plate; A second insulating layer covers the second gate layer; A second semiconductor layer is disposed on the surface of the second insulating layer away from the substrate, and includes the channel of the first reset transistor and the compensation transistor; A second gate insulating layer covers the second semiconductor layer; A third gate layer is disposed on the surface of the third gate insulating layer away from the substrate and overlaps with at least a portion of the second semiconductor layer. The third gate layer includes the first reset control line, the first reset signal line, the second scan line, and at least a portion of the third reset signal line. A third insulating layer covers the third gate layer; A first source / drain layer is disposed on the surface of the third insulating layer away from the substrate, and includes the second reset signal line and at least a portion of the third reset signal line; A first planarization layer is disposed on the side of the first source / drain layer away from the substrate; The second source / drain layer is disposed on the surface of the first planarization layer away from the substrate, and includes the first connection line; A second planarization layer covers the second source / drain layer; The third source / drain layer is disposed on the surface of the second planarization layer away from the substrate, and includes the data line, power line, and second connection line; A third planarization layer covers the third source / drain layer; the first electrode is disposed on the surface of the third planarization layer away from the substrate.

15. The display panel according to claim 14, wherein, The second semiconductor layer includes an active oxide portion extending along the column direction, the active oxide portion being located between the first reset signal line and the third reset signal line; the first reset control line overlaps with the active oxide portion to form the first reset transistor, and the second reset control line overlaps with the active oxide portion to form the compensation transistor; The first source / drain layer includes a first connection portion, one end of which is connected to the first electrode plate, and the other end of which is connected to the oxide active portion between the channel of the first reset transistor and the second reset control line. The driving backplane also includes a plurality of shielding portions located in the second source-drain layer; one of the shielding portions overlaps with a first connection portion of the pixel circuit and the channel of the compensation transistor, and is connected to a power line connected to the pixel circuit.

16. The display panel according to claim 15, wherein, In a circuit unit containing the shielding portion and the first connecting portion overlapping therewith, both second electrode plates of the pixel circuit of the circuit unit overlap and are connected to the shielding portion.

17. The display panel according to claim 16, wherein, The first source / drain layer includes a second connection portion and a third connection portion, wherein the second connection portion connects two second electrode plates; and the third connection portion connects one second electrode plate and the first electrode of the first light-emitting control transistor.

18. The display panel according to claim 15, wherein, In a circuit unit containing the shielding portion and the first connecting portion overlapping therewith, the two data lines connected to the circuit unit are located on both sides of the shielding portion, and the power line connected to the circuit unit is located between the two data lines, overlapping and connected to the shielding portion.

19. The display panel according to claim 14, wherein, In one of the power lines and the circuit units connected thereto, the power line has protrusions that bulge outwards in both directions along the row direction, and the two protrusions overlap with the channels of the first reset transistors of the two pixel circuits, respectively.

20. The display panel according to claim 15, wherein, The first reset control line, first reset signal line, second reset control line, second reset signal line, third reset signal line, first scan line, second scan line, and light emission control line connecting the pixel circuits in the same row all extend along the row direction and are distributed along the column direction; The first reset control line, the first scan line, the second scan line, the third reset signal line, the light emission control line, and the second reset control line are located between the first reset signal line and the second reset signal line; the first scan line, the second scan line, at least a portion of the third reset signal line, and the light emission control line are located between the first reset control line and the second reset control line; the second scan line is located between the first scan line and the light emission control line; the second electrode is located between the second scan line and at least a portion of the third reset signal line; the light emission control line overlaps with at least a portion of the third reset signal line. The first reset signal line connecting the pixel circuit in row (n+1) overlaps with the second reset control line connecting the pixel circuit in row (n).

21. The display panel according to claim 20, wherein, The second reset signal line connecting the pixel circuit in the (n+1)th row overlaps with the first reset control line and the first scan line connecting the pixel circuit in the nth row.

22. The display panel according to claim 20, wherein, The third reset signal line includes a line body extending along the row direction and a line branch connected to the side of the line body near the second reset signal line. The line body and the line branch are located on different layers. The line body is located between the second scan line and the second reset control line and overlaps with the light emission control line. The line branch extends between the second reset control line and the second reset signal line and is connected to the first electrode of the third reset transistor.

23. The display panel according to claim 22, wherein, The line body is located in the third gate layer, and the line branch is located in the first source / drain layer.

24. The display panel according to claim 20, wherein, The first reset signal line overlaps with the first connection line.

25. The display panel according to claim 20, wherein, The oxide active portion has a capacitor portion extending along the row direction, and the capacitor portion is connected between the channels of the first reset transistor and the compensation transistor; the capacitor portion overlaps with the first scan line and is connected to the first connection portion.

26. A display device comprising the display panel according to any one of claims 1-25.

Images