A signal detection system and method

Abstract

The application provides a signal detection system and method, which sends mode information matched with a to-be-tested system and parameter information matched with the to-be-tested system to a field programmable gate array by an advanced reduced instruction set machine processor. The field programmable gate array generates an excitation signal of the to-be-tested system according to the mode information and the parameter information. In the application, based on the advanced reduced instruction set machine processor and the field programmable gate array, different to-be-tested systems can be configured by the advanced reduced instruction set machine processor, so that the field programmable gate array works in a target mode matched with the to-be-tested system and generates an excitation signal matched with the to-be-tested system, thereby making the signal detection system applicable to to-be-tested systems in various application scenarios and effectively improving the versatility of the signal detection system.

Description

Technical Field

[0001] This application relates to the field of signal detection technology, and in particular to a signal detection system and method. Background Technology

[0002] Weak signal detection technology uses electronic and information theory methods to detect weak, useful signals obscured by noise, analyze the causes and patterns of noise generation, and study the characteristics and correlations of the measured signal. Weak signal detection is an important means of developing advanced technologies and exploring and discovering new natural laws, and it is of great significance for promoting the development of related fields.

[0003] With the development of science and technology, the need for weak signal detection is becoming increasingly urgent. However, due to the diverse application scenarios of weak signal detection, it is usually necessary to customize corresponding electronic systems for different application scenarios to achieve signal detection of the system under test in the corresponding application scenarios.

[0004] Because current signal detection methods are not applicable to all application scenarios, corresponding electronic systems need to be customized for each application scenario to detect signals in the system under test, resulting in poor versatility. Summary of the Invention

[0005] This application provides a signal detection system and method, the purpose of which is to solve the problem of poor versatility of signal detection systems.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] Firstly, this application provides a signal detection system, including: a field-programmable gate array (FPGA) and an advanced reduced instruction set machine (ARM) processor;

[0008] The ARM processor is used to send mode information matching the system under test and parameter information matching the system under test to the FPGA. The mode information instructs the FPGA to operate in a target mode matching the system under test. The target mode is used to generate an excitation signal matching the system under test. The parameter information is used to indicate the parameters required to generate the excitation signal of the system under test.

[0009] The FPGA is used to generate excitation signals for the system under test based on the mode information and parameter information.

[0010] In one possible implementation, the FPGA is further used for:

[0011] Based on the mode information and parameter information, a reference signal for the system under test is generated; based on the reference signal, the first response signal generated by the system under test in response to the excitation signal is subjected to phase-locked amplification to obtain a second response signal, and the second response signal is sent to the ARM processor;

[0012] The ARM processor is also used to process the second response signal.

[0013] In one possible implementation, the parameter information is further used to indicate analog-to-digital converter parameters and digital-to-analog converter parameters, and the FPGA is further used for:

[0014] Based on the analog-to-digital converter (ADC) parameters and digital-to-analog converter (DAC) parameters, the ADC and DAC connected to the FPGA are configured to obtain the configured ADC and DAC. The configured ADC is used to convert the analog first response signal generated by the system under test in response to the excitation signal into a digital first response signal. The configured DAC is used to convert the digital excitation signal into an analog excitation signal.

[0015] In one possible implementation, the system also includes an output drive filter circuit and a front-end preprocessing circuit;

[0016] The output drive filter circuit is used to filter the analog excitation signal to obtain the filtered excitation signal.

[0017] The front-end preprocessing circuit is used to preprocess the analog first response signal generated in response to the filtered excitation signal to obtain the preprocessed first response signal.

[0018] The configured analog-to-digital converter is used to convert the preprocessed first response signal into a digitized first response signal.

[0019] In one possible implementation, when the target mode is the first mode, the parameter information includes a preset frequency, and the FPGA is specifically used for:

[0020] Based on the preset frequency in the parameter information, an excitation signal with the preset frequency is generated; based on the preset frequency in the parameter information, a reference signal with the preset frequency is generated.

[0021] In one possible implementation, when the target mode is the second mode, the parameter information includes:

[0022] Preset frequency, the rate of change corresponding to the preset frequency, and the range of change;

[0023] The FPGA is specifically used for:

[0024] Based on the preset frequency in the parameter information, and the corresponding rate of change and range of change of the preset frequency, an excitation signal is generated with the preset frequency as its frequency and changing at the rate of change of change within the range of change of the preset frequency; based on the preset frequency in the parameter information, and the corresponding rate of change and range of change of the preset frequency, a reference signal is generated with the preset frequency as its frequency and changing at the rate of change of change of change of change of change within the range of change of the preset frequency.

[0025] In one possible implementation, when the target mode is the third mode, the parameter information includes a preset frequency and parameters of the proportional-integral-derivative (PID) controller. The parameters of the PID controller are used to configure the PID controller in the FPGA to obtain a configured PID controller. Specifically, the FPGA is used for:

[0026] Based on the preset frequency in the parameter information, an excitation signal with the preset frequency and a reference signal with the preset frequency are generated;

[0027] Based on a reference signal with the preset frequency, the first response signal generated by the system under test responding to the excitation signal with the preset frequency is subjected to phase-locked amplification to obtain a second response signal.

[0028] Based on the configured proportional-integral-derivative (PID) controller, the second response signal is compared with the set value provided by the configured PID controller to obtain a first error between the second response signal and the set value;

[0029] Based on the first error, a correction signal is generated;

[0030] The excitation signal is adjusted based on the correction signal to generate an adjusted excitation signal;

[0031] The third response signal generated by the system under test in response to the adjusted excitation signal is subjected to phase-locked amplification to obtain the fourth response signal;

[0032] The fourth response signal is sent to the ARM processor.

[0033] In one possible implementation, the ARM processor is also used to drive at least one of wired and wireless communication via a communication port.

[0034] In one possible implementation, the ARM processor is also used to write or read data from memory.

[0035] Second aspect: This application provides a signal detection method, including:

[0036] Based on the mode information matching the system under test (SUT) and the parameter information matching the SUT, an excitation signal for the SUT is generated. The mode information instructs the FPGA to operate in a target mode matching the SUT. The target mode is used to generate the excitation signal matching the SUT. The parameter information is used to indicate the parameters required to generate the excitation signal for the SUT.

[0037] Compared with the prior art, this application has the following beneficial effects:

[0038] This application provides a signal detection system and method. An ARM processor can send mode information and parameter information matching the system under test (SUT) to an FPGA. The mode information instructs the FPGA to operate in a target mode matching the SUT, which generates an excitation signal matching the SUT. The parameter information indicates the parameters required to generate the excitation signal. Based on this, the FPGA can generate the excitation signal for the SUT according to the mode and parameter information. In this application, based on the ARM processor and FPGA, the ARM processor can configure the FPGA to operate in a target mode matching the SUT for different SUTs, generating an excitation signal matching the SUT. This makes the signal detection system applicable to SUTs in various application scenarios, effectively improving the versatility of the signal detection system. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a first signal detection system provided in an embodiment of this application;

[0040] Figure 2 A schematic diagram of a signal detection system in a precise locking mode provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of a second signal detection system provided in an embodiment of this application. Detailed Implementation

[0042] The terms "first," "second," and "third," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.

[0043] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first:

[0045] The Advanced Reduced Instruction Set Machine (ARM) processor is a 32-bit Reduced Instruction Set (RISC) processor that features small size, low power consumption, low cost, high performance, flexible and simple addressing modes, and high execution efficiency.

[0046] A Field Programmable Gate Array (FPGA) is a programmable logic device consisting of a large number of programmable logic units (PLUs) and programmable interconnect resources (PIRs). A PLU is a basic logic unit that can be programmed to implement various logic functions; PIRs are used to connect PLUs to form complex logic circuits.

[0047] Weak signal detection has wide applications and demands in cutting-edge physics research, geological exploration, chemical analysis, and medical instruments. The application scenarios for weak signal detection are diverse, and the measuring instruments and testing methods used also vary. Among them, correlation detection is an effective method for weak signal detection.

[0048] Taking correlation detection as an example, when performing correlation detection, an excitation signal needs to be applied to the system under test, and the response signal generated by the system under test based on the excitation signal is read and analyzed. This method can be used to measure weak signals in environments with extremely low signal-to-noise ratios.

[0049] However, the required excitation signal parameters for the system under test (SUT) vary across different application scenarios, and the corresponding processing methods for the response signals also differ. Currently, it is usually necessary to customize a specific signal detection system to send a matching excitation signal to the SUT in the corresponding application scenario and to detect the output response signal of the SUT. Because different application scenarios require customized signal detection systems, existing signal detection systems cannot be applied to all application scenarios, resulting in poor versatility.

[0050] Based on this, this application provides a signal detection system and method. An ARM processor can send mode information and parameter information matching the system under test (SUT) to an FPGA. The mode information instructs the FPGA to operate in a target mode matching the SUT, which is used to generate an excitation signal matching the SUT. The parameter information indicates the parameters required to generate the excitation signal. Based on this, the FPGA can generate the excitation signal for the SUT according to the mode and parameter information. In this application, based on the ARM processor and FPGA, the ARM processor can configure the FPGA accordingly for different SUTs, enabling it to operate in a target mode matching the SUT and generate an excitation signal matching the SUT. This makes the signal detection system applicable to SUTs in various application scenarios, effectively improving the versatility of the signal detection system.

[0051] The following is combined with Figures 1-3 This application provides a signal detection system, such as... Figure 1 As shown in the figure, this figure is a schematic diagram of the first signal detection system provided in the embodiment of this application.

[0052] The system comprises an integrated processing platform consisting of an ARM processor and an FPGA. The ARM processor can send mode information and parameter information matching the system under test to the FPGA.

[0053] The mode information is used to instruct the FPGA to operate in a target mode that matches the system under test, the target mode is used to generate an excitation signal that matches the system under test, and the parameter information is used to indicate the parameters required to generate the excitation signal for the system under test.

[0054] Specifically, the ARM processor may include a configuration module that can input mode information and parameter information matching the system under test to the FPGA, thereby enabling automated control of multiple operating modes.

[0055] For example, parameter information may include, but is not limited to, the channel parameters of the selected analog-to-digital converter (ADC) and analog-to-analog converter (DAC), compensation for ADC offset error, initialization parameters of peripheral chips such as ADC or DAC, parameters of the proportional-integral-derivative (PID) controller, and parameters such as the sampling rate and bandwidth of the response signal.

[0056] After receiving parameter and mode information from the ARM processor, the FPGA can generate an excitation signal that matches the system under test based on the parameter and mode information.

[0057] In one possible implementation, the system under test (SUT) responds to a first response signal generated by the excitation signal. The FPGA can generate a reference signal for the SUT based on the mode information and parameter information. Based on the reference signal, the first response signal is subjected to lock-in amplification to obtain a second response signal, which is then sent to the ARM processor so that the ARM processor can process the data from the second response signal.

[0058] Specifically, the excitation signal and reference signal can be generated by a waveform generation module in the FPGA. The waveform generation module sends the generated reference signal to a phase-locked loop (PLL) detection module in the FPGA. The PLL detection module can perform PLL amplification on the first response signal based on the reference signal to obtain a second response signal. The ARM processor may include a data processing module, which can be used to process the second response signal.

[0059] In one possible implementation, when the target mode is the first mode, the parameter information includes a preset frequency. The FPGA is specifically used to: generate an excitation signal with a preset frequency and a reference signal sent to the phase-locked loop detection module according to the preset frequency in the parameter information.

[0060] The first mode can be a phase-locked detection (PLD) mode. Specifically, the FPGA internally may include a PLD detection module and a waveform generation module. The waveform generation module can generate a signal of a specific frequency, that is, generate an excitation signal with the preset frequency according to the parameter information, which serves as the excitation signal for the system under test. The PLD detection module can extract the useful signal from the weak first response signal, that is, filter out the noise component in the first response signal to obtain the second response signal, thereby improving the signal-to-noise ratio. This allows the response of the system under test to the excitation signal of the specific frequency to be detected.

[0061] In one possible implementation, when the target mode is the second mode, the parameter information includes: a preset frequency, a rate of change corresponding to the preset frequency, and a range of change. The FPGA can generate an excitation signal with the preset frequency, varying within the range of change corresponding to the preset frequency at the specified rate of change, and a reference signal with the preset frequency, varying within the range of change corresponding to the preset frequency at the specified rate of change, based on the preset frequency in the parameter information.

[0062] The second mode can be a fast scan mode. Specifically, similar to the phase-locked detection mode described above, the excitation signal generated by the waveform generation module in the FPGA is input to the system under test, and the first response signal is read back through the phase-locked detection module in the FPGA. Useful information is extracted using the phase-locked detection module to obtain the second response signal. The first response signal is then filtered out by the phase-locked detection module of the FPGA to obtain a second response signal with a higher signal-to-noise ratio.

[0063] Unlike the phase-locked loop (PLL) detection mode described above, the frequency of the excitation signal generated by the waveform generation module can be continuously varied within a range set by the ARM processor at a certain speed. This allows for the rapid measurement of the response curve of the response signal to excitation signals of different frequencies.

[0064] In one possible implementation, when the target mode is the third mode, the FPGA can compare the second response signal with the setpoint provided by the configured PID controller based on the PID controller to determine whether the second response signal is the expected response signal. The setpoint can represent the expected response signal.

[0065] Specifically, when the target mode is the third mode, this third mode can be a precise locking mode. The parameter information includes a preset frequency and parameters of the proportional-integral-derivative (PID) controller. The parameters of the PID controller are used to configure the PID controller in the FPGA to obtain the configured PID controller. The FPGA can generate an excitation signal and a reference signal with the preset frequency according to the preset frequency in the parameter information. Based on the reference signal with the preset frequency, a first response signal is generated by the system under test in response to the excitation signal with the preset frequency. The system performs phase-locked amplification to obtain a second response signal; based on the configured proportional-integral-derivative (PID) controller, it compares the second response signal with the set value provided by the configured PID controller to obtain a first error between the second response signal and the set value; based on the first error, it generates a correction signal, adjusts the excitation signal based on the correction signal, and generates an adjusted excitation signal; it performs phase-locked amplification on the third response signal generated by the system under test in response to the adjusted excitation signal to obtain a fourth response signal; and it sends the fourth response signal to the ARM processor so that the ARM processor can process the data of the fourth response signal.

[0066] like Figure 2As shown in the figure, this is a schematic diagram of a signal detection system in a precise locking mode provided by an embodiment of this application. When it is required to lock onto and follow the response signal of the system under test to obtain information about the input and output signals at a specific point, the phase-locked detection module receives a reference signal generated by the waveform generation module and performs phase-locked amplification processing on the first response signal based on the reference signal to obtain a second response signal. The second response signal is then input to the PID controller in the FPGA.

[0067] The PID controller can obtain a correction signal by comparing the first error between the second response signal and the setpoint provided by the configured PID controller, and performing proportional-integral-derivative (PI) operations. The waveform generation module adjusts the excitation signal based on this correction signal to obtain an adjusted excitation signal. Thus, the system under test can generate a third response signal in response to the adjusted excitation signal. The phase-locked loop (PLL) detection module in the FPGA performs PLL amplification on this third response signal to obtain a fourth response signal, which is then sent to the ARM processor for data processing.

[0068] For example, the fourth response signal is input to the PID controller. If an error still exists between the fourth response signal and the set value, the PID controller can continue to send a corresponding correction signal to the waveform generation module based on the error between the fourth response signal and the set value to correct the adjusted excitation signal until the expected response signal is obtained. In this way, the system under test can be locked in a specified state, and a precise measurement result at that point can be obtained.

[0069] In one possible implementation, the parameter information is further used to indicate the analog-to-digital converter (ADC) parameters and the digital-to-analog converter (DAC) parameters. The FPGA can configure the ADC and DAC connected to the FPGA according to the ADC and DAC parameters to obtain the configured ADC and DAC. In this application, the relevant parameters of the DAC and ADC can be configured through the peripheral chip configuration module in the FPGA.

[0070] The configured analog-to-digital converter is used to convert the analog first response signal generated by the system under test in response to the excitation signal into a digital first response signal, and the configured digital-to-analog converter is used to convert the digital excitation signal into an analog excitation signal.

[0071] In one possible implementation, the system further includes an output drive filter circuit and a front-end preprocessing circuit. The output drive filter circuit can be used to filter the analog excitation signal to obtain a filtered excitation signal. The front-end preprocessing circuit can preprocess the analog first response signal generated in response to the filtered excitation signal to obtain a preprocessed first response signal. A configured analog-to-digital converter is used to convert the preprocessed first response signal into a digital first response signal.

[0072] Specifically, such as Figure 3 As shown, this figure is a schematic diagram of a second signal detection system provided in an embodiment of this application. Unlike the embodiments described above, the waveform generation module can input the digitized excitation signal into a DAC for digital-to-analog conversion to obtain an analog excitation signal. Based on this, the analog excitation signal output from the DAC can be filtered and amplified by an output driving circuit to meet the usage requirements of the system under test before being input into the system under test.

[0073] The system under test outputs an analog first response signal. This analog first response signal can be preprocessed by a front-end preprocessing circuit. For example, the front-end preprocessing circuit can perform pre-amplification and filtering on the analog first response signal. The preprocessed analog first response signal is then input to an ADC for analog-to-digital conversion to obtain a digitized first response signal. The phase-locked loop detection module in the FPGA performs phase-locked loop amplification on the digitized first response signal to obtain a second response signal.

[0074] In one possible implementation, the ARM processor can drive at least one of wired and wireless communication via a communication port, enabling it to write and read data from the peripheral memory.

[0075] Specifically, such as Figure 3 As shown, the ARM processor also includes a storage and communication port module. This module can interact with the configuration module, write and read data from the external memory, and drive wired and wireless communication. The memory can be used to store processed data. Wired and wireless communication enable the signal detection system to interact with a host computer or central control board.

[0076] In summary, this application provides a signal detection system in which an ARM processor can send mode information and parameter information matching the system under test (SUT) to an FPGA. The mode information instructs the FPGA to operate in a target mode matching the SUT, which is used to generate an excitation signal matching the SUT. The parameter information indicates the parameters required to generate the excitation signal. Based on this, the FPGA can generate the excitation signal for the SUT according to the mode and parameter information. In this application, based on the ARM processor and FPGA, the ARM processor can configure the FPGA accordingly for different SUTs, enabling it to operate in a target mode matching the SUT and generate an excitation signal matching the SUT. This makes the signal detection system applicable to SUTs in various application scenarios, effectively improving its versatility.

[0077] Second aspect: This application provides a signal detection method, including:

[0078] Based on the mode information matching the system under test (SUT) and the parameter information matching the SUT, an excitation signal for the SUT is generated. The mode information instructs the FPGA to operate in a target mode matching the SUT. The target mode is used to generate the excitation signal matching the SUT. The parameter information is used to indicate the parameters required to generate the excitation signal for the SUT.

[0079] In one possible implementation, the method further includes: generating a reference signal for the system under test based on the mode information and parameter information; performing phase-locked amplification on a first response signal generated by the system under test in response to the excitation signal based on the reference signal to obtain a second response signal, and sending the second response signal to the ARM processor; so that the ARM processor performs data processing on the second response signal.

[0080] In one possible implementation, the parameter information is further used to indicate analog-to-digital converter parameters and digital-to-analog converter parameters, and the method further includes:

[0081] Based on the analog-to-digital converter (ADC) parameters and digital-to-analog converter (DAC) parameters, the ADC and DAC connected to the FPGA are configured to obtain the configured ADC and DAC. The configured ADC is used to convert the analog first response signal generated by the system under test in response to the excitation signal into a digital first response signal. The configured DAC is used to convert the digital excitation signal into an analog excitation signal.

[0082] In one possible implementation, the method further includes:

[0083] The analog excitation signal is filtered to obtain a filtered excitation signal; the analog first response signal generated in response to the filtered excitation signal is preprocessed to obtain a preprocessed first response signal; the configured analog-to-digital converter is used to convert the preprocessed first response signal into a digital first response signal.

[0084] In one possible implementation, when the target mode is a first mode, the parameter information includes a preset frequency, and the step of generating an excitation signal for the system under test based on mode information matching the system under test and parameter information matching the system under test includes:

[0085] Based on the preset frequency in the parameter information, an excitation signal with the preset frequency is generated;

[0086] The step of generating a reference signal for the system under test based on the mode information and parameter information includes: generating a reference signal with a preset frequency based on a preset frequency in the parameter information.

[0087] In one possible implementation, when the target mode is the second mode, the parameter information includes:

[0088] Preset frequency, the rate of change corresponding to the preset frequency, and the range of change;

[0089] The step of generating an excitation signal for the system under test based on mode information matching the system under test and parameter information matching the system under test includes:

[0090] Based on the preset frequency in the parameter information, as well as the rate of change and range of change corresponding to the preset frequency, an excitation signal is generated with the preset frequency as the preset frequency and changes according to the rate of change corresponding to the preset frequency within the range of change corresponding to the preset frequency.

[0091] The step of generating a reference signal for the system under test based on the mode information and parameter information includes: generating a reference signal with the preset frequency as its frequency and changing at the speed of change corresponding to the preset frequency within the changing range corresponding to the preset frequency, based on the preset frequency in the parameter information, and the changing speed and changing range corresponding to the preset frequency.

[0092] In one possible implementation, when the target mode is the third mode, the parameter information includes a preset frequency and parameters of the proportional-integral-derivative (PID) controller. The parameters of the PID controller are used to configure the PID controller in the FPGA to obtain the configured PID controller. The step of generating the excitation signal for the system under test based on the mode information matching the system under test and the parameter information matching the system under test includes:

[0093] Based on the preset frequency in the parameter information, an excitation signal with the preset frequency and a reference signal with the preset frequency are generated;

[0094] The method further includes: based on a reference signal with the frequency of the preset frequency, performing phase-locked amplification on a first response signal generated by the system under test responding to an excitation signal with the frequency of the preset frequency to obtain a second response signal;

[0095] Based on the configured proportional-integral-derivative (PID) controller, the second response signal is compared with the set value provided by the configured PID controller to obtain the first error between the second response signal and the set value;

[0096] Based on the first error, a correction signal is generated;

[0097] The excitation signal is adjusted based on the correction signal to generate an adjusted excitation signal;

[0098] The third response signal generated by the system under test in response to the adjusted excitation signal is subjected to phase-locked amplification to obtain the fourth response signal;

[0099] The fourth response signal is sent to the ARM processor.

[0100] In summary, the method provided in this application, based on an ARM processor and an FPGA, can be configured by the ARM processor to operate in a target mode that matches the system under test for different systems under test, thereby generating an excitation signal that matches the system under test. This makes the signal detection system applicable to systems under test in various application scenarios, effectively improving the versatility of the signal detection system.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal detection system, characterized in that, This includes: Field Programmable Gate Arrays (FPGAs) and Advanced Reduced Instruction Set Machine (ARM) processors; The ARM processor is used to send mode information matching the system under test and parameter information matching the system under test to the FPGA. The mode information instructs the FPGA to operate in a target mode matching the system under test. The target mode is used to generate an excitation signal matching the system under test. The parameter information is used to indicate the parameters required to generate the excitation signal of the system under test. The FPGA is used to generate the excitation signal of the system under test based on the mode information and parameter information. When the target mode is the first mode, the parameter information includes a preset frequency, and the FPGA is specifically used for: Based on the preset frequency in the parameter information, an excitation signal with the preset frequency is generated; based on the preset frequency in the parameter information, a reference signal with the preset frequency is generated. When the target mode is the second mode, the parameter information includes: Preset frequency, the rate of change corresponding to the preset frequency, and the range of change; The FPGA is specifically used for: Based on the preset frequency in the parameter information, and the change rate and change range corresponding to the preset frequency, an excitation signal with the preset frequency as its frequency and changing at the change rate corresponding to the preset frequency within the change range corresponding to the preset frequency is generated; based on the preset frequency in the parameter information, and the change rate and change range corresponding to the preset frequency, a reference signal with the preset frequency as its frequency and changing at the change rate corresponding to the preset frequency within the change range corresponding to the preset frequency is generated. When the target mode is the third mode, the parameter information includes a preset frequency and parameters of the proportional-integral-derivative (PID) controller. The parameters of the PID controller are used to configure the PID controller in the FPGA to obtain the configured PID controller. Specifically, the FPGA is used for: Based on the preset frequency in the parameter information, an excitation signal with the preset frequency and a reference signal with the preset frequency are generated; Based on a reference signal with the preset frequency, the first response signal generated by the system under test responding to the excitation signal with the preset frequency is subjected to phase-locked amplification to obtain a second response signal. Based on the configured proportional-integral-derivative (PID) controller, the second response signal is compared with the set value provided by the configured PID controller to obtain a first error between the second response signal and the set value; Based on the first error, a correction signal is generated; The excitation signal is adjusted based on the correction signal to generate an adjusted excitation signal; The third response signal generated by the system under test in response to the adjusted excitation signal is subjected to phase-locked amplification to obtain the fourth response signal; The fourth response signal is sent to the ARM processor.

2. The system according to claim 1, characterized in that, The FPGA is also used for: Based on the mode information and parameter information, a reference signal for the system under test is generated; based on the reference signal, the first response signal generated by the system under test in response to the excitation signal is subjected to phase-locked amplification to obtain a second response signal, and the second response signal is sent to the ARM processor; The ARM processor is also used to process the second response signal.

3. The system according to claim 2, characterized in that, The parameter information is also used to indicate analog-to-digital converter parameters and digital-to-analog converter parameters; the FPGA is further used for: Based on the analog-to-digital converter (ADC) parameters and digital-to-analog converter (DAC) parameters, the ADC and DAC connected to the FPGA are configured to obtain the configured ADC and DAC. The configured ADC is used to convert the analog first response signal generated by the system under test in response to the excitation signal into a digital first response signal. The configured DAC is used to convert the digital excitation signal into an analog excitation signal.

4. The system according to claim 3, characterized in that, The system also includes an output drive filter circuit and a front-end preprocessing circuit; The output drive filter circuit is used to filter the analog excitation signal to obtain the filtered excitation signal. The front-end preprocessing circuit is used to preprocess the analog first response signal generated in response to the filtered excitation signal to obtain the preprocessed first response signal. The configured analog-to-digital converter is used to convert the preprocessed first response signal into a digitized first response signal.

5. The system according to any one of claims 1-4, characterized in that, The ARM processor is also used to drive at least one of wired communication and wireless communication via a communication port.

6. The system according to any one of claims 1-4, characterized in that, The ARM processor is also used to write or read data from the memory.

7. A signal detection method, characterized in that, The method is used to implement the signal detection system according to any one of claims 1-6, the method comprising: Based on the mode information matching the system under test (SUT) and the parameter information matching the SUT, an excitation signal for the SUT is generated. The mode information instructs the FPGA to operate in a target mode matching the SUT. The target mode is used to generate the excitation signal matching the SUT. The parameter information is used to indicate the parameters required to generate the excitation signal for the SUT.

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