Chip comparison test apparatus and method

Abstract

The application provides a chip comparison test device and method, and belongs to the technical field of chip testing. The device comprises: an upper computer unit for sending a test instruction to a lower computer unit; the lower computer unit is used for sending a test signal to a replaceable module through a connector unit in response to the test instruction; the connector unit is used for plugging connection between the lower computer unit and the replaceable module; the replaceable module is connected with the lower computer unit through the connector unit and connected with an oscilloscope unit; the replaceable module is a unit where a measured chip is located; the measured chip comprises a measured main chip and a measured substitute chip; the oscilloscope unit is used for acquiring a test waveform corresponding to the measured chip and sending the test waveform to the upper computer unit; and the upper computer unit is further used for comparison analysis on the test waveform and output of a comparison analysis result. The application can improve the test efficiency of the substitute chip, shorten the test period and reduce the test cost.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip comparison testing apparatus and method. Background Technology

[0002] To ensure the normal supply of electronic devices such as switches and servers after mass production, it is usually necessary to perform replacement chip matching and testing on the electronic chips and structural components used in the electronic devices during the design phase. This is so that when there are problems with the supply of the main chip, the replacement chip can be switched to in time to ensure the normal supply of electronic devices.

[0003] Currently, the testing and verification of alternative chips usually adopts the alternative chip board verification method. That is, for the replaceable chips in each board of the equipment, the alternative chips are replaced in the factory production and printed circuit board assembly (PCBA) production. After the PCBA is produced, signal testing and other verifications are performed. This increases the PCBA production cost and extends the testing cycle of the alternative chips.

[0004] Therefore, there is an urgent need for a simple and effective chip comparison test method to meet the demand for rapid testing and verification of alternative chips. Summary of the Invention

[0005] This invention provides a chip comparison testing apparatus and method to address the shortcomings of existing technologies in testing and verifying alternative chips.

[0006] In a first aspect, the present invention provides a chip comparison testing apparatus, comprising:

[0007] The system comprises a host computer unit, a slave computer unit, a connector unit, a replaceable module, an oscilloscope unit, and a power supply unit.

[0008] The host computer unit is connected to the slave computer unit and the oscilloscope unit respectively, and is used to send test commands to the slave computer unit;

[0009] The lower-level unit is connected to the upper-level unit and the connector unit respectively, and is used to receive the test command and, in response to the test command, send a test signal to the replaceable module through the connector unit.

[0010] The connector unit is connected to the lower-level machine unit and the replaceable module respectively, and is used for plug-in connection between the lower-level machine unit and the replaceable module;

[0011] The replaceable module is connected to the lower-level unit via a connector unit, and the replaceable module is also connected to the oscilloscope unit. The replaceable module is the unit where the chip under test is located, wherein the chip under test includes the main chip under test and the replacement chip under test.

[0012] The oscilloscope unit is used to acquire the test waveform corresponding to the chip under test and send the test waveform to the host computer unit; the host computer unit is also used to acquire the test waveform output by the oscilloscope unit, perform comparative analysis on the test waveform, and output the comparative analysis results of the main chip under test and the replacement chip under test.

[0013] The power supply unit is connected to the lower-level machine unit and the replaceable module respectively, and is used to supply power to the lower-level machine unit and the replaceable module.

[0014] According to a chip comparison testing device provided by the present invention, the replaceable module includes at least one type of socket for fixing the chip under test. Within the same replaceable module, the socket types corresponding to the main chip under test and the replacement chip under test are the same.

[0015] According to the chip comparison testing device provided by the present invention, the host computer unit includes: an input module, a control module, and a data analysis module.

[0016] The input module is used to acquire the operation instructions determined by the operator based on the type of the chip under test.

[0017] The control module is used to convert the operation instructions into corresponding test instructions and waveform acquisition instructions. The test instructions are sent to the lower-level machine unit through a serial interface, and the waveform acquisition instructions are sent to the oscilloscope unit through a network interface.

[0018] The control module is also used to acquire test data from the lower-level unit through the serial interface, and to acquire test waveforms from the oscilloscope unit through the network interface;

[0019] The data analysis module is used to compare and analyze the test waveforms and output the comparison and analysis results.

[0020] According to a chip comparison testing device provided by the present invention, the test instructions are used to instruct signal testing and / or functional testing.

[0021] According to a chip comparison testing device provided by the present invention, when the test instruction is used to instruct signal testing, the host computer unit is further used to receive signal test judgment criteria, and the slave computer unit is further used to configure some general-purpose input / output pins of the slave computer unit as I / O output ports.

[0022] The host computer unit is also used to acquire the test waveforms output by the oscilloscope unit, perform comparative analysis on the test waveforms, and output the comparative analysis results of the tested main chip and the tested replacement chip, including:

[0023] The host computer unit acquires the test waveform of the main chip under test and the test waveform of the replacement chip under test.

[0024] The host computer unit determines the difference in test waveforms between the main chip under test and the replacement chip under test;

[0025] The host computer unit compares the test waveform difference between the main chip under test and the replacement chip under test with the signal test judgment standard to obtain the comparison analysis results of the main chip under test and the replacement chip under test.

[0026] The host computer unit outputs the comparison analysis results.

[0027] According to a chip comparison testing apparatus provided by the present invention, when the test instruction is used to instruct functional testing,

[0028] The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit.

[0029] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

[0030] According to the chip comparison testing apparatus provided by the present invention, when the test instruction is used to instruct signal testing and functional testing,

[0031] The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit.

[0032] The oscilloscope unit is also used to acquire test waveforms during the data interaction process between the lower-level unit and the chip under test.

[0033] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

[0034] The host computer unit is also used to analyze the test waveforms during the data interaction between the slave computer unit and the chip under test, and output the signal test results of the main chip under test and the replacement chip under test.

[0035] According to a chip comparison testing device provided by the present invention, the power supply unit includes multiple voltage adjustment units. By adjusting the output of different voltage adjustment units, the lower-level unit is also used to perform voltage bias test on the chip under test.

[0036] In a second aspect, the present invention also provides a chip comparison testing method, based on the chip comparison testing apparatus as described in the first aspect, comprising:

[0037] The host computer unit sends test commands to the slave computer unit;

[0038] The lower-level unit receives the test command and, in response to the test command, sends a test signal to the chip under test in the replaceable module through the connector unit;

[0039] The oscilloscope unit acquires the test waveform corresponding to the chip under test and sends the test waveform to the host computer unit;

[0040] The host computer unit performs comparative analysis on the test waveforms and outputs the comparative analysis results.

[0041] Thirdly, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip comparison test method as described in the second aspect.

[0042] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the chip comparison test method as described in the second aspect.

[0043] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the chip comparison test method as described in the second aspect.

[0044] The chip comparison testing apparatus and method provided by this invention send test commands to a lower-level computer unit via a host computer unit; the lower-level computer unit sends test signals to a replaceable module, which includes the main chip under test and a replacement chip under test; the replaceable module and connector unit are configured to be plugged and plugged into the lower-level computer unit; the test waveform corresponding to the chip under test is acquired by an oscilloscope unit and sent to the host computer unit; the host computer unit performs comparative analysis on the test waveforms and outputs the comparative analysis results. This method can realize comparative testing of the main chip under test and the replacement chip under test, and can be used for comparative testing of chips with different packages and types. It has a wide range of applications, can automatically capture test waveforms, and automatically compare test data, saving test time and avoiding the problems of misjudgment / omission by manual inspection. It can automatically realize functional testing, stress testing, and test result judgment of the main replacement chip, improve the testing efficiency of the replacement chip, and effectively reduce the testing cost and test cycle. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the chip comparison testing device provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device under a signal testing scenario, provided in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device under a functional testing scenario, provided in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device under signal testing and functional testing scenarios provided in an embodiment of the present invention.

[0050] Figure 5 This is one of the flowcharts illustrating the chip comparison testing method provided in an embodiment of the present invention;

[0051] Figure 6 The second schematic flowchart of the chip comparison test method provided in the embodiment of the present invention;

[0052] Figure 7 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention;

[0053] Figure label:

[0054] 101: Host computer unit; 102: Subordinate computer unit; 103: Connector unit;

[0055] 104: Replaceable module; 105: Oscilloscope unit; 106: Power supply unit. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0057] Figure 1 This is a schematic diagram of the chip comparison testing device provided in an embodiment of the present invention. Figure 1 As shown, the chip comparison testing device includes: a host computer unit 101, a slave computer unit 102, a connector unit 103, a replaceable module 104, an oscilloscope unit 105, and a power supply unit 106.

[0058] The host computer unit 101 is connected to the slave computer unit 102 and the oscilloscope unit 105 respectively, and is used to send test commands to the slave computer unit 102.

[0059] Optionally, the host computer unit 101 sends test commands to the slave computer unit 102 via a serial interface. For example, the host computer unit 101 sends test commands to the slave computer unit 102 via a Universal Asynchronous Receiver / Transmitter (UART).

[0060] Optionally, the test command is used to instruct signal testing and / or functional testing. Optionally, the test command also carries test parameters, such as signal frequency, register read / write, data read / write, number of read / write operations, duty cycle, etc.

[0061] Signal testing primarily focuses on the quality of signals in a circuit system. If a signal can be transmitted from the source to the receiver without distortion within a specified time, the signal is considered intact. The main goal of this testing is to ensure signal fidelity during transmission. Specifically, signal testing can include multiple steps, such as waveform testing, signal transmission speed testing, clock signal testing, signal loss testing, and reflection testing. Among these, waveform testing is the most basic method, typically performed using an oscilloscope, and mainly tests the waveform's amplitude, glitches, and edges. By testing the waveform's characteristics, it's possible to analyze whether parameters such as rise time, high and low levels, rising edge, falling edge, frequency, and duty cycle meet the requirements.

[0062] Functional testing is a systematic check of a chip's various functional specifications. Its goal is to verify whether the chip's parameters, specifications, and functions meet the design requirements. Functional testing typically involves two steps: first, connecting the pins of the chip under test (DUT) to the functional modules of a lower-level computer; and second, applying input signals to the DUT through the lower-level computer and detecting the DUT's output signals to determine whether the DUT's functions and performance meet the design requirements.

[0063] That is, the host computer unit can instruct the slave computer unit to perform signal testing on the chip under test, or to perform functional testing on the chip under test, or to perform both signal testing and functional testing on the chip under test.

[0064] Optionally, the content to be tested for the chip under test can be determined according to the type of the chip under test.

[0065] For example, if the chip under test is a switch-type chip, then a signal test is performed on the chip under test.

[0066] If the chip under test is a functional chip, then perform functional testing on the chip under test, or perform signal testing and functional testing on the chip under test.

[0067] Here, a switch-type chip refers to a chip that plays a role in the conversion, distribution, detection, and other power management functions of electrical energy in an electronic device system.

[0068] Functional chips refer to chips with specific functions. Computers contain various functional chips, including but not limited to computing chips, memory chips, and sensing chips. Computing chips, such as CPUs, GPUs, FPGAs, and MCUs, are used for computation and analysis. Memory chips, such as DRAM, SDRAM, ROM, NAND, and FLASH, are primarily used for data storage. Sensing chips, such as microphones and cameras, are used to receive and process signals from the external environment.

[0069] Optionally, the specific content of the test for the chip under test can be determined based on the type of chip under test, its on-chip resources, and application requirements. Here, on-chip resources include storage resources, system resources, and on-chip peripheral resources. Application requirements are determined based on the application scenario of the chip under test.

[0070] In practical applications, the host computer unit 101 also sends a waveform acquisition command to the oscilloscope unit 105 so that the oscilloscope unit can start acquiring the test waveform corresponding to the chip under test.

[0071] Specifically, the host computer unit 101 sends waveform acquisition commands to the oscilloscope unit 105 via a network interface. For example, the host computer unit 101 sends waveform acquisition commands to the oscilloscope unit 105 via an Ethernet interface (ETH).

[0072] The lower-level machine unit 102 is connected to the upper-level machine unit 101 and the connector unit 103 respectively, and is used to receive the test command and, in response to the test command, send a test signal to the replaceable module 104 through the connector unit 103.

[0073] In practical applications, the lower-level unit 102 receives the test command and can obtain the test content for the chip under test by parsing the test command.

[0074] If the test command instructs to perform a signal test, the lower-level unit will perform a signal test on the chip under test.

[0075] If the test command instructs to perform a functional test, the lower-level unit will perform a functional test on the chip under test.

[0076] If the test command instructs to perform signal testing and functional testing, the lower-level unit will perform signal testing and functional testing on the chip under test.

[0077] The lower-level unit 102 sends test signals to the replaceable module 104 through the connector unit 103 to perform signal testing and / or functional testing on the chip under test.

[0078] Specifically, the lower-level unit 102 can be any CPLD control chip that meets the requirements, such as LCMXO3LF-4300C-5BG256I. The lower-level unit is used to execute test instructions from the upper-level unit, and can also be used to transmit test results to the upper-level unit through a serial interface.

[0079] The connector unit 103 is connected to the lower-level machine unit 102 and the replaceable module 104 respectively, and is used for plug-in connection between the lower-level machine unit 102 and the replaceable module 104.

[0080] The connector unit can be any type of board-end connector that meets the requirements.

[0081] The replaceable module 104 is connected to the lower-level unit 102 via the connector unit 103. The replaceable module 104 is also connected to the oscilloscope unit 105. The replaceable module 104 is the unit where the chip under test is located. The chip under test includes the main chip under test and the replacement chip under test.

[0082] The replaceable module is the unit containing the chip under test, and the replaceable unit is also a circuit board with different types of sockets. It should be noted that by replacing the replaceable module, chips with different packages can be tested.

[0083] The socket types of the two chips under test in the same replaceable module are the same. The same replaceable module includes two chips under test, one is the main chip under test and the other is the backup chip under test.

[0084] Different modules can use different types of sockets for the chip under test, such as SOP-8, SOP-16, TSSOP-8, TSSOP-16, etc., which are different IC package types. This allows for the testing of chips with different packages.

[0085] The chip under test (DUT) within the replaceable module can be not only I / O input / output type chips and I2C interface chips, but also other interface type chips, such as SPI interface chips and LPC interface chips. Except for I / O input / output type chips, the functional testing procedure for other bus interface chips is the same as that for I2C interfaces.

[0086] The oscilloscope unit 105 is used to acquire the test waveform corresponding to the chip under test and send the test waveform to the host computer unit 101.

[0087] Specifically, the oscilloscope unit 105 can be any type of digital oscilloscope with network protocol functionality, such as the MXR054A oscilloscope.

[0088] The host computer unit 101 is also used to acquire the test waveform output by the oscilloscope unit 105, perform comparative analysis on the test waveform, and output the comparative analysis results of the tested main chip and the tested replacement chip.

[0089] The power supply unit 106 is connected to the lower-level machine unit 102 and the replaceable module 104 respectively, and is used to supply power to the lower-level machine unit 102 and the replaceable module 104.

[0090] Specifically, the power supply unit can be any DC / DC voltage regulator chip that supports output voltage adjustment.

[0091] The chip comparison testing device provided by this invention sends test commands to a lower-level computer unit via a host computer unit; the lower-level computer unit sends test signals to a replaceable module, which includes the main chip under test and a replacement chip under test; the replaceable module and connector unit are configured to be plugged and plugged into the lower-level computer unit; the test waveform corresponding to the chip under test is acquired by an oscilloscope unit and sent to the host computer unit; the host computer unit performs comparative analysis on the test waveforms and outputs the comparative analysis results. This device can perform comparative testing of the main chip under test and the replacement chip under test, and can be used for comparative testing of chips with different packages and types. It has a wide range of applications, can automatically capture test waveforms, and automatically compare test data, saving testing time and avoiding the problems of misjudgment / omission during manual inspection. It can automatically perform functional testing, stress testing, and test result judgment of the main replacement chip, improving the testing efficiency of the replacement chip and effectively reducing testing costs and testing cycle.

[0092] In some embodiments, the replaceable module 104 includes at least one type of socket for securing the chip under test. Within the same replaceable module, the socket types corresponding to the main chip under test and the replacement chip under test are the same.

[0093] Understandably, to achieve comparative testing of the main chip under test (DUT) and its replacement chip, the DUT and the replacement chip are inserted into the same type of socket to form a replaceable module. The lower-level computer unit sends test signals to the replaceable module, and the oscilloscope unit acquires the test waveform corresponding to the DUT in the replaceable module. This test waveform is then sent to the upper-level computer unit, which performs comparative analysis and outputs the results. This allows for comparative testing of the DUT and its replacement chip, improving testing efficiency, shortening the testing cycle, and reducing testing costs.

[0094] In some embodiments, the host computer unit includes: an input module, a control module, and a data analysis module.

[0095] The input module is used to acquire the operation instructions determined by the operator based on the type of the chip under test.

[0096] The control module is used to convert the operation instructions into corresponding test instructions and waveform acquisition instructions. The test instructions are sent to the lower-level machine unit through a serial interface, and the waveform acquisition instructions are sent to the oscilloscope unit through a network interface.

[0097] The control module is also used to acquire test data from the lower-level unit through the serial interface, and to acquire test waveforms from the oscilloscope unit through the network interface;

[0098] The data analysis module is used to compare and analyze the test waveforms and output the comparison and analysis results.

[0099] Optionally, the input module is used to obtain operation instructions determined by the operator based on the type of the chip under test.

[0100] For example, if the chip under test is a switch-type chip, the operation instruction is to perform a signal test on the chip under test.

[0101] If the chip under test is a functional chip, the operation instruction is to perform a functional test on the chip under test, or to perform a signal test and a functional test on the chip under test.

[0102] The input module is used to obtain the operation instructions determined by the operator based on the type of the chip under test, combined with the on-chip resources and application requirements of the chip under test.

[0103] The control module is used to convert the operation instructions into corresponding test instructions and waveform acquisition instructions. The test instructions are sent to the lower-level machine unit through a serial interface so that the lower-level machine unit can perform corresponding tests on the chip under test in accordance with the test instructions. The waveform acquisition instructions are sent to the oscilloscope unit through a network interface so that the oscilloscope unit can start acquiring the test waveform corresponding to the chip under test.

[0104] The data analysis module is used to compare and analyze the test waveforms and output the comparison and analysis results of the tested main chip and the tested replacement chip.

[0105] The chip comparison testing device provided by this invention allows the host computer unit to acquire operation instructions determined by the operator based on the type of the chip under test, convert the operation instructions into corresponding test instructions and waveform acquisition instructions, and send them to the slave computer unit and oscilloscope unit respectively. Test data is acquired from the slave computer unit, and test waveforms are acquired from the oscilloscope unit. The test waveforms are compared and analyzed, and the comparison and analysis results are output. This device enables comparative testing of the main chip under test and the replacement chip under test, improving the testing efficiency of the replacement chip, shortening the testing cycle, and reducing the testing cost.

[0106] In some embodiments, when the test instruction is used to instruct the signal test, the host computer unit is further configured to receive the signal test judgment criteria, and the slave computer unit is further configured to configure some of the general-purpose input / output pins of the slave computer unit as I / O output ports.

[0107] The host computer unit is also used to acquire the test waveforms output by the oscilloscope unit, perform comparative analysis on the test waveforms, and output the comparative analysis results of the tested main chip and the tested replacement chip, including:

[0108] The host computer unit acquires the test waveform of the main chip under test and the test waveform of the replacement chip under test.

[0109] The host computer unit determines the difference in test waveforms between the main chip under test and the replacement chip under test;

[0110] The host computer unit compares the test waveform difference between the main chip under test and the replacement chip under test with the signal test judgment standard to obtain the comparison analysis results of the main chip under test and the replacement chip under test.

[0111] The host computer unit outputs the comparison analysis results.

[0112] Figure 2 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device under a signal testing scenario, as provided in an embodiment of the present invention.

[0113] like Figure 2 As shown, the lower-level machine unit 102 configures some of the general-purpose input / output pins GPIOA, B, E, and F of the lower-level machine unit as I / O output ports OUT1, OUT2, OUT3, and OUT4, respectively.

[0114] The input terminal of the replaceable module 104 is connected to the I / O output port of the lower-level unit 102 through the connector unit 103, and the output terminal of the replaceable module 104 is connected to the oscilloscope unit 105, which acquires the output signal waveform of the chip under test.

[0115] The host computer unit 101 also receives signal test and judgment criteria, including rise time difference, high and low level difference, etc.

[0116] Furthermore, the host computer unit acquires the test waveform of the main chip under test and the test waveform of the replacement chip under test, determines the difference between the test waveforms of the main chip under test and the replacement chip under test, and compares the difference between the test waveforms of the main chip under test and the replacement chip under test with the signal test judgment standard to obtain the comparison analysis results of the main chip under test and the replacement chip under test.

[0117] For example, if the difference in the test waveforms is within the preset threshold range of the signal test judgment standard, the comparison analysis result indicates that the tested replacement chip has passed the test. If the difference in the test waveforms is not within the preset threshold range of the signal test judgment standard, the comparison analysis result indicates that the tested replacement chip has failed the test.

[0118] The chip comparison testing device provided by this invention, in a signal testing scenario, configures some general-purpose input / output pins as I / O output ports in the lower-level unit, and the upper-level unit receives the signal testing judgment standard, compares the test waveform difference between the main chip under test and the replacement chip under test with the signal testing judgment standard, and can realize the comparison test of the main chip under test and the replacement chip under test, thereby improving the testing efficiency of the replacement chip, shortening the testing cycle and reducing the testing cost.

[0119] In some embodiments, where the test instruction is used to instruct functional testing to be performed...

[0120] The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit.

[0121] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

[0122] Figure 3 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device under a functional testing scenario, as provided in an embodiment of the present invention.

[0123] like Figure 3 As shown, the lower-level machine unit 102 configures some of the general-purpose input / output pins GPIO A, B, E, and F of the lower-level machine unit as data or clock signal output ports SDA1, SCL1, SDA2, and SCL2, respectively.

[0124] The input terminal of the replaceable module 104 is connected to the data or clock signal output port of the lower-level unit 102 via the connector unit 103.

[0125] It should be noted that in functional testing scenarios, an oscilloscope unit may not be required. The lower-level unit 102 is also used to interact with the chip under test through the data or clock signal output port, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit;

[0126] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

[0127] The chip comparison testing device provided by this invention, in a functional testing scenario, configures some general-purpose input / output pins of the lower-level unit as data or clock signal output ports. The lower-level unit interacts with the chip under test through the data or clock signal output ports, records the test data of the main chip under test and the replacement chip under test, and sends the test data to the upper-level unit. This enables comparative testing of the main chip under test and the replacement chip under test, improving the testing efficiency of the replacement chip, shortening the testing cycle, and reducing the testing cost.

[0128] In some embodiments, where the test instructions are used to instruct signal testing and functional testing to be performed...

[0129] The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit.

[0130] The oscilloscope unit is also used to acquire test waveforms during the data interaction process between the lower-level unit and the chip under test.

[0131] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

[0132] The host computer unit is also used to analyze the test waveforms during the data interaction between the slave computer unit and the chip under test, and output the signal test results of the main chip under test and the replacement chip under test.

[0133] Figure 4 This is a schematic diagram showing the connection relationship of each component in a chip comparison testing device for signal testing and functional testing scenarios provided in an embodiment of the present invention.

[0134] like Figure 4As shown, the lower-level machine unit 102 configures some of the general-purpose input / output pins GPIO A, B, E, and F of the lower-level machine unit as data or clock signal output ports SDA1, SCL1, SDA2, and SCL2, respectively.

[0135] The input terminal of the replaceable module 104 is connected to the data or clock signal output port of the lower-level unit 102 via the connector unit 103.

[0136] The oscilloscope unit 105 is connected to the data or clock signal output port and is used to acquire test waveforms during the data interaction process between the lower-level unit and the chip under test.

[0137] The lower-level unit 102 interacts with the chip under test through the data or clock signal output port, records the test data of the main chip under test and the replacement chip under test, and sends the test data to the upper-level unit.

[0138] The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test. The host computer unit is also used to analyze the test waveforms during the data interaction process between the slave computer unit and the chip under test, and output the signal test results of the main chip under test and the replacement chip under test.

[0139] The chip comparison testing device provided by this invention, in signal testing and functional testing scenarios, configures some general-purpose input / output pins of the lower-level unit as data or clock signal output ports. The lower-level unit interacts with the chip under test (DUT) through these data or clock signal output ports, records the test data of the DUT main chip and the DUT replacement chip, and sends the test data to the upper-level unit. An oscilloscope unit is connected to the data or clock signal output ports to acquire the test waveforms during the data interaction between the lower-level unit and the DUT. The upper-level unit queries the test data of the DUT main chip and the DUT replacement chip sent by the lower-level unit in real time, compares and analyzes the test data to obtain functional test comparison analysis results. The upper-level unit also analyzes the test waveforms during the data interaction between the lower-level unit and the DUT to obtain signal test results. This device enables comparative testing of the DUT main chip and the DUT replacement chip, improving the testing efficiency of the replacement chip, shortening the testing cycle, and reducing testing costs.

[0140] In some embodiments, the power supply unit includes multiple voltage regulation units. By adjusting the output of different voltage regulation units, the lower-level unit is also used to perform voltage bias test on the chip under test.

[0141] It is understood that the power supply unit can be any DC / DC voltage regulator chip that supports I2C-based output voltage adjustment. It can be divided into multiple voltage regulation units, each used to power the lower-level unit and the replaceable module. By individually modifying the output of different voltage regulation units, independent voltage bias testing of the chip under test (DUT) within the lower-level unit and the replaceable module can be performed. This allows for the determination of the DUT's operational stability under abnormal voltage conditions, achieving voltage stress testing of the DUT. It enables comparative testing of the main chip under test and its replacement chip, improving replacement chip testing efficiency, shortening the testing cycle, and reducing testing costs.

[0142] Figure 5 This is one of the flowcharts illustrating the chip comparison testing method provided in this embodiment of the invention, such as... Figure 5 As shown, the chip comparison test methods include:

[0143] Step 500: The host computer unit sends a test command to the slave computer unit;

[0144] Step 501: The lower-level unit receives the test command and, in response to the test command, sends a test signal to the chip under test in the replaceable module through the connector unit.

[0145] Step 502: The oscilloscope unit acquires the test waveform corresponding to the chip under test and sends the test waveform to the host computer unit;

[0146] Step 503: The host computer unit performs comparative analysis on the test waveform and outputs the comparative analysis results.

[0147] For an understanding of the chip comparison testing method provided in the embodiments of the present invention, please refer to the description in the aforementioned chip comparison testing device, which will not be repeated here.

[0148] Figure 6 This is the second flowchart illustrating the chip comparison testing method provided in this embodiment of the invention. Figure 6 The example given is an I2C interface chip, but this does not constitute a limitation of the invention. The functional testing procedures for other bus interface chips are the same as those for the I2C interface.

[0149] A chip comparison testing method, taking tested chips A1 / A2 (pins 1 / 2 are input pins, pins 5 / 6 are output pins) and B1 / B2 (pins 1 / 2 are I2C pins) as examples, such as... Figure 6 As shown, it includes:

[0150] (1) Select the appropriate replaceable module according to the type of chip being tested, power on after installation, and proceed to step (2);

[0151] (2) Is it necessary to bias the voltage of the chip under test? If yes, proceed to step (3); otherwise, proceed to step (5).

[0152] (3) Set the voltage value to be pulled to, and send the voltage value to be adjusted to the lower unit through the host computer unit, and proceed to step (4).

[0153] (4) The lower-level unit modifies the output voltage value of the power supply unit voltage regulator through the I2C interface (I2C0) and proceeds to step (5);

[0154] (5) Select the test content according to the type of chip under test. If signal testing is required (chip under test A1 / A2), proceed to step (6); if functional testing is required (chip under test B1 / B2), proceed to step (12).

[0155] (6) Configure signal test judgment criteria through the host computer unit, including rise time difference, high and low level difference, etc., and proceed to step (7);

[0156] (7) The lower-level machine unit GPIOA / B / E / F is configured as an I / O output port, and proceed to step (8);

[0157] (8) The host computer unit sends test instructions to the slave computer unit, including signal frequency, duty cycle, etc., and at the same time, sends waveform capture instructions to the oscilloscope unit so that the oscilloscope unit can start the test waveform capture and proceed to step (9).

[0158] (9) The lower-level machine unit GPIOA / B / E / F outputs test signals to pin 1 / 2 of the chip under test according to the test instructions, and proceeds to step (10);

[0159] (10) The oscilloscope unit captures the waveform output from pins 5 / 6 of the chip under test and transmits the test results to the host computer unit, then proceeds to step (11).

[0160] (11) The host computer unit compares the difference between the test waveform data of the chip under test and the test standard set in step (6) to determine whether the test passes or fails, and then proceeds to step (16).

[0161] (12) The host computer unit selects the test interface type as I2C, and the slave computer unit configures GPIOA / B / E / F as I2C SDA / SCL (data / clock) signals respectively, and proceeds to step (13);

[0162] (13) The host computer unit sends test instructions to the slave computer unit, including I2C frequency, read and write register, read and write data, read and write count, etc., and then proceeds to step (14);

[0163] (14) The lower-level unit interacts with the chip under test via GPIOA / B / E / F (I2C) and records the test results synchronously, and then proceeds to step (15).

[0164] (15) The host computer unit can query the current test results in real time through the serial interface, including the number of tests, the number of successful tests, the number of failed tests, etc., and then proceed to step (16);

[0165] (16) Is it over? If yes, proceed to step (17); otherwise, return to step (2).

[0166] (17) End.

[0167] The chip comparison testing method provided in this invention can be used for comparison testing of chips with different packages and types. It has a wide range of applications, can automatically capture test waveforms, and automatically compare test data, saving test time and avoiding the problems of misjudgment / omission by manual inspection. It can automatically realize the functional testing, stress testing and test result judgment of the main replacement chip, effectively reducing test costs and test cycle.

[0168] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0169] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7 As shown, the electronic device may include a processor 710, a communication interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 can call logic instructions in the memory 730 to execute a chip comparison test method, which includes: a host computer unit sending a test instruction to a slave computer unit; the slave computer unit receiving the test instruction and, in response to the test instruction, sending a test signal to the chip under test in the replaceable module through a connector unit; an oscilloscope unit acquiring the test waveform corresponding to the chip under test and sending the test waveform to the host computer unit; and the host computer unit performing comparative analysis on the test waveform and outputting the comparative analysis results.

[0170] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0171] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the chip comparison test method provided by the above methods. The method includes: a host computer unit sending a test command to a slave computer unit; the slave computer unit receiving the test command and, in response to the test command, sending a test signal to the chip under test in a replaceable module through a connector unit; an oscilloscope unit acquiring the test waveform corresponding to the chip under test and sending the test waveform to the host computer unit; and the host computer unit performing comparative analysis on the test waveform and outputting the comparative analysis result.

[0172] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the chip comparison test method provided by the above methods. The method includes: a host computer unit sending a test command to a slave computer unit; the slave computer unit receiving the test command and, in response to the test command, sending a test signal to the chip under test in a replaceable module through a connector unit; an oscilloscope unit acquiring a test waveform corresponding to the chip under test and sending the test waveform to the host computer unit; and the host computer unit performing comparative analysis on the test waveform and outputting the comparative analysis result.

[0173] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0174] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip-to-chip test apparatus, characterized by comprising: include: The system comprises a host computer unit, a slave computer unit, a connector unit, a replaceable module, an oscilloscope unit, and a power supply unit. The host computer unit is connected to the slave computer unit and the oscilloscope unit respectively, and is used to send test commands to the slave computer unit; The lower-level unit is connected to the upper-level unit and the connector unit respectively, and is used to receive the test command and, in response to the test command, send a test signal to the replaceable module through the connector unit. The connector unit is connected to the lower-level machine unit and the replaceable module respectively, and is used for plug-in connection between the lower-level machine unit and the replaceable module; The replaceable module is connected to the lower-level unit via a connector unit, and is also connected to the oscilloscope unit. The replaceable module is the unit where the chip under test is located, wherein the chip under test includes a main chip under test and a replacement chip under test. The replaceable module includes at least one type of socket for fixing the chip under test. Within the same replaceable module, the socket types corresponding to the main chip under test and the replacement chip under test are the same. The oscilloscope unit is used to acquire the test waveform corresponding to the chip under test and send the test waveform to the host computer unit; the host computer unit is also used to acquire the test waveform output by the oscilloscope unit, perform comparative analysis on the test waveform, and output the comparative analysis results of the main chip under test and the replacement chip under test. The power supply unit is connected to the lower-level machine unit and the replaceable module respectively, and is used to supply power to the lower-level machine unit and the replaceable module.

2. The chip comparison testing device according to claim 1, characterized in that, The host computer unit includes: an input module, a control module, and a data analysis module. The input module is used to acquire the operation instructions determined by the operator based on the type of the chip under test. The control module is used to convert the operation instructions into corresponding test instructions and waveform acquisition instructions. The test instructions are sent to the lower-level machine unit through a serial interface, and the waveform acquisition instructions are sent to the oscilloscope unit through a network interface. The control module is also used to acquire test data from the lower-level unit through the serial interface, and to acquire test waveforms from the oscilloscope unit through the network interface; The data analysis module is used to compare and analyze the test waveforms and output the comparison and analysis results.

3. The chip comparison testing device according to claim 2, characterized in that, The test instructions are used to instruct signal testing and / or functional testing to be performed.

4. The chip comparison testing device according to claim 3, characterized in that, When the test instruction is used to instruct the signal test, the host computer unit is also used to receive the signal test judgment criteria, and the slave computer unit is also used to configure some of the general-purpose input / output pins of the slave computer unit as I / O output ports. The host computer unit is also used to acquire the test waveforms output by the oscilloscope unit, perform comparative analysis on the test waveforms, and output the comparative analysis results of the tested main chip and the tested replacement chip, including: The host computer unit acquires the test waveform of the main chip under test and the test waveform of the replacement chip under test. The host computer unit determines the difference in test waveforms between the main chip under test and the replacement chip under test; The host computer unit compares the test waveform difference between the main chip under test and the replacement chip under test with the signal test judgment standard to obtain the comparison analysis results of the main chip under test and the replacement chip under test. The host computer unit outputs the comparison analysis results.

5. The chip comparison testing apparatus according to claim 3, characterized in that, When the test instruction is used to instruct functional testing to be performed. The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit. The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test.

6. The chip comparison testing apparatus according to claim 3, characterized in that, When the test instructions are used to instruct signal testing and functional testing to be performed. The lower-level unit is also used to configure some of its general-purpose input / output pins as data or clock signal output ports, and to interact with the chip under test through the data or clock signal output ports, record the test data of the main chip under test and the replacement chip under test, and send the test data to the upper-level unit. The oscilloscope unit is also used to acquire test waveforms during the data interaction process between the lower-level unit and the chip under test. The host computer unit is used to query the test data of the main chip under test and the replacement chip under test sent by the slave computer unit in real time, and to perform comparative analysis based on the test data of the main chip under test and the replacement chip under test, and output the functional test comparison analysis results of the main chip under test and the replacement chip under test. The host computer unit is also used to analyze the test waveforms during the data interaction between the slave computer unit and the chip under test, and output the signal test results of the main chip under test and the replacement chip under test.

7. The chip comparison testing apparatus according to claim 5 or 6, characterized in that, The power supply unit includes multiple voltage regulation units. By adjusting the output of different voltage regulation units, the lower-level unit is also used to perform voltage bias testing on the chip under test.

8. A chip comparison testing method, based on the chip comparison testing apparatus as described in any one of claims 1 to 7, characterized in that, include: The host computer unit sends test commands to the slave computer unit; The lower-level unit receives the test command and, in response to the test command, sends a test signal to the chip under test in the replaceable module through the connector unit; The oscilloscope unit acquires the test waveform corresponding to the chip under test and sends the test waveform to the host computer unit; The host computer unit performs comparative analysis on the test waveforms and outputs the comparative analysis results.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip comparison test method as described in claim 8.

Images