A DTOF data processing method, device, equipment and storage medium

Abstract

Embodiments of the present application provide a DTOF data processing method, device and equipment and a storage medium. The method is applied to a device including SPADs. Each SPAD includes N pixels, and each pixel is configured with a register for saving offset data. The method includes: when the indication bits of all registers are configured as a first value, the data bits of the register corresponding to each pixel are simultaneously configured, and the data bits of the register corresponding to any two pixels are the same; when the indication bits of all registers are configured as a second value, the data bits of the register corresponding to each pixel are sequentially configured, and the data bits of the register corresponding to each pixel satisfy an offset setting condition; and the TDC data of each pixel is calculated with the data bits of the register corresponding to each pixel to determine the corrected histogram data corresponding to each pixel. According to the embodiments of the present application, the corrected histogram data can be quickly obtained.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a DTOF data processing method, apparatus, device and storage medium. Background Technology

[0002] When light is extremely weak, it disperses into individual photons. A single photon refers to the quantum state of a single photon, describing its quantum properties. Due to their weak intensity and significant particle nature, single-photon signals are difficult to detect using conventional techniques. Direct Time of Flight (DTOF) technology directly calculates distance based on the time difference between pulse emission and reception, overcoming the difficulties of photoelectric detection technology and enabling single-photon detection.

[0003] Single-photon avalanche diodes (SPADs) are the core technology for achieving DTOF (Digital Time-to-Flight). An increasing number of electronic devices (such as cameras or mobile phones) integrate chips containing SPADs. A SPAD consists of multiple pixels, and the pixel's Time-to-Digital Converter (TDC) data needs to be corrected before being stored in a histogram to obtain corrected histogram data. How to quickly obtain the corrected histogram data is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a DTOF data processing method, apparatus, device, and storage medium that can quickly obtain corrected histogram data.

[0005] In a first aspect, embodiments of this application provide a DTOF data processing method. This method is applied to a device including a SPAD array, where the SPAD array comprises N pixels, and each of the N pixels is configured with a register for storing offset data, where N is a positive integer greater than 1. The method includes:

[0006] When all register indicator bits are configured to the first value, the data bit value of the register corresponding to each of the N pixels is configured at the same time, and the data bit values ​​of the registers corresponding to any two of the N pixels are the same;

[0007] When all register indicator bits are configured to the second value, the data bits of the register corresponding to each of the N pixels are configured sequentially, and the data bits of the register corresponding to each of the N pixels satisfy the offset setting condition.

[0008] The TDC data of each of the N pixels is calculated together with the data bit values ​​of the corresponding registers of each of the N pixels to determine the corrected histogram data for each of the N pixels.

[0009] Therefore, when all register indicator bits are at their first value, the data bits of all registers can be quickly configured to the same value, thus improving the efficiency of DTOF data processing. When all register indicator bits are at their second value, the data bits of the registers corresponding to each of the N pixels are configured sequentially, ensuring that the data bits of the registers corresponding to each of the N pixels satisfy the offset setting conditions. This improves the accuracy of the corrected histogram data when the TDC data of a pixel is processed based on the pixel's offset data to obtain the corrected histogram data.

[0010] In one possible implementation, the method further includes: if the TDC performance difference between any two pixels among the N pixels is within a threshold range, then configure the indicator bits of all registers to a first value; if the TDC performance difference between any two pixels among the N pixels is not within the threshold range, then configure the indicator bits of all registers to a second value. Thus, when the TDC performance difference between any two pixels among the N pixels is small, the efficiency of DTOF data processing can be improved. When the TDC performance difference between any two pixels among the N pixels is large, the accuracy of the corrected histogram data corresponding to each pixel among the N pixels can be improved.

[0011] In one possible implementation, the method further includes: if the N pixels are pixels in a single-point scene, then determining that the TDC performance difference between any two pixels among the N pixels is within a threshold range. Therefore, if the N pixels are pixels in a single-point scene, the efficiency of DTOF data processing can be improved.

[0012] In one possible implementation, the data bits of the register corresponding to each of the N pixels are configured simultaneously. Specifically, this includes: configuring the data bits of the register corresponding to the i-th pixel among the N pixels, where i is an integer greater than or equal to 1 and less than or equal to N; and using a broadcast mode, configuring the data bits of the register corresponding to each of the other N-1 pixels (excluding the i-th pixel), where the values ​​of the data bits of the register corresponding to each of the other N-1 pixels are the same as the values ​​of the data bits of the register corresponding to the i-th pixel. Thus, using the broadcast mode saves time in configuring the registers and improves the efficiency of register configuration.

[0013] In one possible implementation, the TDC data of each of the N pixels is calculated along with the value of the data bit in the register corresponding to each of the N pixels to determine the corrected histogram data for each pixel. Specifically, this involves subtracting the photon counts corresponding to the preceding Mi timeboxes from the TDC data of the i-th pixel, where Mi is the value of the data bit in the register corresponding to the i-th pixel. The value of the data bit in the register corresponding to the pixel is the pixel's offset data. Thus, by processing the pixel's TDC data based on the pixel's offset data, the corrected histogram data for the pixel can be obtained, correcting the pixel's TDC data and yielding more accurate timing information.

[0014] In one possible implementation, the method further includes: each of the N pixels has a register consisting of 10 bits, with the first bit serving as an indicator bit and the remaining bits serving as data bits. This allows the value of the indicator bit to be quickly detected using the first bit, improving the efficiency of DTOF data processing.

[0015] In one possible implementation, the method further includes: the histogram data includes time bins and the photon counts corresponding to the time bins.

[0016] Secondly, embodiments of this application provide a DTOF data processing apparatus, which includes a SPAD array comprising N pixels, each of the N pixels being configured with a register for storing offset data, where N is a positive integer greater than 1; the apparatus further includes:

[0017] The configuration unit is used to configure the data bit value of the register corresponding to each of the N pixels simultaneously when all the indicator bits of the registers are configured to the first value, such that the data bit values ​​of any two pixels in the N pixels are the same; and to configure the data bit value of the register corresponding to each of the N pixels sequentially when all the indicator bits of the registers are configured to the second value, such that the data bit value of the register corresponding to each of the N pixels satisfies the offset setting condition.

[0018] The calculation unit is used to calculate the TDC data of each pixel in the N pixels and the value of the data bit of the register corresponding to each pixel in the N pixels to determine the corrected histogram data corresponding to each pixel in the N pixels.

[0019] On one hand, embodiments of this application provide a computer device, including: a processor, a communication interface, and a memory, wherein the processor, the communication interface, and the memory are interconnected, wherein the memory stores executable program code, and the processor is used to call the executable program code to implement the DTOF data processing method provided in embodiments of this application.

[0020] Accordingly, embodiments of this application also provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to implement the DTOF data processing method provided in embodiments of this application. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a DTOF data processing method provided in an exemplary embodiment of this application;

[0022] Figure 2 This is a schematic diagram illustrating an exemplary embodiment of this application of storing pixel offset data using a register;

[0023] Figure 3 This is a schematic diagram of the data structure of TDC data or modified histogram data provided in an exemplary embodiment of this application;

[0024] Figure 4 This is a schematic diagram of TDC data provided in an exemplary embodiment of this application;

[0025] Figure 5 This is a schematic diagram of modified histogram data provided in an exemplary embodiment of this application;

[0026] Figure 6 This is a schematic block diagram of a DTOF data processing apparatus provided in an exemplary embodiment of this application;

[0027] Figure 7 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] First, the terms or concepts involved in the embodiments of this application will be explained.

[0030] 1. Photon

[0031] A photon can be used to represent the fundamental particle of light, that is, a microscopic entity in which light exists in particle form. In quantum physics, light can be viewed as being composed of many photons.

[0032] 2. Single photon

[0033] A single photon refers to the quantum state of a single photon, describing the quantum properties of a photon.

[0034] 3. DTOF

[0035] DTOF stands for Direct Time-of-Flight, which calculates distance directly based on the time difference between pulse emission and reception. DTOF can be used in photoelectric detection technology to calculate the distance a photon travels in space using the time difference between emission and reception and the speed of light, overcoming the difficulties of photoelectric detection technology and enabling single-photon detection.

[0036] 4. SPAD

[0037] SPAD is a highly sensitive photodiode. SPADs are used in photoelectric detection technology and are the core technology for achieving Direct Time-of-Flight (DTOF). The working principle of a SPAD is based on the photoelectric effect and avalanche amplification. When a photon enters the photosensitive area of ​​the SPAD, it generates an electron-hole pair. This pair of charge carriers is accelerated by an electric field, breaking down the reverse bias voltage of the pn junction and triggering the avalanche effect. The avalanche effect generates a large number of secondary electrons and holes, forming a rapid current pulse. This current pulse can be detected and recorded by a receiving circuit or a counter.

[0038] A SPAD consists of multiple pixels, each of which is an independent photodiode with its own photosensitive area and circuitry. It can also be considered a separate detection unit used to measure light intensity or time to arrival. When a photon strikes a pixel, it is detected and converted into an electrical signal. This signal is amplified, converted, and processed by appropriate circuitry to obtain relevant information about the light. The pixel value in a SPAD typically represents the intensity of the light signal; a higher pixel value indicates greater light intensity.

[0039] 5. Pixel TDC data

[0040] Pixel TDC data refers to digital data about the time of light propagation or time of light arrival, obtained through TDC measurements. When a photon hits a pixel, the TDC begins timing and records the time it takes for light to arrive at the pixel. The TDC converts the light arrival time into digital form and represents it with a specific level of precision.

[0041] The TDC data of a pixel can be two-dimensional, including a time bin and the photon count corresponding to the time bin. The time bin can represent the range of values ​​of the pixel, and the photon count corresponding to the time bin can represent the number of times a photon arrives at or leaves the pixel at the corresponding pixel value.

[0042] 6. Pixel offset data

[0043] Pixel offset data represents the offset of a pixel on the time axis. It can also be used to represent how many time bins of data need to be subtracted before the TDC data of each pixel is stored in the histogram.

[0044] 7. Single point

[0045] If multiple pixels are pixels in a single-point scene, then the histogram data of the above multiple pixels need to be merged into one histogram data, and the TDC performance difference between any two pixels among the above multiple pixels is not significant.

[0046] 8. Registers

[0047] Registers are an important component in computers for storing data. They can be used to store information such as instructions, data, and addresses. In this scheme, registers are used to store pixel offset data.

[0048] The DTOF data processing method provided in the embodiments of this application will be described in detail below.

[0049] Please see Figure 1 , Figure 1 This is a flowchart illustrating a DTOF data processing method provided in an exemplary embodiment of this application. The method includes, but is not limited to, the following steps:

[0050] S101. When all register indicator bits are configured to the first value, the data bit value of the register corresponding to each of the N pixels is configured at the same time, and the data bit values ​​of the registers corresponding to any two of the N pixels are the same.

[0051] In this embodiment, the SPAD array includes N pixels, and each of the N pixels is configured with a register for storing offset data, where N is a positive integer greater than 1. Each register for each of the N pixels includes an indicator bit and data bits. The indicator bit can be used to indicate the configuration state of the register, and the data bits are used to store the pixel's offset data. The register can include multiple bits, and the DTOF data processing device can configure one or more bits in the register as indicator bits, and configure the other bits as data bits. For example, the register includes 10 bits, and the DTOF data processing device configures the first bit of the 10 bits as an indicator bit, and configures the other bits as data bits. The DTOF data processing device can quickly detect the value of the indicator bit through the first bit, improving the efficiency of DTOF data processing.

[0052] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating an exemplary embodiment of this application, showing how to store pixel offset data using a register. Figure 2 Taking a SPAD consisting of 100 pixels as an example, each of the 100 pixels corresponds to a register used to store offset data. Figure 2 Taking the row containing pixel 1 as an example, the row containing pixel 1 includes pixel 1 and the corresponding register 1 used to store offset data. For example, the register corresponding to pixel 1 used to store offset data has 10 bits. The DTOF data processing device configures the first bit of the 10 bits as an indicator bit and the bits other than the first bit of the 10 bits as data bits. At this time, register 1 can be represented as register 1[9:0]. Register 1[9] is the indicator bit of pixel 1, and register 1[8:0] is the data bit of pixel 1. This data bit is used to store the offset data of pixel 1.

[0053] In one embodiment, if the TDC performance difference between any two pixels out of N pixels is within a threshold range, that is, when the TDC performance difference between any two pixels out of N pixels is small, the DTOF data processing device configures the indicator bits of all registers to a first value. The threshold range can be a default value, such as the factory-set threshold range. This application embodiment does not limit the specific value of the threshold range. Within the threshold range can be understood as a small TDC performance difference, and outside the threshold range can be understood as a large TDC performance difference. For example, if the value of N is 100, and the TDC performance difference between any two pixels out of these 100 pixels is within the threshold range (e.g., the threshold is 10, and the difference in TDC performance parameters between any two pixels is less than 10), then the DTOF data processing device configures the indicator bits of the registers corresponding to each pixel in the aforementioned 100 pixels to a first value. For an example with a second value of 0, please refer to [link to relevant documentation]. Figure 2 For example, the register corresponding to a pixel has 10 bits, with the first bit of the register being the indicator bit. The values ​​of register 1[9], register 2[9], ... and register 100[9] are 0.

[0054] In one embodiment, if the aforementioned N pixels are pixels in a single-point scene, then the DTOF data processing device can determine that the TDC performance difference between any two pixels among these N pixels is within a threshold range. This application does not limit the specific method by which the DTOF data processing device determines a single-point scene.

[0055] In one embodiment, simultaneously configuring the data bits of the register corresponding to each of the N pixels can be achieved by the DTOF data processing device configuring the data bits of the register storing offset data corresponding to any one of the N pixels. This "any one pixel" can be represented as the i-th pixel, where i is an integer greater than or equal to 1 and less than or equal to N. For example, the i-th pixel could be the 1st, 2nd, ..., or Nth pixel among the N pixels. Using a broadcast mode, the data bits of the register corresponding to each of the other N-1 pixels (excluding the i-th pixel) are configured, ensuring that the data bits of the register corresponding to each of the other N-1 pixels are the same as the data bits of the register corresponding to the i-th pixel. This broadcast mode saves time in configuring the registers and improves the efficiency of register configuration. For example, N is 100, i is 1, and the offset data corresponding to the first pixel is 200. The DTOF data processing device configures the data bits of the register corresponding to the first pixel out of 100 pixels to 200, and then uses broadcast mode to configure the data bits of the registers corresponding to the remaining 99 pixels to be the same as the data bits of the first pixel. Please refer to [link to relevant documentation]. Figure 2For example, the register corresponding to a pixel has 10 bits, with the first bit of the register being an indicator bit. At this time, the values ​​of register 1[8:0], register 2[8:0], register 3[8:0]... and register 100[8:0] are all 200.

[0056] In step S101, when the indicator bit of the register is configured to the first value, the DTOF data processing device can quickly configure the values ​​of the data bits of all registers to the same value, thereby improving the efficiency of DTOF data processing.

[0057] S102. When all register indicator bits are configured to the second value, the data bits of the register corresponding to each of the N pixels are configured sequentially, and the data bits of the register corresponding to each of the N pixels satisfy the offset setting condition.

[0058] In one embodiment, if the TDC performance difference between any two pixels out of N pixels is not within a threshold range (i.e., the TDC performance difference between any two pixels out of N pixels is large), the DTOF data processing device configures the indicator bits of all registers to a second value. For example, if N is 100, and the TDC performance difference between any two pixels out of these 100 pixels is not within a threshold range (e.g., the threshold is 10, and the difference in TDC performance parameters between any two pixels is greater than or equal to 10), then the DTOF data processing device configures the indicator bits of the registers corresponding to these 100 pixels to the second value, for example, a second value of 1. See also... Figure 2 For example, the register corresponding to a pixel has 10 bits, with the first bit of the register being the indicator bit. The values ​​of register 1[9], register 2[9], ... and register 100[9] are 1.

[0059] It should be noted that the second value mentioned above is not the same as the first value. For example, the first value is 0 and the second value is 1; or the first value is 1 and the second value is 0. For example,... Figure 2 Taking the row where pixel 1 is located as an example, the register corresponding to pixel 1 has a total of 10 bits. The first bit of the register is the indicator bit. When the value of the indicator bit of pixel 1 is the first value, register 1[9] is 0. When the value of the indicator bit of pixel 1 is the second value, register 1[9] is 1. Or, when the value of the indicator bit of pixel 1 is the first value, register 1[9] is 1. When the value of the indicator bit of pixel 1 is the second value, register 1[9] is 0.

[0060] Unlike when all register indicator bits are at the first value, when all register indicator bits are at the second value, the DTOF data processing device needs to sequentially configure the data bits of the register corresponding to each of the N pixels, so that the value of the data bits of the register corresponding to each of the N pixels is the data offset value corresponding to that pixel. For example, if N is 100, the indicator bits of the registers corresponding to each of these 100 pixels are at the second value. The offset data of the first pixel is 200, so the DTOF data processing device configures the data bits of the register corresponding to the first pixel to 200; the offset data of the second pixel is 220, so the DTOF data processing device configures the data bits of the register corresponding to the second pixel to 220; the offset data of the third pixel is 240, so the DTOF data processing device configures the data bits of the register corresponding to the third pixel to 240, and so on, sequentially configuring the data bits of the registers corresponding to each of the 100 pixels. See also... Figure 2 Taking a pixel-corresponding register as an example, with the first bit of the register serving as an indicator, the value of register 1 [8:0] is 200, the value of register 2 [8:0] is 220, the value of register 3 [8:0] is 240...

[0061] In step S102, when the indicator bit of the register is configured to the second value, when the DTOF data processing device processes the TDC data of the pixel based on the offset data of the pixel to obtain the corrected histogram data corresponding to the pixel, the accuracy of the corrected histogram data corresponding to the pixel can be improved.

[0062] S103. Calculate the TDC data of each pixel in the N pixels and the value of the data bit of the register corresponding to each pixel in the N pixels to determine the corrected histogram data corresponding to each pixel in the N pixels.

[0063] In this embodiment, the TDC data and the corrected histogram data are two-dimensional, including time bins and the photon counts corresponding to each time bin. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of a data structure for TDC data or modified histogram data provided in an exemplary embodiment of this application. It can be divided into an x-axis and a y-axis in two-dimensional space, where the x-axis can represent a time box and the y-axis can represent the photon count corresponding to the time box.

[0064] In this embodiment, the TDC data of each pixel in the N pixels is calculated together with the value of the data bit of the register corresponding to each pixel in the N pixels to determine the corrected histogram data corresponding to each pixel in the N pixels. For example, taking any pixel in the N pixels as the i-th pixel, the DTOF data processing device subtracts the photon counts corresponding to the preceding Mi timeboxes from the TDC data of the i-th pixel to obtain the corrected histogram data corresponding to the i-th pixel. Mi is the value of the data bit of the register corresponding to the i-th pixel, and the value of the data bit of the register corresponding to the i-th pixel is the data offset value of the i-th pixel. For an example, please refer to [link to example]. Figure 4 , Figure 4 This is a schematic diagram of TDC data provided in an exemplary embodiment of this application. The TDC data of the i-th pixel has 1000 time boxes, and each of the 1000 time boxes has a corresponding photon count of 1000. When the time box is 200, the corresponding photon count is 300; when the time box is 400, the corresponding photon count is 400; when the time box is 600, the corresponding photon count is 320; when the time box is 800, the corresponding photon count is 340; and when the time box is 1000, the corresponding photon count is 270. Assuming that the value of the register data bit corresponding to the i-th pixel is 200, the DTOF data processing device needs to subtract the photon counts corresponding to the first 200 time boxes from the TDC data of the i-th pixel to obtain the modified histogram data of the i-th pixel. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of modified histogram data provided in an exemplary embodiment of this application. In this case, the modified histogram data of the i-th pixel is the last 800 time boxes of the TDC data of the i-th pixel and the photon count corresponding to the 800 time boxes.

[0065] exist Figure 1 In the embodiment shown, the DTOF data processing device processes the TDC data of a pixel based on pixel offset data to obtain the corrected histogram data corresponding to the pixel, which can correct the TDC data of the pixel and obtain more accurate time information.

[0066] Please see Figure 6 , Figure 6 This is a schematic block diagram of a DTOF data processing apparatus provided in an exemplary embodiment of this application. The DTOF data processing apparatus described in this embodiment includes a SPAD array, which comprises N pixels. Each of the N pixels is configured with a register for storing offset data, where N is a positive integer greater than 1. The DTOF data processing apparatus further includes:

[0067] The configuration unit 601 is used to: when the indicator bits of all registers are configured to the first value, simultaneously configure the value of the data bit of the register corresponding to each of the N pixels, wherein the values ​​of the data bits of the registers corresponding to any two of the N pixels are the same;

[0068] Configuration unit 601 is further configured to: when the indicator bits of all registers are configured to the second value, sequentially configure the value of the data bit of the register corresponding to each of the N pixels, wherein the value of the data bit of the register corresponding to each of the N pixels satisfies the offset setting condition;

[0069] The calculation unit 602 is used to: calculate the TDC data of each of the N pixels and the value of the data bit of the register corresponding to each of the N pixels to determine the corrected histogram data corresponding to each of the N pixels.

[0070] In one embodiment, the configuration unit 601 is specifically configured to: if the TDC performance difference between any two pixels among N pixels is within a threshold range, configure the indicator bits of all registers to a first value; if the TDC performance difference between any two pixels among N pixels is not within the threshold range, configure the indicator bits of all registers to a second value.

[0071] In one embodiment, the configuration unit 601 is specifically used to: if the N pixels are pixels in a single-point scene, determine that the TDC performance difference between any two pixels among the N pixels is within the threshold range.

[0072] In one embodiment, the configuration unit 601 is specifically used to: configure the value of the data bit of the register corresponding to the i-th pixel among the N pixels, where i is an integer greater than or equal to 1 and less than or equal to N; and, using a broadcast mode, configure the value of the register data bit corresponding to each of the other N-1 pixels besides the i-th pixel among the N pixels, so that the value of the register data bit corresponding to each of the other N-1 pixels is the same as the value of the register data bit corresponding to the i-th pixel.

[0073] In one embodiment, the calculation unit 602 is specifically used to: subtract the photon counts corresponding to the preceding Mi timeboxes from the TDC data of the i-th pixel among the N pixels to obtain the corrected histogram data corresponding to the i-th pixel, where Mi is the value of the data bit of the register corresponding to the i-th pixel.

[0074] In one embodiment, the configuration unit 601 is specifically used to: configure the register corresponding to each of the N pixels as 10 bits, configure the first bit of the 10 bits as an indicator bit, and configure the bits other than the first bit of the 10 bits as data bits.

[0075] In one embodiment, the histogram data includes time bins and the photon counts corresponding to the time bins.

[0076] It is understood that the functions of each functional unit of the DTOF data processing device in the embodiments of this application can be specifically implemented according to the DTOF data processing method in the above method embodiments. The specific implementation process can be referred to the relevant description in the above DTOF data processing method embodiments, which will not be repeated here.

[0077] Please see Figure 7 , Figure 7 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device described in this embodiment includes a processor 701, a communication interface 702, and a memory 703. The processor 701, communication interface 702, and memory 703 can be connected via a bus or other means; this embodiment uses a bus connection as an example.

[0078] The processor 701 (or CPU, Central Processing Unit) is the computing and control core of the computer device. It can parse various instructions and process various data within the computer device. For example, the CPU can parse power-on / off commands sent by the user and control the computer device to perform power-on / off operations; it can also transmit various interactive data between internal structures of the computer device. The communication interface 702 may optionally include standard wired interfaces or wireless interfaces (such as Wi-Fi, mobile communication interfaces, etc.), and is controlled by the processor 701 for sending and receiving data. The memory 703 is the storage device in the computer device, used to store programs and data. It is understood that the memory 703 here can include the computer device's built-in memory, or it can include extended memory supported by the computer device. The memory 703 provides storage space for the computer device's operating system, which may include, but is not limited to, Android, iOS, Windows Phone, etc., and this application does not limit this.

[0079] In this embodiment, processor 701 includes a SPAD array comprising N pixels. Each of the N pixels is configured with a register for storing offset data, where N is a positive integer greater than 1. Processor 701 performs the following operations by running executable program code in memory 703:

[0080] When all register indicator bits are configured to the first value, the data bit value of the register corresponding to each of the N pixels is configured at the same time, and the data bit values ​​of the registers corresponding to any two of the N pixels are the same;

[0081] When all register indicator bits are configured to the second value, the data bits of the register corresponding to each of the N pixels are configured sequentially, and the data bits of the register corresponding to each of the N pixels satisfy the offset setting condition.

[0082] The TDC data of each of the N pixels is calculated together with the data bit values ​​of the corresponding registers of each of the N pixels to determine the corrected histogram data for each of the N pixels.

[0083] In one embodiment, the processor 701 is specifically configured to: if the TDC performance difference between any two pixels among the N pixels is within a threshold range, configure the indicator bits of all registers to the first value; if the TDC performance difference between any two pixels among the N pixels is not within the threshold range, configure the indicator bits of all registers to the second value.

[0084] In one embodiment, the processor 701 is specifically configured to: if the N pixels are pixels in a single-point scene, determine that the TDC performance difference between any two pixels among the N pixels is within the threshold range.

[0085] In one embodiment, the processor 701 is specifically configured to: configure the value of the data bit of the register corresponding to the i-th pixel among the N pixels, where i is an integer greater than or equal to 1 and less than or equal to N; and, using a broadcast mode, configure the value of the register data bit corresponding to each of the other N-1 pixels (excluding the i-th pixel) among the N pixels, so that the value of the register data bit corresponding to each of the other N-1 pixels is the same as the value of the register data bit corresponding to the i-th pixel.

[0086] In one embodiment, the processor 701 is specifically configured to: subtract the photon counts corresponding to the preceding Mi timeboxes from the TDC data of the i-th pixel among the N pixels to obtain the corrected histogram data corresponding to the i-th pixel, where Mi is the value of the data bit of the register corresponding to the i-th pixel.

[0087] In one embodiment, the processor 701 is specifically configured to: each of the N pixels has a register containing 10 bits, configure the first bit of the 10 bits as an indicator bit, and configure the remaining bits of the 10 bits as data bits.

[0088] In one embodiment, the histogram data includes time bins and the photon counts corresponding to the time bins.

[0089] In specific implementations, the processor 701, communication interface 702, and memory 703 described in the embodiments of this application can execute the implementation of the computer device described in the DTOF data processing method provided in the embodiments of this application, or the implementation of the DTOF data processing device provided in the embodiments of this application, which will not be repeated here.

[0090] This application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to implement the DTOF data processing method provided in this application.

[0091] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0092] Those skilled in the art will understand that all or part of the steps in the various methods of this embodiment can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0093] The above-disclosed embodiments are only some of the embodiments of this application, and should not be construed as limiting the scope of this application. Therefore, any equivalent changes made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A DTOF data processing method, characterized in that, The method is applied to a device including a SPAD, wherein the SPAD comprises N pixels, and each of the N pixels is configured with a register for storing offset data, where N is a positive integer greater than 1; the method includes: When all register indicator bits are configured to the first value, the data bits of the register corresponding to each of the N pixels are simultaneously configured, and the data bits of the registers corresponding to any two of the N pixels have the same value; the simultaneous configuration of the data bits of the registers corresponding to each of the N pixels includes: configuring the data bit of the register corresponding to the i-th pixel of the N pixels, where i is an integer greater than or equal to 1 and less than or equal to N; and using a broadcast mode, configuring the data bits of the registers corresponding to each of the other N-1 pixels (excluding the i-th pixel) of the N pixels, where the data bits of the registers corresponding to each of the other N-1 pixels have the same value as the data bits of the register corresponding to the i-th pixel; When all register indicator bits are configured to the second value, the data bits of the register corresponding to each of the N pixels are configured sequentially, and the data bits of the register corresponding to each of the N pixels satisfy the offset setting condition; The TDC data of each of the N pixels is calculated together with the data bit value of the register corresponding to each of the N pixels to determine the corrected histogram data corresponding to each of the N pixels.

2. The method as described in claim 1, characterized in that, The method further includes: If the TDC performance difference between any two pixels among the N pixels is within the threshold range, then the indicator bits of all registers are configured to the first value; If the TDC performance difference between any two pixels among the N pixels is not within the threshold range, then the indicator bits of all registers are configured to the second value.

3. The method as described in claim 2, characterized in that, The method further includes: If the N pixels are pixels in a single-point scene, then the TDC performance difference between any two pixels among the N pixels is determined to be within the threshold range.

4. The method according to any one of claims 1-3, characterized in that, The step of calculating the TDC data of each of the N pixels and the value of the data bit of the register corresponding to each of the N pixels to determine the corrected histogram data for each of the N pixels includes: Subtract the photon counts corresponding to the preceding Mi timeboxes from the TDC data of the i-th pixel among the N pixels to obtain the corrected histogram data corresponding to the i-th pixel, where Mi is the value of the data bit of the register corresponding to the i-th pixel.

5. The method as described in claim 1, characterized in that, Each of the N pixels has a register consisting of 10 bits. The first bit of the 10 bits is an indicator bit, and the bits other than the first bit are data bits.

6. The method as described in claim 1, characterized in that, The histogram data includes time bins and the photon counts corresponding to the time bins.

7. A DTOF data processing device, characterized in that, The device includes a SPAD array comprising N pixels, each of the N pixels being configured with a register for storing offset data, where N is a positive integer greater than 1; the device further includes: A configuration unit is configured to, when all register indicator bits are configured to a first value, simultaneously configure the data bit value of the register corresponding to each of the N pixels, wherein the data bit values ​​of any two pixels in the N pixels are the same; when all register indicator bits are configured to a second value, sequentially configure the data bit value of the register corresponding to each of the N pixels, wherein the data bit value of the register corresponding to each pixel in the N pixels satisfies an offset setting condition; the simultaneous configuration of the data bit value of the register corresponding to each of the N pixels includes: configuring the data bit value of the register corresponding to the i-th pixel in the N pixels, where i is an integer greater than or equal to 1 and less than or equal to N; and, using a broadcast mode, configuring the data bit value of the register corresponding to each of the other N-1 pixels (excluding the i-th pixel) in the N pixels, wherein the data bit value of the register corresponding to each of the other N-1 pixels is the same as the data bit value of the register corresponding to the i-th pixel; The calculation unit is used to calculate the TDC data of each of the N pixels and the value of the data bit of the register corresponding to each of the N pixels to determine the corrected histogram data corresponding to each of the N pixels.

8. A computer device, characterized in that, include: The system includes a processor, a communication interface, and a memory, which are interconnected. The memory stores executable program code, and the processor is used to call the executable program code to implement the DTOF data processing method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the computer to implement the DTOF data processing method as described in any one of claims 1-6.

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