Control system and control method for exiting low power mode, display device

Abstract

This invention discloses a control system and method for exiting a low-power mode, as well as a display device. The control system for exiting a low-power mode includes a central processing unit (CPU), a main control module, a low-power mode entry / exit control module, and a mode control circuit. The main control module is electrically connected to the low-power mode entry / exit control module, which is electrically connected to the first control terminal of the mode control circuit. When the potential at its first control terminal changes from a first potential signal to a second potential signal, the mode control circuit controls the CPU to exit the low-power mode from the stage it was in when entering the low-power mode. By determining the stage the CPU was in when entering the low-power mode upon receiving the instruction to exit the low-power mode through the mode control circuit, and directly executing the exit from the last stage, the time to exit the low-power mode is shortened.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a control system and control method for exiting low-power mode, and a display device. Background Technology

[0002] Electronic devices operate in two states: low-power mode and normal mode. When no functional operation is required, the electronic device can enter a low-power mode. For example, if a mobile phone does not receive a touch within a set time, the screen can be turned off to reduce the power consumption of the entire device.

[0003] Electronic devices, including central processing units (MCUs), typically require an exit from low-power mode to perform normal functional operations. This exit occurs when the MCU is fully in low-power mode, followed by a wake-up process (the exit process). However, if the electronic device receives an exit command while the MCU is entering low-power mode, it will continue with the remaining steps of the low-power mode entry process until it is fully in low-power mode, at which point the wake-up process will occur. This results in a longer exit time for the MCU. Summary of the Invention

[0004] This invention provides a control system and control method for exiting a low-power mode, as well as a display device, to shorten the time required to exit the low-power mode and improve the system's response speed.

[0005] According to one aspect of the present invention, a control system for exiting a low-power mode is provided, comprising: a central processing unit, a main control module, a low-power mode entry / exit control module, and a mode control circuit.

[0006] The main control module is electrically connected to the low-power mode entry / exit control module, and the low-power mode entry / exit control module is electrically connected to the first control terminal of the mode control circuit. When the main control module receives an instruction to control the central processing unit to enter a low-power mode, it controls the low-power mode entry / exit control module to transmit a first potential signal to the first control terminal. The low-power mode entry / exit control module is also electrically connected to the second control terminal of the mode control circuit, and the low-power mode entry / exit control module is used to transmit an entry stage timing signal to the second control terminal to control the central processing unit to gradually enter a low-power mode.

[0007] The main control module is also used to control the low-power mode entry / exit control module to transmit a second potential signal to the first control terminal when it receives an instruction to control the central processing unit to exit the low-power mode.

[0008] The mode control circuit is used to determine the stage in which the central processing unit enters the low-power mode based on the entry stage timing signal when the potential at its first control terminal changes from a first potential signal to a second potential signal.

[0009] The mode control circuit is also used to control the central processing unit to exit the low-power mode from the stage of entering the low-power mode when the potential of its first control terminal is the second potential.

[0010] Optionally, the mode control circuit includes a memory circuit and a wake-up circuit. The first input terminal of the memory circuit serves as the third control terminal of the mode control circuit, the second input terminal of the memory circuit serves as the first control terminal of the mode control circuit, the third input terminal of the memory circuit serves as the second control terminal of the mode control circuit, and the fourth input terminal of the memory circuit is electrically connected to the low-power mode entry / exit control module. The memory circuit is used to determine the stage in which the central processing unit enters the low-power mode based on the potential of its second input terminal and the entry stage timing signal when the potential of its first input terminal is a first potential signal. The low-power mode entry / exit control module is used to generate an exit timing signal based on the stage in which the central processing unit enters the low-power mode. The memory circuit is used to control the central processing unit to exit the low-power mode based on the potential of its second input terminal and the exit timing signal when the potential of its first input terminal is a first potential signal.

[0011] The first input terminal of the wake-up circuit is electrically connected to the output terminal of the central processing unit (CPU), and the second input terminal of the wake-up circuit is electrically connected to the first output terminal of the main control module. When the main control module receives an instruction to control the CPU to enter a low-power mode, it transmits the first potential signal to the second input terminal of the wake-up circuit. The third input terminal of the wake-up circuit is electrically connected to the second output terminal of the main control module. The control terminal of the wake-up circuit is electrically connected to the output terminal of the memory circuit, and the output terminal of the wake-up circuit is electrically connected to the CPU. When the main control module receives an instruction to control the CPU to exit the low-power mode, it transmits the first potential signal to the third input terminal of the wake-up circuit. The wake-up circuit generates a wake-up signal based on the potentials of its first, second, and third input terminals to control the CPU to exit the low-power mode.

[0012] Optionally, the memory circuit includes a first unit and a second unit. The first unit includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the first unit serves as the first input terminal of the memory circuit, the second terminal of the first unit serves as the second input terminal of the memory circuit, the third terminal of the first unit serves as the third input terminal of the memory circuit, and the fourth terminal of the first unit serves as the fourth input terminal of the memory circuit. The output terminal of the first unit is electrically connected to the input terminal of the second unit. The first unit is used to transmit the entry stage timing signal to the input terminal of the second unit when the potential of its first terminal is a first potential signal and the potential of its second terminal is the first potential signal. The first unit is also used to transmit the exit timing signal to the input terminal of the second unit when the potential of its first terminal is the first potential signal and the potential of its second terminal is the second potential signal.

[0013] The control terminal of the second unit is electrically connected to the second terminal of the first unit. The second unit is used to count the number of pulses of the entry phase timing signal when the potential of its own control terminal is the first potential, and is also used to control the wake-up circuit to generate a wake-up signal according to the counted number of pulses of the entry phase timing signal and the number of pulses of the exit timing signal when the potential of its own control terminal is the second potential.

[0014] Optionally, the number of pulses in the entry phase timing signal is the same as the number of pulses in the exit phase timing signal.

[0015] Optionally, the entry phase timing signal includes m pulses, and the nth pulse of the entry phase timing signal has the same shape as the (m-n+1)th pulse of the exit timing signal, where m and n are both positive integers, and n is less than m.

[0016] Optionally, the first unit includes a first selector and a first AND gate, and the second unit includes a counter;

[0017] The first input terminal of the first selector serves as the third terminal of the first unit, the second input terminal of the first selector serves as the fourth terminal of the first unit, the control terminal of the first selector serves as the second terminal of the first unit, the output terminal of the first selector is electrically connected to the first input terminal of the first AND gate, the second input terminal of the first AND gate serves as the first terminal of the first unit, the output terminal of the first AND gate is electrically connected to the input terminal of the counter, the control terminal of the counter serves as the control terminal of the second unit, and the output terminal of the counter serves as the output terminal of the second unit.

[0018] Optionally, the memory circuit further includes a register, the input of which is electrically connected to the output of the memory circuit, and the register is used to store the stage in which the central processing unit enters the low-power mode.

[0019] Optionally, the wake-up circuit includes a second AND gate, a third AND gate, and a second selector. The first input terminal of the second AND gate serves as the second input terminal of the wake-up circuit, the second input terminal of the second AND gate serves as the third input terminal of the wake-up circuit, the output terminal of the second AND gate is electrically connected to the first input terminal of the third AND gate, the second input terminal of the third AND gate serves as the first input terminal of the wake-up circuit, the output terminal of the third AND gate is electrically connected to the first input terminal of the second selector, the second input terminal of the second selector is connected to a fixed potential signal, the control terminal of the second selector serves as the control terminal of the wake-up circuit, and the output terminal of the second selector serves as the output terminal of the wake-up circuit.

[0020] According to another aspect of the present invention, a control method for exiting a low-power mode is provided, for controlling the control system for exiting the low-power mode as described in any of the preceding aspects, the control method comprising:

[0021] When the main control module receives an instruction to control the central processing unit to enter low-power mode, it controls the low-power control module to transmit a first potential signal to the first control terminal of the mode control circuit.

[0022] The low-power control module transmits an entry stage timing signal to the second control terminal of the mode control circuit to control the central processing unit to gradually enter the low-power mode.

[0023] When the main control module receives an instruction to control the central processing unit to exit the low-power mode, it controls the low-power control module to transmit a second potential signal to the first control terminal of the mode control circuit.

[0024] When the potential at its first control terminal changes from a first potential signal to a second potential signal, the mode control circuit determines the stage in which the central processing unit enters the low-power mode based on the entry stage timing signal.

[0025] When the potential of its first control terminal is the second potential, the mode control circuit controls the central processing unit to exit the low-power mode from the stage in which it entered the low-power mode.

[0026] According to another aspect of the present invention, a display device is provided, including a control system for exiting the low-power mode as described in any one of the above.

[0027] The control system for exiting low-power mode provided in this embodiment of the invention includes a central processing unit (CPU), a main control module, a low-power mode entry / exit control module, and a mode control circuit. The main control module is electrically connected to the low-power mode entry / exit control module, which is electrically connected to the first control terminal of the mode control circuit. When the main control module receives an instruction to control the CPU to enter low-power mode, it controls the low-power mode entry / exit control module to transmit a first potential signal to the first control terminal. The low-power mode entry / exit control module is also electrically connected to the second control terminal of the mode control circuit. The low-power mode entry / exit control module transmits an entry stage timing signal to the second control terminal to control the CPU to gradually enter low-power mode. When the main control module receives an instruction to control the CPU to exit low-power mode, it controls the low-power mode entry / exit control module to transmit a second potential signal to the first control terminal. When the potential at its first control terminal changes from the first potential signal to the second potential signal, the mode control circuit determines the stage in which the CPU is entering low-power mode based on the entry stage timing signal. The mode control circuit also controls the CPU to exit low-power mode from the stage it was in when it entered low-power mode when the potential at its first control terminal is the second potential signal. The mode control circuit determines the stage the central processing unit was in when entering low-power mode upon receiving the instruction to exit low-power mode, and directly executes the exit from the last stage. This avoids having to complete all the steps to enter low-power mode before executing the exit process, shortening the exit time and improving the response speed of the control system.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a control system for exiting low-power mode provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of another control system for exiting low-power mode provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of another control system for exiting low-power mode provided in an embodiment of the present invention;

[0033] Figure 4 This is a driving timing diagram of a control system for exiting low-power mode provided in an embodiment of the present invention;

[0034] Figure 5 This is a flowchart of a control method for exiting low-power mode provided by an embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Figure 1 This is a schematic diagram of a control system for exiting low-power mode according to an embodiment of the present invention, with reference to... Figure 1 The control system for exiting low-power mode is characterized by comprising: a central processing unit 1, a main control module 2, a low-power mode entry / exit control module 3, and a mode control circuit 4.

[0038] The main control module 2 is electrically connected to the low-power mode entry / exit control module 3, and the low-power mode entry / exit control module 3 is electrically connected to the first control terminal A1 of the mode control circuit 4. When the main control module 2 receives an instruction to control the central processing unit 1 to enter the low-power mode, it controls the low-power mode entry / exit control module 3 to transmit a first potential signal to the first control terminal A1. The low-power mode entry / exit control module 3 is also electrically connected to the second control terminal A2 of the mode control circuit 4. The low-power mode entry / exit control module 3 is used to transmit an entry stage timing signal to the second control terminal A2 to control the central processing unit 1 to gradually enter the low-power mode.

[0039] The main control module 2 is also used to control the low-power control module 3 to transmit a second potential signal to the first control terminal A1 when it receives an instruction to control the central processing unit 1 to exit the low-power mode.

[0040] When the potential of its first control terminal A1 changes from the first potential signal to the second potential signal, the mode control circuit 4 determines the stage in which the central processing unit 1 enters the low-power mode based on the entry stage timing signal.

[0041] The mode control circuit 4 is also used to control the central processing unit 1 to exit the low power mode from the stage of entering the low power mode when the potential of its first control terminal A1 is the second potential.

[0042] For example, when the control system for exiting low-power mode in this embodiment is applied to a display device such as a mobile phone, tablet, or smartwatch, the main control module 2 is also connected to the touch module of the display device. The instruction to control the central processing unit 1 to enter low-power mode can be a trigger signal generated when the touch module does not receive any touch operation within a set time. The instruction to control the central processing unit 1 to exit low-power mode is a trigger signal generated when the touch module receives a touch operation.

[0043] For example, the first terminal of the low-power control module 3 is electrically connected to the first control terminal A1 of the mode control circuit 4, and the second terminal of the low-power control module 3 is electrically connected to the second control terminal A2 of the mode control circuit 4. Optionally, the main control module 2 is also electrically connected to the central processing unit 1, and the output terminal of the central processing unit 1 is electrically connected to the third control terminal A3 of the mode control circuit 4. When the main control module 2 receives an instruction to control the central processing unit 1 to enter the low-power mode, it controls the central processing unit 1 to transmit a first potential signal to the third control terminal A3 of the mode control circuit 4. When the main control module 2 detects that the central processing unit 1 has transmitted the first potential signal to the third control terminal A3 of the mode control circuit 4, it controls the low-power control module 3 to transmit an entry stage timing signal to the second control terminal A2 of the mode control circuit 4. The central processing unit 1 can enter the low-power mode in multiple stages sequentially. In this embodiment, the entry stage timing signal is used to characterize the process of entering the low-power mode, that is, executing one stage of entering the low-power mode corresponds to one pulse. For example, entering low-power mode involves five stages, each corresponding to a different operation, such as the CPU 1 controlling the closing of different switching devices. If the main control module 2 does not receive any instruction to exit low-power mode during the process of entering low-power mode, the CPU 1 will execute the operations corresponding to the five stages sequentially to fully enter low-power mode. Accordingly, the entry stage timing signal includes five pulse counts. If the main control module 2 receives an instruction to exit low-power mode during the process of controlling the CPU 1 to enter low-power mode, it controls the low-power mode entry / exit control module 3 to transmit a second potential signal to the second control terminal A2 of the mode control circuit 4. At this time, the entry stage timing signal output by the low-power mode entry / exit control module 3 becomes the second potential signal and no longer outputs pulses. The mode control circuit 4 counts the pulses in the entry stage timing signal until the potential of its second control terminal A2 is the second potential signal, at which point the counting ends. The number of pulses in the entry stage timing signal is equal to the number of stages executed by the CPU 1 when entering low-power mode. For example, when an instruction to exit low-power mode is received during the fourth stage of entering low-power mode, the mode control circuit 4 determines that the central processing unit 1 is in the fourth stage of entering low-power mode based on the count value. The mode control circuit 4 then controls the central processing unit 1 to exit low-power mode from the determined stage. For instance, if the stage of entering low-power mode is the fourth stage, the mode control circuit 4 controls the central processing unit to exit low-power mode sequentially from the fourth stage, that is, sequentially disconnecting the switch closed in the fourth stage, disconnecting the switch closed in the third stage, closing the switch open in the second stage, and closing the switch open in the first stage to exit low-power mode.The first potential signal and the second potential signal can be opposite potentials; the first potential signal can be high level and the second potential signal can be low level.

[0044] The mode control circuit determines the stage the central processing unit (CPU) was in when it entered low-power mode when it received the instruction to exit low-power mode. It then directly executes the exit from the last stage, thus avoiding the need to complete all the stages of entering low-power mode before executing the exit process. This shortens the time to exit low-power mode and improves the response speed of the control system.

[0045] Figure 2 This is a schematic diagram of another control system for exiting low-power mode provided in an embodiment of the present invention, with reference to... Figure 2 Optionally, the mode control circuit 4 includes a memory circuit 41 and a wake-up circuit 42. The first input terminal of the memory circuit 41 serves as the third control terminal A3 of the mode control circuit 4, the second input terminal of the memory circuit 41 serves as the first control terminal A1 of the mode control circuit 4, the third input terminal of the memory circuit 41 serves as the second control terminal A2 of the mode control circuit 4, the fourth input terminal of the memory circuit 41 is electrically connected to the low-power control module 3, and the output terminal B1 of the memory circuit 41 is electrically connected to the low-power control module 3. The memory circuit 41 is used to determine the stage in which the central processing unit 1 enters the low-power mode based on the potential of its second input terminal and the entry stage timing signal when the potential of its first input terminal is the first potential signal. The low-power control module 3 is used to generate an exit timing signal based on the stage in which the central processing unit 1 enters the low-power mode. The memory circuit 41 is used to control the central processing unit 1 to exit the low-power mode based on the potential of its second input terminal and the exit timing signal when the potential of its first input terminal is the first potential signal.

[0046] The first input terminal C1 of the wake-up circuit 42 is electrically connected to the output terminal of the central processing unit 1, and the second input terminal C2 of the wake-up circuit 42 is electrically connected to the first output terminal of the main control module 2. When the main control module 2 receives an instruction to control the central processing unit to enter a low-power mode, it transmits a first potential signal to the second input terminal C2 of the wake-up circuit 42. The third input terminal C3 of the wake-up circuit 42 is electrically connected to the second output terminal of the main control module 2. The control terminal C4 of the wake-up circuit 42 is electrically connected to the output terminal B1 of the memory circuit 41, and the output terminal C5 of the wake-up circuit 42 is electrically connected to the central processing unit 1. When the main control module 2 receives an instruction to control the central processing unit 1 to exit the low-power mode, it transmits a first potential signal to the third input terminal C3 of the wake-up circuit 42. The wake-up circuit 42 generates a wake-up signal based on the potentials of its first input terminal C1, second input terminal C2, and third input terminal C3 to control the central processing unit 1 to exit the low-power mode.

[0047] Optionally, the mode control circuit 4 further includes a fourth control terminal A4 electrically connected to the low-power mode control module 3, with the fourth input terminal of the memory circuit 41 serving as the fourth control terminal A4 of the mode control circuit 4. The memory circuit 41 counts the number of pulses of the entry phase timing signal when both its first and second input terminals are at the first potential signal. The stage in which the central processing unit 1 enters the low-power mode is the counted number of pulses. The low-power mode control module 3 generates an exit timing signal based on the counted number of pulses divided by the stage in the low-power mode. The number of pulses in the entry phase timing signal is the same as the number of pulses in the exit timing signal, so that the central processing unit 1 exits the low-power mode gradually according to the stages executed during entry. The entry phase timing signal includes m pulses, and the nth pulse of the entry phase timing signal has the same shape as the (m-n+1)th pulse of the exit timing signal, where m and n are both positive integers, and n is less than m. For example, if the entry phase timing signal includes four pulses, then the CPU 1 executes four stages of entering low-power mode. In the fourth stage, the main control module 2 receives an instruction to control the CPU to exit low-power mode. The low-power mode entry / exit control module 3 generates an exit timing signal based on the pulse count signal output by the memory circuit 41. The first pulse of the exit timing signal is the same as the fourth pulse of the entry phase timing signal, the second pulse of the exit timing signal is the same as the third pulse of the entry phase timing signal, the third pulse of the exit timing signal is the same as the second pulse of the entry phase timing signal, and the fourth pulse of the exit timing signal is the same as the first pulse of the entry phase timing signal. This ensures that when exiting low-power mode, the CPU 1 exits sequentially from the fourth stage. The wake-up circuit 42 is used to subtract the number of pulses from the exit timing signal based on the counted pulse count. Each time an exit timing signal pulse passes, the pulse count value at the output of the wake-up circuit 42 decreases by one until it reaches 0. At this point, the memory circuit 41 generates a wake-up signal.

[0048] Figure 3 This is a schematic diagram of another control system for exiting low-power mode provided in an embodiment of the present invention, with reference to... Figure 3Optionally, the memory circuit 41 includes a first unit 411 and a second unit 412. The first unit 411 includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the first unit 411 serves as the first input terminal of the memory circuit 41, the second terminal of the first unit 411 serves as the second input terminal of the memory circuit 41, the third terminal of the first unit 411 serves as the third input terminal of the memory circuit 41, and the fourth terminal of the first unit 411 serves as the fourth input terminal of the memory circuit 41. The output terminal of the first unit 411 is electrically connected to the input terminal of the second unit 412. The first unit 411 is used to transmit an entry stage timing signal to the input terminal of the second unit 412 when the potential of its first terminal is a first potential signal and the potential of its second terminal is a first potential signal. The first unit 411 is also used to transmit an exit timing signal to the input terminal of the second unit 412 when the potential of its first terminal is a first potential signal and the potential of its second terminal is a second potential signal.

[0049] The control terminal of the second unit 412 is electrically connected to the second terminal of the first unit 411. The second unit 412 is used to count the number of pulses of the entry phase timing signal when the potential of its own control terminal is the first potential; it is also used to control the wake-up circuit 42 to generate a wake-up signal according to the counted number of pulses of the entry phase timing signal and the number of pulses of the exit phase timing signal when the potential of its own control terminal is the second potential.

[0050] Continue to refer to Figure 3The first end of the first unit 411 serves as the first input terminal of the memory circuit 41, which is also the third control terminal A3 of the mode control circuit 4. The second end of the first unit 411 serves as the second input terminal of the memory circuit 41, which is also the first control terminal A1 of the mode control circuit 4. The third end of the first unit 411 serves as the third input terminal of the memory circuit 41, which is also the second control terminal A2 of the mode control circuit 4. The fourth end of the first unit 411 serves as the fourth input terminal of the memory circuit 41, which is also the fourth control terminal A4 of the mode control circuit 4. When the first unit 411 has a first potential signal at its first terminal, it transmits one of the entry phase timing signal and the exit timing signal to the input terminal of the second unit 412 based on the potential of its second terminal. Specifically, when its second terminal has a first potential signal, i.e., the central processing unit 1 is in a low-power mode, it transmits the entry phase timing signal to the input terminal of the second unit 412. When its second terminal has a second potential signal, i.e., the central processing unit 1 is in a low-power mode exit, it transmits the exit timing signal to the input terminal of the second unit 412. When the second unit 412 has a first potential signal at its control terminal, it counts the number of pulses of the entry phase timing signal. That is, for each pulse of the entry phase timing signal, the value output by the output terminal of the second unit 412 is incremented by 1 until the potential of the control terminal of the second unit 412 changes to the second potential signal, at which point the counting of the number of pulses of the entry phase timing signal ends. When the potential at the control terminal of the second unit 412 is the second potential signal, based on the number of pulses of the entry phase timing signal of the count, for each pulse of the exit timing signal, the value output by the output terminal of the second unit 412 is reduced by 1 until the value output by the output terminal of the second unit 412 is 0, at which point the wake-up circuit 42 is controlled to generate a wake-up signal.

[0051] Continue to refer to Figure 3 Optionally, the first unit 411 includes a first selector 4111 and a first AND gate 4112, and the second unit 412 includes a counter 4121;

[0052] The first input terminal of the first selector 4111 serves as the third terminal of the first unit 411, the second input terminal of the first selector 4111 serves as the fourth terminal of the first unit 411, and the control terminal of the first selector 4111 serves as the second terminal of the first unit 411. The output terminal of the first selector 4111 is electrically connected to the first input terminal of the first AND gate 4112, the second input terminal of the first AND gate 4112 serves as the first terminal of the first unit 411, and the output terminal of the first AND gate 4112 is electrically connected to the input terminal of the counter 4121. The control terminal of the counter 4121 serves as the control terminal of the second unit 412, and the output terminal of the counter 4121 serves as the output terminal of the second unit 412. The counter 4121 includes an adder counter and a subtractor counter. The counter 4121 is used to perform addition calculations based on the entry phase timing signal when its own control terminal is a first potential signal, and also to perform subtraction calculations based on the exit timing signal when its own control terminal is a second potential signal.

[0053] The first input terminal of the first selector 4111 serves as the third terminal of the first unit 411, which is also the second control terminal A2 of the mode control circuit 4. The second input terminal of the first selector 4111 serves as the fourth terminal of the first unit 411, which is also the fourth control terminal A4 of the mode control circuit 4. The control terminal of the first selector 4111 serves as the second terminal of the first unit 411, which is also the first control terminal A1 of the mode control circuit 4. The second input terminal of the first AND gate 4112 serves as the first terminal of the first unit 4111, which is also the third control terminal A3 of the mode control circuit 4.

[0054] Continue to refer to Figure 3Optionally, the memory circuit 41 also includes a register 413. The input terminal of register 413 is electrically connected to the output terminal B1 of the memory circuit 41. Register 413 is used to store the stage at which the central processing unit enters low-power mode. The memory circuit 41 also includes a third selector 414 electrically connected to the clock terminal of register 413. The first input terminal D1 of the third selector 414 is electrically connected to the first clock terminal K1 of the low-power control module 3 to receive the first clock signal. The second input terminal D2 of the third selector 414 is electrically connected to the second clock terminal K2 of the low-power control module 3 to receive the second clock signal. The control terminal D3 of the third selector 414 is electrically connected to the clock control terminal K3 of the low-power control module 3 to receive pulse control signals. When register 413 is working normally, it needs to input a pulse signal to its own clock terminal. As the process of entering low-power mode progresses, the first clock signal output by the low-power control module 3 will be pulled low, causing register 413 to fail to count normally. When the first clock signal is pulled low, the pulse control signal of the control output of the low-power control module 3 becomes low, thereby causing the clock signal at the input register 413 to switch from the first clock signal to the second clock signal. The second clock signal has a pulse signal both when entering and exiting the low-power mode, so as to ensure the normal operation of the register 413.

[0055] Continue to refer to Figure 3 Optionally, the wake-up circuit 42 includes a second AND gate 421, a third AND gate 422, and a second selector 423. The first input terminal of the second AND gate 421 serves as the second input terminal C2 of the wake-up circuit 42, and the second input terminal of the second AND gate 421 serves as the third input terminal C3 of the wake-up circuit 42. The output terminal of the second AND gate 421 is electrically connected to the first input terminal of the third AND gate 422, and the second input terminal of the third AND gate 422 serves as the first input terminal C1 of the wake-up circuit 42. The output terminal of the third AND gate 422 is electrically connected to the first input terminal of the second selector 423. The second input terminal V1 of the second selector 423 is connected to a fixed potential signal. The control terminal of the second selector 423 serves as the control terminal C4 of the wake-up circuit 42, and the output terminal of the second selector 423 serves as the output terminal C5 of the wake-up circuit 42.

[0056] The signal input to the second input terminal of the second AND gate 421 remains low during the process of entering low-power mode and before the action to exit low-power mode is executed, so that the signal output by the second selector 423 is low. This continues until the main control module 2 receives the instruction to control the central processing unit 1 to exit low-power mode. At this point, the signal input to the second input terminal of the second AND gate 421 becomes high, and the signal output by the second selector 423 becomes high. After the value output by the output terminal B1 of the memory circuit 41 becomes 0, the signal output by the second selector 423 becomes the fixed potential signal input to its own second input terminal, i.e., low, at which point the wake-up signal is generated. After receiving the wake-up signal, the central processing unit 1 transmits a low level to the third control terminal A3 of the control mode control circuit 4, thus completely exiting low-power mode.

[0057] It is worth noting that the working principle of the first selector 4111, the second selector 423, and the third selector 414 is the same: when the potential of its own control terminal is high, the selector outputs the signal input from the first input terminal; when the potential of its own control terminal is low, the selector outputs the signal input from the second input terminal.

[0058] Figure 4 This is a driving timing diagram of a control system exiting low-power mode provided in an embodiment of the present invention. Figure 4 The timing shown is applicable to Figure 3 The structure shown, and in Figure 3 In the structure shown, the first potential signal is high level, and the second potential signal is low level. The operation process of the control system exiting the low-power mode includes the first stage t1, the second stage t2, and the third stage t3.

[0059] At the start of the first stage t1, the main control module 2 receives an instruction to control the central processing unit 1 to enter low-power mode. It then controls the low-power control module 3 to transmit a high-level signal to the control terminal of the first selector 4111 (i.e., the first control terminal A1 of the mode control circuit 4) and the control terminal of the counter 4121. The main control module 2 controls the central processing unit 1 to execute the WFE instruction, causing the central processing unit 1 to input a high-level signal to the second input terminal of the first AND gate 4112 (i.e., the third control terminal A3 of the mode control circuit 4). The low-power control module 3 detects that the central processing unit... When the device outputs a high level to the second input of the first AND gate 4112, it transmits an entry stage timing signal to the first input of the first selector 4111 (i.e., the second control terminal A2 of the mode control circuit 4). Since the control terminal of the first selector 4111 is high, the input from the first selector 4111 to the second input of the first AND gate 4112 is the entry stage timing signal. The second input of the second AND gate 4112 is high throughout the first stage t1. Therefore, the signal output by the second AND gate 4112 to the counter 4121 is the same as the entry stage timing signal. The control terminal of the counter 4121 is high in the first stage t1, and the adder in the counter 4121 works to count the number of pulses of the entry stage timing signal. In the first stage t1, when the main control module 2 receives the instruction to control the central processing unit 1 to enter the low-power mode, the main control module 2 transmits a high level to the first input of the second AND gate 421 (i.e., the second input C2 of the wake-up circuit 42), and the high level continues until the end of the third stage t3. Simultaneously, the main control module 2 transmits a low level to the second input terminal of the second AND gate 421 (i.e., the third input terminal C3 of the wake-up circuit 42). The second AND gate 421 outputs a low level to the first input terminal of the third AND gate 422, and then the third AND gate 422 outputs a low level to the first input terminal of the second selector 423. The control terminal of the second selector 423 is connected to the output terminal of the counter 4121. That is, the control terminal is connected to the number of pulses of the timing signal of the counting entry stage. In other words, the potential of the control terminal is not 0, and the output terminal of the second selector 423 (i.e., the output terminal C5 of the wake-up circuit 42) outputs a low level. As the process gradually enters the low-power mode, at the third pulse of the entry phase timing signal, which is the third stage of the entry process, the first clock signal output by the first clock terminal K1 of the low-power control module 3 is pulled low. At this time, the level transmitted from the low-power control module 3 to the control terminal D3 of the third selector 414 changes from high to low, so that the third selector 414 transmits the second clock signal output by the second clock terminal K2 of the low-power control module 3 to the clock terminal of the register 413, so as to ensure that the register is controlled by the pulse, thereby ensuring the normal operation of the register 413.

[0060] At the start of the second stage t2, when the main control module 2 receives the instruction to control the central processing unit 1 to exit the low-power mode, it controls the low-power mode entry / exit control module 3 to transmit a low level to the control terminal of the first selector 4111 and the control terminal of the counter 4121, and controls the low-power mode entry / exit control module 3 to read the number of pulses of the count entry stage timing signal stored in the register 413 at this time. In this embodiment, the number of pulses is 4. The low-power mode entry / exit control module 3 determines the stage of the central processing unit 1 entering the low-power mode based on the number of pulses of the count entry stage timing signal and generates an exit timing signal, which is transmitted to the second input terminal of the first selector 4111. The control terminal of the first selector 4111 is at a low level, so the first selector 4111 transmits the exit timing signal to the first AND gate 4112, and the first AND gate 4112 transmits the exit timing signal to the counter 4121. The central processing unit executes the process of exiting the low-power mode. The potential of the control terminal of the counter 4121 is low, and the subtractor works. Counter 4121 performs subtraction calculations based on the exit timing signal. For each pulse signal, the count is reduced by one from the final count of pulses by the adder. After receiving the instruction to exit low-power mode, the main control module 2 transmits a high level to the second input of the second AND gate 421. The second AND gate 421 then inputs a high level to the first input of the third AND gate 422. In the second stage t2, the central processing unit 1 transmits a high level to the second input of the third AND gate 422. The third AND gate 422 then inputs a high level to the first input of the second selector 423. The potential at the control terminal of the second selector 423 is greater than 0, causing the output of the second selector 423 to output a high level to the central processing unit 1. As the low-power mode exits, at the low level of the first pulse of the signal input to the fourth control terminal A4 of the exit timing signal (i.e., the mode control circuit 4), the first clock signal output by the low-power control module 3 recovers. Therefore, the low-power control module 3 transmits a high level to the control terminal D3 of the third selector 414, so that the third selector 414 transmits the first clock signal input to its first input terminal D1 to the clock terminal of the register 413. The register 413 then operates normally under the control of the first clock signal.

[0061] In the third stage t3, when the last pulse of the exit timing signal arrives, the output value of counter 4121 is 0, so the control terminal of second selector 423 is low, and second selector 423 outputs a fixed potential signal (low level) from its second input terminal V1 to central processing unit 1. At this point, the output terminal of second selector 423 generates a wake-up signal (i.e., a low-high-low pulse signal). After receiving the wake-up signal, central processing unit 1 transmits a low level to the control terminals of first selector 4111 and counter 4121. After receiving the wake-up signal, the process of central processing unit 1 exiting low-power mode is complete.

[0062] This invention also provides a control method for exiting a low-power mode, used to control any of the aforementioned control systems that exit a low-power mode. Figure 5 A flowchart of a control method for exiting a low-power mode provided in an embodiment of the present invention is shown. The control method includes:

[0063] S10: When the main control module receives the instruction to control the central processing unit to enter the low-power mode, it controls the low-power control module to transmit the first potential signal to the first control terminal of the mode control circuit.

[0064] S20: The low-power control module transmits the entry stage timing signal to the second control terminal of the mode control circuit to control the central processing unit to gradually enter the low-power mode.

[0065] S30: When the main control module receives an instruction to control the central processing unit to exit the low-power mode, it controls the low-power control module to transmit a second potential signal to the first control terminal of the mode control circuit.

[0066] S40: When the potential of its first control terminal changes from the first potential signal to the second potential signal, the mode control circuit determines the stage in which the central processing unit enters the low-power mode based on the entry stage timing signal.

[0067] S50: When the potential of its first control terminal is the second potential, the mode control circuit controls the central processing unit to exit the low-power mode from the stage in which it entered the low-power mode.

[0068] The control method for exiting low-power mode has the same beneficial effects as the control system for exiting low-power mode, and will not be described again in this embodiment.

[0069] This invention also provides a display device including any of the aforementioned control systems for exiting low-power modes. The display device can be a mobile phone, tablet, smartwatch, or other similar device. The beneficial effects of the display device are the same as those of the control system for exiting low-power modes, and will not be repeated here.

[0070] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0071] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A control system for exiting a low power mode, characterized by, include: Central processing unit, main control module, input / output low-power control module and mode control circuit, The main control module is electrically connected to the low-power mode entry / exit control module, and the low-power mode entry / exit control module is electrically connected to the first control terminal of the mode control circuit. When the main control module receives an instruction to control the central processing unit to enter a low-power mode, it controls the low-power mode entry / exit control module to transmit a first potential signal to the first control terminal. The low-power mode entry / exit control module is also electrically connected to the second control terminal of the mode control circuit, and the low-power mode entry / exit control module is used to transmit an entry stage timing signal to the second control terminal to control the central processing unit to gradually enter a low-power mode. The main control module is also used to control the low-power mode entry / exit control module to transmit a second potential signal to the first control terminal when it receives an instruction to control the central processing unit to exit the low-power mode. The mode control circuit is used to determine the stage in which the central processing unit enters the low-power mode based on the entry stage timing signal when the potential at its first control terminal changes from a first potential signal to a second potential signal. The mode control circuit is also used to control the central processing unit to exit the low-power mode from the stage of entering the low-power mode when the potential of its first control terminal is the second potential.

2. The control system for exiting a low power mode of claim 1, wherein, The mode control circuit includes a memory circuit and a wake-up circuit. The first input terminal of the memory circuit serves as the third control terminal of the mode control circuit, the second input terminal of the memory circuit serves as the first control terminal of the mode control circuit, the third input terminal of the memory circuit serves as the second control terminal of the mode control circuit, and the fourth input terminal of the memory circuit is electrically connected to the low-power control module. The memory circuit is used to determine the stage in which the central processing unit enters the low-power mode based on the potential of its second input terminal and the entry stage timing signal when the potential of its first input terminal is a first potential signal. The low-power mode entry / exit control module is used to generate an exit timing signal according to the stage at which the central processing unit enters the low-power mode. The memory circuit is used to control the central processing unit to exit the low-power mode according to the potential of its second input terminal and the exit timing signal when the potential of its first input terminal is the first potential signal. The output terminal of the central processing unit is electrically connected to the third control terminal of the mode control circuit. The first input terminal of the wake-up circuit is electrically connected to the output terminal of the central processing unit (CPU), and the second input terminal of the wake-up circuit is electrically connected to the first output terminal of the main control module. When the main control module receives an instruction to control the CPU to enter a low-power mode, it transmits the first potential signal to the second input terminal of the wake-up circuit. The third input terminal of the wake-up circuit is electrically connected to the second output terminal of the main control module. The control terminal of the wake-up circuit is electrically connected to the output terminal of the memory circuit, and the output terminal of the wake-up circuit is electrically connected to the CPU. When the main control module receives an instruction to control the CPU to exit the low-power mode, it transmits the first potential signal to the third input terminal of the wake-up circuit. The wake-up circuit generates a wake-up signal based on the potentials of its first, second, and third input terminals to control the CPU to exit the low-power mode.

3. The control system for exiting a low power mode of claim 2, wherein, The memory circuit includes a first unit and a second unit. The first unit includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the first unit serves as the first input terminal of the memory circuit, the second terminal of the first unit serves as the second input terminal of the memory circuit, the third terminal of the first unit serves as the third input terminal of the memory circuit, and the fourth terminal of the first unit serves as the fourth input terminal of the memory circuit. The output terminal of the first unit is electrically connected to the input terminal of the second unit. The first unit is used to transmit the entry stage timing signal to the input terminal of the second unit when the potential of its first terminal is a first potential signal and the potential of its second terminal is the first potential signal. The first unit is also used to transmit the exit timing signal to the input terminal of the second unit when the potential of its first terminal is the first potential signal and the potential of its second terminal is the second potential signal. The control terminal of the second unit is electrically connected to the second terminal of the first unit. The second unit is used to count the number of pulses of the entry phase timing signal when the potential of its own control terminal is the first potential, and is also used to control the wake-up circuit to generate a wake-up signal according to the counted number of pulses of the entry phase timing signal and the number of pulses of the exit timing signal when the potential of its own control terminal is the second potential.

4. The control system for exiting a low power mode of claim 3, wherein, The number of pulses in the entry phase timing signal is the same as the number of pulses in the exit phase timing signal.

5. The control system for exiting low-power mode according to claim 4, characterized in that, The entry phase timing signal includes m pulses. The nth pulse of the entry phase timing signal has the same shape as the (m-n+1)th pulse of the exit timing signal, where m and n are both positive integers and n is less than m.

6. The control system for exiting a low power mode of claim 3, wherein, The first unit includes a first selector and a first AND gate, and the second unit includes a counter; The first input terminal of the first selector serves as the third terminal of the first unit, the second input terminal of the first selector serves as the fourth terminal of the first unit, the control terminal of the first selector serves as the second terminal of the first unit, the output terminal of the first selector is electrically connected to the first input terminal of the first AND gate, the second input terminal of the first AND gate serves as the first terminal of the first unit, the output terminal of the first AND gate is electrically connected to the input terminal of the counter, the control terminal of the counter serves as the control terminal of the second unit, and the output terminal of the counter serves as the output terminal of the second unit.

7. The control system for exiting a low power mode of claim 3, wherein, The memory circuit also includes a register, the input of which is electrically connected to the output of the memory circuit, and the register is used to store the stage in which the central processing unit enters the low-power mode.

8. The control system for exiting a low power mode of claim 3, wherein, The wake-up circuit includes a second AND gate, a third AND gate, and a second selector. The first input terminal of the second AND gate serves as the second input terminal of the wake-up circuit, and the second input terminal of the second AND gate serves as the third input terminal of the wake-up circuit. The output terminal of the second AND gate is electrically connected to the first input terminal of the third AND gate, and the second input terminal of the third AND gate serves as the first input terminal of the wake-up circuit. The output terminal of the third AND gate is electrically connected to the first input terminal of the second selector. A fixed potential signal is connected to the second input terminal of the second selector. The control terminal of the second selector serves as the control terminal of the wake-up circuit, and the output terminal of the second selector serves as the output terminal of the wake-up circuit.

9. A control method of exiting a low power consumption mode, characterized by, A control system for controlling the exit from the low-power mode as described in any one of claims 1-8, the control method comprising: When the main control module receives an instruction to control the central processing unit to enter low-power mode, it controls the low-power control module to transmit a first potential signal to the first control terminal of the mode control circuit. The low-power control module transmits an entry stage timing signal to the second control terminal of the mode control circuit to control the central processing unit to gradually enter the low-power mode. When the main control module receives an instruction to control the central processing unit to exit the low-power mode, it controls the low-power control module to transmit a second potential signal to the first control terminal of the mode control circuit. When the potential at its first control terminal changes from a first potential signal to a second potential signal, the mode control circuit determines the stage in which the central processing unit enters the low-power mode based on the entry stage timing signal. When the potential of its first control terminal is the second potential, the mode control circuit controls the central processing unit to exit the low-power mode from the stage in which it entered the low-power mode.

10. A display device, characterized by comprising: The control system for exiting low-power mode as described in any one of claims 1-8.

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