A two-stage operational amplifier voltage regulation circuit and electronic equipment

Abstract

This invention discloses a two-stage operational amplifier voltage regulation circuit, comprising: based on a conventional two-stage operational amplifier with N-transistors (first and second field-effect transistors), an additional NT-transistor (third and fourth field-effect transistors) input, and a first switch, a second switch, a third switch, and a fourth switch. When the input voltage is greater than a preset voltage, the first and second switches are turned off, allowing the N-transistor to conduct; or, when the input voltage is not greater than the preset voltage, the third and fourth switches are turned off, allowing the NT-transistor to conduct. This can increase the common-mode input voltage range to 2V. dsat This reduces circuit area and power consumption.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more particularly to a two-stage operational amplifier voltage regulation circuit and electronic equipment. Background Technology

[0002] To increase the input common-mode voltage range, traditional NMOS differential input dual-stage op-amps can only choose a folded cascode structure, where both PMOS and NMOS are used as inputs. This rail-to-rail input folded cascode structure will greatly increase the area. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a two-stage operational amplifier voltage regulation circuit and an electronic device that reduces circuit area and power consumption.

[0004] Specifically, the technical solution of the present invention is as follows:

[0005] A two-stage operational amplifier voltage regulation circuit includes:

[0006] First power supply, second power supply, first field-effect transistor, second field-effect transistor, third field-effect transistor, fourth field-effect transistor, first switch, second switch, third switch, fourth switch, first circuit and second circuit;

[0007] The gate of the first field-effect transistor is connected to the first power supply, the drain of the first field-effect transistor is connected to the input terminal of the first circuit, the source of the first field-effect transistor is connected to one end of the first switch, and the other end of the first switch is connected to the input terminal of the second circuit.

[0008] The gate of the second field-effect transistor is connected to the second power supply, the drain of the second field-effect transistor is connected to the input terminal of the first circuit, the source of the second field-effect transistor is connected to one end of the second switch, and the other end of the second switch is connected to the input terminal of the second circuit.

[0009] The gate of the third field-effect transistor is connected to the first power supply, the drain of the third field-effect transistor is connected to the input terminal of the first circuit, the source of the third field-effect transistor is connected to one end of the third switch, and the other end of the third switch is connected to the input terminal of the second circuit.

[0010] The gate of the fourth field-effect transistor is connected to the second power supply, the drain of the fourth field-effect transistor is connected to the input terminal of the first circuit, the source of the fourth field-effect transistor is connected to one end of the fourth switch, and the other end of the fourth switch is connected to the input terminal of the second circuit.

[0011] Compared to traditional solutions, this only adds two MOSFETs and four switches, reducing circuit area and power consumption.

[0012] In some implementations...

[0013] When the secondary operational amplifier voltage regulation circuit is in boost mode, the first switch and the second switch are both closed, the third switch and the fourth switch are both open, and the first field-effect transistor and the second field-effect transistor are turned on. The boost mode is to increase the input voltage of the first power supply and the second power supply.

[0014] In some implementations...

[0015] When the secondary operational amplifier voltage regulation circuit is in boost mode, the third switch and the fourth switch are both closed, the first switch and the second switch are both open, and the third field-effect transistor and the fourth field-effect transistor are turned on. The boost mode is to increase the input voltage of the first power supply and the second power supply.

[0016] In some embodiments, the second circuit includes:

[0017] The fifth field-effect transistor has its gate connected to an external power supply, its source grounded, and its drain connected to the first switch, the second switch, the third switch, and the fourth switch, respectively.

[0018] In some embodiments, the second circuit further includes:

[0019] The sixth field-effect transistor has its gate connected to the external power supply, its source grounded, and its drain connected to the input terminal of the first circuit.

[0020] In some embodiments, the first circuit includes:

[0021] The seventh field-effect transistor has its drain connected to a third power supply, its source connected to the drains of the first and third field-effect transistors respectively, and its gate connected to the source of the seventh field-effect transistor.

[0022] The eighth field-effect transistor has its drain connected to the third power supply, its source connected to the drain of the second field-effect transistor, and its gate connected to the gate and source of the seventh field-effect transistor.

[0023] In some implementations, it also includes:

[0024] The ninth field-effect transistor has its drain connected to the third power supply, and its source connected to the drain of the sixth field-effect transistor and the first power supply, respectively. The gate of the seventh field-effect transistor is connected to the drain of the fourth field-effect transistor and the source of the eighth field-effect transistor, respectively.

[0025] In some embodiments, the first and second field-effect transistors are N-type field-effect transistors; the third and fourth field-effect transistors are NT-type field-effect transistors.

[0026] In some embodiments, the seventh and eighth field-effect transistors are P-type field-effect transistors.

[0027] The present invention also provides an electronic device using a two-stage operational amplifier voltage regulation circuit, including the two-stage operational amplifier voltage regulation circuit described in the foregoing embodiments.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] This design adds a third and fourth MOSFET, a first switch, a second switch, a third switch, and a fourth switch. When the input voltage exceeds a preset voltage, the third and fourth switches are turned off, allowing the first and second MOSFETs to conduct, thus increasing the common-mode voltage range. Alternatively, when the input voltage is not greater than the preset voltage, the first and second switches are turned off, allowing the third and fourth MOSFETs to conduct, further increasing the common-mode voltage range. Compared to traditional solutions, this design only adds two MOSFETs and four switches, reducing circuit area and power consumption. Attached Figure Description

[0030] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.

[0031] Figure 1 This is a structural diagram of an embodiment of a two-stage operational amplifier voltage regulation circuit according to the present invention;

[0032] Figure 2 This is a structural diagram of a traditional NMOS transistor differential input two-stage operational amplifier circuit; Attached image description:

[0034] Third power supply 110; First circuit 100; Second circuit 200. Detailed Implementation

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0036] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0037] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0038] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0039] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0041] Traditional NMOS transistor differential input two-stage operational amplifier circuit, such as Figure 2 As shown, the NMOS is the input pair transistor, and the input common-mode voltage range is V. THN +2V dsatIf the voltage is below this value, NM1 and NM2 will enter the linear region, causing the op-amp to malfunction. To increase the input common-mode voltage range, a folded cascode structure must be selected, using both PMOS and NMOS as inputs. This rail-to-rail input folded cascode structure will significantly increase the area.

[0042] To address the aforementioned technical problems, this invention proposes a method for increasing the input voltage range of an N-transistor input two-stage operational amplifier, as detailed in the appendix to the specification. Figure 1 Based on the traditional N-stage operational amplifier (first and second field-effect transistors), an NT-stage transistor (third and fourth field-effect transistors) input is added. When the input voltage is less than V... THN +2V dsat When the switch is selected to use the NT transistor as the input, and the input voltage is greater than V... THN +2V dsat When switching, the N-channel transistor is selected as the input. This can increase the common-mode input voltage range to 2V. dsat The area only increases by two NT transistors and four switches. THN +V dsat y is the turn-on voltage of the input NMOS transistor. gs It needs to be greater than V THN +V dsat Only then can saturation occur, another V dsat This is the saturation drain-source voltage of NM5. Only when this voltage is greater than this will the MOSFET be in the saturation region.

[0043] The specific plan is as follows:

[0044] In one embodiment, such as Figure 1 As shown, the present invention provides a two-stage operational amplifier voltage regulation circuit, comprising the following steps:

[0045] First power supply, second power supply, first field-effect transistor, second field-effect transistor, third field-effect transistor, fourth field-effect transistor, first switch, second switch, third switch, fourth switch, first circuit and second circuit.

[0046] The gate of the first field-effect transistor is connected to the first power supply, the drain of the first field-effect transistor is connected to the input terminal of the first circuit, the source of the first field-effect transistor is connected to one end of the first switch, and the other end of the first switch is connected to the input terminal of the second circuit.

[0047] The gate of the second field-effect transistor is connected to the second power supply, the drain of the second field-effect transistor is connected to the input terminal of the first circuit, the source of the second field-effect transistor is connected to one end of the second switch, and the other end of the second switch is connected to the input terminal of the second circuit.

[0048] The gate of the third field-effect transistor is connected to the first power supply, the drain of the third field-effect transistor is connected to the input terminal of the first circuit, the source of the third field-effect transistor is connected to one end of the third switch, and the other end of the third switch is connected to the input terminal of the second circuit.

[0049] The gate of the fourth field-effect transistor is connected to the second power supply, the drain of the fourth field-effect transistor is connected to the input terminal of the first circuit, the source of the fourth field-effect transistor is connected to one end of the fourth switch, and the other end of the fourth switch is connected to the input terminal of the second circuit.

[0050] Specifically, the first field-effect transistor (see attached document) Figure 1 The gate of NM1 in the reference is connected to the first power supply (see attached). Figure 1 The first field-effect transistor (FET) is connected to the input terminal of the first circuit 100, and the source of the first FET is connected to the first switch (see attached diagram). Figure 1 One end of the first switch (SW1) is connected, and the other end of the first switch is connected to the input terminal of the second circuit 200.

[0051] Second field-effect transistor (see attached) Figure 1 The gate of NM2 and the second power supply (see attached diagram) Figure 1 The first circuit 100 has its Vinp terminal connected to the first circuit 100, and its drain is connected to the input terminal of the second field-effect transistor. The source of the second field-effect transistor is connected to the second switch (see attached diagram). Figure 1 One end of SW2 is connected to the circuit, and the other end of the second switch is connected to the input terminal of the second circuit 200.

[0052] The first field-effect transistor, the second field-effect transistor, the first switch, the second switch, the first power supply, and the second power supply together form a circuit that increases the common-mode voltage range.

[0053] Furthermore, the third field-effect transistor (see attached document) Figure 1 The gate of the NTM1 transistor is connected to the first power supply, the drain of the third field-effect transistor is connected to the input terminal of the first circuit, and the source of the third field-effect transistor is connected to the third switch (see attached diagram). Figure 1 One end of SW3 is connected, and the other end of the third switch is connected to the input terminal of the second circuit.

[0054] Fourth field-effect transistor (see attached) Figure 1 The gate of the NTM2 is connected to the second power supply, the drain of the fourth field-effect transistor is connected to the input terminal of the first circuit, and the source of the fourth field-effect transistor is connected to the fourth switch (see attached diagram). Figure 1 One end of SW4 is connected, and the other end of the fourth switch is connected to the input of the second circuit.

[0055] The third field-effect transistor, the fourth field-effect transistor, the third switch, the fourth switch, the first power supply, and the second power supply together form another circuit that increases the common-mode voltage range.

[0056] Furthermore, when the input voltage of the first power supply and the second power supply is greater than the preset voltage (the preset voltage is 1V or V), THN +2V dsat When the third and fourth switches are disconnected, and the first and second switches are closed, the first and second field-effect transistors are turned on, thereby increasing the common-mode voltage range to 2V. dsat This means that the two-stage operational amplifier voltage regulation circuit is in a boosting state.

[0057] When the input voltage of the first and second power supplies is not greater than the preset voltage, the first and second switches are disconnected, and the third and fourth switches are closed, causing the third and fourth field-effect transistors to conduct, thereby increasing the common-mode voltage range to 2V. dsat This means the two-stage operational amplifier voltage regulation circuit is in boost mode. The common-mode input voltage range is increased to 2Vdsat by using an NT transistor as the input because the Vth of the NT transistor is close to 0.

[0058] The method of increasing the common-mode voltage in this embodiment only adds two MOSFETs and four switches compared to the traditional solution, thus reducing the circuit area and power consumption.

[0059] In one embodiment, such as Figure 1 As shown, the present invention provides a two-stage operational amplifier voltage regulation circuit. Based on the above embodiment, the second circuit includes:

[0060] Fifth field-effect transistor (see attached) Figure 1 In the NM5, the gate of the fifth field-effect transistor is connected to an external power supply, the source of the fifth field-effect transistor is grounded, and the drain of the fifth field-effect transistor is connected to the first switch, the second switch, the third switch and the fourth switch respectively.

[0061] Sixth field-effect transistor (see attached reference) Figure 1 In this embodiment, NM5 and NM7 are both current mirror transistors, providing current to the second-stage operational amplifier voltage regulation circuit. The gate of the sixth field-effect transistor is connected to an external power supply, the source of the sixth field-effect transistor is grounded, and the drain of the sixth field-effect transistor is connected to the input terminal of the first circuit.

[0062] In one embodiment, such as Figure 1 As shown, the present invention provides a two-stage operational amplifier voltage regulation circuit. Based on the above embodiments, the first circuit shown includes:

[0063] Seventh Field-Effect Transistor (see attached document) Figure 1In the case of PM3), the drain of the seventh field-effect transistor is connected to the third power supply 110, the source of the seventh field-effect transistor is connected to the drain of the first field-effect transistor and the third field-effect transistor respectively, and the gate of the seventh field-effect transistor is connected to the source of the seventh field-effect transistor.

[0064] Eighth field-effect transistor (see attached) Figure 1 In the PM4), the drain of the eighth field-effect transistor is connected to the third power supply 110, the source of the eighth field-effect transistor is connected to the drain of the second field-effect transistor, and the gate of the eighth field-effect transistor is connected to the gate and source of the seventh field-effect transistor.

[0065] Ninth Field-Effect Transistor (see attached document) Figure 1 In this embodiment, PM6 is the drain of the ninth field-effect transistor (FET), connected to the third power supply. The source of the ninth FET is connected to the drain of the sixth FET and the first power supply, respectively. The gate of the seventh FET is connected to the drain of the fourth FET and the source of the eighth FET, respectively. In this embodiment, PM3 and PM4 are the load transistors of the common-source operational amplifier, which improve the gain. PM6 is the power transistor of the second-stage operational amplifier, which also improves the gain.

[0066] In one embodiment, such as Figure 1 As shown, the present invention provides a two-stage operational amplifier voltage regulation circuit, based on the above embodiments,

[0067] The first and second field-effect transistors are N-type field-effect transistors; the third and fourth field-effect transistors are NT-type field-effect transistors.

[0068] The seventh and eighth field-effect transistors are P-type field-effect transistors.

[0069] In one embodiment, the present invention provides an electronic device using a two-stage operational amplifier voltage regulation circuit, including the two-stage operational amplifier voltage regulation circuit described in the foregoing embodiments.

[0070] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A two-stage operational amplifier voltage regulating circuit, characterized by comprising: include: First power supply, second power supply, first field-effect transistor, second field-effect transistor, third field-effect transistor, fourth field-effect transistor, first switch, second switch, third switch, fourth switch, first circuit and second circuit; The gate of the first field-effect transistor is connected to the first power supply, and the source of the first field-effect transistor is connected to one end of the first switch. The gate of the second field-effect transistor is connected to the second power supply, and the source of the second field-effect transistor is connected to one end of the second switch; The gate of the third field-effect transistor is connected to the first power supply, and the source of the third field-effect transistor is connected to one end of the third switch. The gate of the fourth field-effect transistor is connected to the second power supply, and the source of the fourth field-effect transistor is connected to one end of the fourth switch. The first and second field-effect transistors are N-type field-effect transistors, and the third and fourth field-effect transistors are NT-type field-effect transistors with Vth close to 0; When the input voltage of the first power supply and the second power supply is greater than the preset voltage, the third switch and the fourth switch are disconnected, and the first switch and the second switch are closed, so that the first field-effect transistor and the second field-effect transistor are turned on. When the input voltage of the first power supply and the second power supply is not greater than the preset voltage, the first switch and the second switch are disconnected, and the third switch and the fourth switch are closed, so that the third field-effect transistor and the fourth field-effect transistor are turned on. The drain of the first field-effect transistor is connected to the drain and gate of the seventh field-effect transistor of the first circuit, and the drain of the first field-effect transistor is also connected to the gate of the eighth field-effect transistor of the first circuit. The drain of the second field-effect transistor is connected to the drain of the eighth field-effect transistor in the first circuit, and to the gate of the ninth field-effect transistor in the first circuit. The drain of the third field-effect transistor is connected to the drain and gate of the seventh field-effect transistor, and the drain of the third field-effect transistor is also connected to the gate of the eighth field-effect transistor. The drain of the fourth field-effect transistor is connected to the drain of the eighth field-effect transistor and to the gate of the ninth field-effect transistor. The other ends of the first switch, the second switch, the third switch, and the fourth switch are all connected to the drain of the fifth field-effect transistor in the second circuit; The gate of the fifth field-effect transistor is connected to an external power supply, and the source of the fifth field-effect transistor is grounded. The sixth field-effect transistor has its gate connected to the external power supply and its source grounded. The drain of the sixth field-effect transistor is connected to the drain of the ninth field-effect transistor; The source of the seventh field-effect transistor is connected to the third power supply; The source of the eighth field-effect transistor is connected to the third power supply; The source of the ninth field-effect transistor is connected to the third power supply, and the drain of the ninth field-effect transistor is also connected to the first power supply.

2. The two-stage operational amplifier voltage regulating circuit of claim 1, wherein The seventh and eighth field-effect transistors are P-type field-effect transistors.

3. An electronic device employing a two-stage operational amplifier voltage regulation circuit, characterized in that, Includes the two-stage operational amplifier voltage regulation circuit as described in any one of claims 1-2.

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