Clock jitter improvement method, programmable logic device and storage medium

Abstract

This invention proposes a clock jitter improvement method, a programmable logic device (PLD), and a storage medium. The clock jitter improvement method is applied to a PLD, which includes a phase-locked loop (PLL), logic function units, and interface units. The method includes: acquiring a local clock output from a crystal oscillator; configuring the frequency and / or phase of the local clock through the PLL to obtain a first system clock corresponding to the logic function unit and a second system clock corresponding to the interface unit, wherein the frequency difference between the first system clock and the second system clock is outside a preset frequency range. This invention can significantly improve the clock jitter of the PLD hardware board without modifying the hardware structure and cost of the PLD, and without affecting the original functionality of the PLD.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a method for improving clock jitter, a programmable logic device, and a storage medium. Background Technology

[0002] Programmable logic devices (PLDs) are widely used in both traditional and emerging markets due to their versatility, flexibility, and short development cycles. With technological advancements, the number of digital signal clocks in PLDs is increasing, while circuit systems are placing increasingly stringent demands on signal setup and hold times, clock jitter, and other factors.

[0003] Clock jitter is caused by interference or noise during the transmission of clock signals. For example, external temperature and voltage changes, as well as signal reflection and crosstalk on transmission lines can affect the rising and falling edges of the clock signal, resulting in changes in frequency, phase, and amplitude. Clock jitter can lead to timing violations and reduced circuit reliability.

[0004] In actual products, especially for data interfaces with clock signals, clock jitter plays a crucial role in the correct sampling of signals. Existing technologies usually improve clock jitter by adjusting the power network or improving the quality of the clock source. However, programmable logic devices are usually small in size and low in cost. The circuit board of programmable logic devices is small, which limits the addition of capacitors and resistors. Using a high-quality clock will also increase costs. Especially for boards that are already in mass production, hardware changes require the entire machine to be retested, and the project time is greatly extended, which cannot meet the requirements and will bring great obstacles to research and development and production. Summary of the Invention

[0005] This invention provides a clock jitter improvement method, a programmable logic device, and a storage medium. Its main purpose is to improve the clock jitter problem without changing the hardware structure of the programmable logic device or increasing costs.

[0006] In a first aspect, embodiments of the present invention provide a clock jitter improvement method, wherein the clock jitter improvement method is applied to a programmable logic device, the programmable logic device including a phase-locked loop, logic function units, and interface units, and the clock jitter improvement method includes:

[0007] Obtain the local clock output from the crystal oscillator;

[0008] The frequency and / or phase of the local clock are configured by the phase-locked loop to obtain the first system clock corresponding to the logic function unit and the second system clock corresponding to the interface unit. The frequency difference between the first system clock and the second system clock is outside a preset frequency range.

[0009] Further, configuring the frequency and / or phase of the local clock through the phase-locked loop to obtain the first system clock corresponding to the logic functional unit includes:

[0010] If there are multiple logic function units, the local clock is configured through the phase-locked loop to obtain multiple first system clocks with different phases but the same frequency, so that the first system clocks drive the corresponding logic function units.

[0011] Further, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0012] The first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit are stored in the memory to enable clock synchronization when the logical functional units communicate with each other and when the logical functional units and the interface units communicate with each other.

[0013] Further, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0014] The programmable logic device is partitioned according to the clock jitter frequency to obtain multiple regions;

[0015] Based on the clock jitter frequency corresponding to the region, and in accordance with preset principles, the communication distance between the logical function units and the interface units in the region is set.

[0016] Furthermore, the principle of following the preset rules is as follows:

[0017] The higher the clock jitter frequency of the region, the farther the communication distance between the region and the interface unit.

[0018] Further, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0019] Recompile to generate a bitstream.

[0020] Furthermore, the memory is a first-in-first-out memory or a random access memory.

[0021] Further, configuring the frequency and / or phase of the local clock via the phase-locked loop includes:

[0022] The local clock is multiplied or divided by the phase-locked loop.

[0023] In a second aspect, embodiments of the present invention provide a programmable logic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of a clock jitter improvement method as provided in the first aspect.

[0024] Thirdly, embodiments of the present invention provide a computer storage medium storing a computer program, which, when executed by a processor, implements the steps of a clock jitter improvement method as provided in the first aspect.

[0025] This invention proposes a clock jitter improvement method, a programmable logic device (PLD), and a storage medium. It utilizes a phase-locked loop (PLL) within the PLD to modulate the local clock output from the crystal oscillator, producing a first system clock and a second system clock. The first system clock drives the logic function units, and the second system clock drives the interface units. The frequency difference between the first and second system clocks is sufficiently large to prevent the logic function modules and interface units from flipping simultaneously, thereby reducing internal power supply ripple and clock jitter interference. This invention significantly improves the clock jitter of the PLD hardware board without modifying the hardware structure or reducing costs, and does not affect the original functionality of the PLD. Attached Figure Description

[0026] Figure 1 A schematic diagram of a programmable logic device scenario for applying a clock jitter improvement method provided in the prior art;

[0027] Figure 2 A flowchart of a clock jitter improvement method provided in this embodiment of the invention;

[0028] Figure 3 This is a schematic diagram of a programmable logic device scenario in which a clock jitter improvement method provided in an embodiment of the present invention is applied.

[0029] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0030] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0031] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, terms such as "first," "second," and "third" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0034] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0035] There are many methods for solving clock jitter in existing technologies. Figure 1 A schematic diagram of a programmable logic device scenario in which a clock jitter improvement method provided in the prior art is applied, such as... Figure 1 As shown, the following measures are typically taken:

[0036] 1. Improve the PCB layout of programmable logic devices by adjusting the circuit arrangement to reduce various stray couplings in the circuit and thus reduce the amplitude of clock jitter.

[0037] 2. Adjust the clock planning, use a high-precision crystal oscillator to provide a high-precision clock source, and reduce the impact of clock jitter by designing a more reasonable clock structure and reducing the clock trace path.

[0038] Both of these methods require changing the physical structure of the programmable logic device, and cannot improve the clock jitter problem for programmable logic devices that are already in mass production.

[0039] 3. Using a dedicated clock chip: Employing a high-specification clock chip can effectively improve clock quality and thus effectively eliminate clock jitter. However, this method increases the cost of the programmable logic device.

[0040] 4. Clock jitter constraints: By imposing corresponding clock jitter constraints on programmable logic devices, the jitter range can be limited to ensure normal system function. However, this method is not applicable to all programmable logic devices.

[0041] This invention provides a clock jitter improvement method, which is applied to programmable logic devices, such as FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device). This invention uses FPGA as an example for illustration. Figure 2 A flowchart of a clock jitter improvement method provided in this embodiment of the invention is shown below. Figure 2 As shown, the clock jitter improvement method is applied to a programmable logic device, which includes a phase-locked loop, logic function units, and interface units. The clock jitter improvement method includes:

[0042] Figure 3 A schematic diagram of a programmable logic device scenario in which a clock jitter improvement method provided in an embodiment of the present invention is applied, as shown in the figure. Figure 3 As shown, the programmable logic device internally includes a phase-locked loop, logic function units, and interface units. A logic function unit refers to a unit within the programmable logic device that implements a specific function, such as a memory unit or a processor unit. This logic function unit can be divided according to its function, and there can be one or more logic function units, depending on the actual situation. This embodiment of the invention does not impose specific limitations on this. An interface unit can be understood as the I / O interface of the programmable logic device.

[0043] S210, obtain the local clock output from the crystal oscillator;

[0044] First, an external crystal oscillator outputs a clock signal, which is called the local clock. This crystal oscillator can be a regular crystal oscillator, and there is no need to add extra clock costs.

[0045] S220, the frequency and / or phase of the local clock are configured through the phase-locked loop to obtain the first system clock corresponding to the logic function unit and the second system clock corresponding to the interface unit, wherein the frequency difference between the first system clock and the second system clock is outside a preset frequency range.

[0046] A local clock is input into a phase-locked loop (PLL). The PLL configures the frequency or phase of the local clock, or simultaneously configures both the frequency and phase, and outputs a first system clock and a second system clock. The first system clock provides clock signals to the logic function units, and the second system clock provides clock signals to the interface units. In this embodiment of the invention, by providing different clock signals to the logic function units and the interface units respectively, and the frequency difference between the first system clock and the second system clock is greater than a preset frequency threshold, it is indicated that the frequency difference between the first system clock and the second system clock is large enough to prevent the logic function units and the interface units from flipping at the same time, thereby reducing the electrical ripple inside the programmable logic device and improving jitter.

[0047] It should be noted that the preset frequency threshold can be determined according to the actual situation, and the embodiments of the present invention do not impose specific limitations on it.

[0048] As one implementation, configuring the frequency and / or phase of the local clock via the phase-locked loop includes:

[0049] The local clock is multiplied or divided by the phase-locked loop.

[0050] In this embodiment of the invention, the phase-locked loop multiplies or divides the local clock to obtain a first system clock and a second system clock. The first system clock is then input into the logic function unit, and the second system clock is input into the interface unit.

[0051] This invention proposes a clock jitter improvement method that utilizes the phase-locked loop (PLL) within a programmable logic device (PLD) to modulate the local clock output from the crystal oscillator, generating a first system clock and a second system clock. The first system clock drives the logic function units, and the second system clock drives the interface units. The frequency difference between the first and second system clocks is sufficiently large to prevent the logic function modules and interface units from flipping simultaneously, thereby reducing internal power supply ripple and clock jitter interference. This invention significantly improves the clock jitter of PLD hardware boards without modifying the hardware structure or reducing costs, and does not affect the original functionality of the PLD.

[0052] In some embodiments, configuring the frequency and / or phase of the local clock through the phase-locked loop to obtain the first system clock corresponding to the logic functional unit includes:

[0053] If there are multiple logic function units, the local clock is configured through the phase-locked loop to obtain multiple first system clocks with different phases but the same frequency, so that the first system clocks drive the corresponding logic function units.

[0054] In this embodiment of the invention, when there are multiple logic function units, each logic function unit is connected to a phase-locked loop (PLL). The PLL outputs multiple first system clocks, each with a different phase but the same frequency. Each first system clock provides a clock signal for the corresponding logic function module.

[0055] In some embodiments, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0056] The first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit are stored in the memory to enable clock synchronization when the logical functional units communicate with each other and when the logical functional units and the interface units communicate with each other.

[0057] For example, the memory is a First In First Out (FIFO) memory or a Random Access Memory (RAM).

[0058] Because a first system clock and a second system clock are provided to the logic function unit and the interface unit respectively through a phase-locked loop, and the first system clock and the second system clock are different, there is a clock deviation between the logic function unit and the interface unit, that is, the clocks of the two are not synchronized. However, when the logic function units and the interface units communicate within the programmable logic device, it is necessary to ensure that the clocks are synchronized. Therefore, in this embodiment of the invention, the first system clock and the second system clock are stored in a memory. When communication is performed, the frequencies of the first system clock and the second system clock are adjusted so that the first system clock and the second system clock can be synchronized, thereby achieving successful communication.

[0059] In some embodiments, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0060] The programmable logic device is partitioned according to the clock jitter frequency to obtain multiple regions;

[0061] Based on the clock jitter frequency corresponding to the region, and in accordance with preset principles, the communication distance between the logical function units and the interface units in the region is set.

[0062] In this embodiment of the invention, when there are many logic functional units, in order to improve processing efficiency, the logic functional units inside the programmable logic device can be partitioned. The specific partitioning method can be determined according to the actual situation, and this embodiment of the invention does not specifically limit it. For example, in this embodiment of the invention, the regions are divided according to the jitter frequency. The jitter frequency is divided into three levels: high, medium, and low. Logic functional modules with high jitter frequency are divided into the same region, logic functional modules with medium jitter frequency are divided into the same region, and logic functional modules with low jitter frequency are divided into the same region. The communication distance between each region and the interface unit is determined accordingly.

[0063] Specifically, the principle of following the preset rules is as follows:

[0064] The higher the clock jitter frequency of the region, the farther the communication distance between the region and the interface unit.

[0065] In this embodiment of the invention, the higher the clock jitter frequency corresponding to a certain region, the farther the communication distance between that region and the interface unit is set. The specific communication distance value can be determined according to the actual situation, and this embodiment of the invention does not impose a specific limitation on it. In actual implementation, different communication distances can be set for testing to find a suitable communication distance.

[0066] In some embodiments, after obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes:

[0067] Recompile to generate a bitstream.

[0068] In this embodiment of the invention, only the clock signals of the logic function unit and the interface unit need to be changed through software programming. There is no need to change the physical structure of the programmable logic device. Therefore, after programming is completed, the program needs to be re-burned into the programmable logic device. Specifically, the bit stream upgrade method is used to synchronize the program inside the mass-produced programmable logic device, so that the upgrade and reloading can be performed.

[0069] The clock jitter improvement method provided by this invention can be adjusted according to customer needs and continuously iterated to achieve the expected effect. It not only avoids the complexity of redesigning hardware and shortens the project design cycle, but also allows the product to achieve the desired effect by upgrading the bit stream of the logic device under different application scenarios.

[0070] In one embodiment, a programmable logic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a clock jitter improvement method described in the above embodiment.

[0071] In one embodiment, a computer storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of a clock jitter improvement method described in the above embodiment.

[0072] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0074] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for improving clock jitter, characterized in that, The clock jitter improvement method is applied to a programmable logic device, which includes a phase-locked loop, logic function units, and interface units. The clock jitter improvement method includes: Obtain the local clock output from the crystal oscillator; The frequency and / or phase of the local clock are configured by the phase-locked loop to obtain the first system clock corresponding to the logic function unit and the second system clock corresponding to the interface unit. The frequency difference between the first system clock and the second system clock is greater than a preset frequency threshold. After obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes: The programmable logic device is partitioned according to the clock jitter frequency to obtain multiple regions; Based on the clock jitter frequency corresponding to the region, and in accordance with preset principles, the communication distance between the logical function unit and the interface unit in the region is set. The predetermined principle is as follows: The higher the clock jitter frequency of the region, the farther the communication distance between the region and the interface unit.

2. The clock jitter improvement method according to claim 1, characterized in that, The step of configuring the frequency and / or phase of the local clock through the phase-locked loop to obtain the first system clock corresponding to the logic functional unit includes: If there are multiple logic function units, the local clock is configured through the phase-locked loop to obtain multiple first system clocks with different phases but the same frequency, so that the first system clocks drive the corresponding logic function units.

3. The clock jitter improvement method according to claim 1, characterized in that, After obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes: The first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit are stored in the memory to enable clock synchronization when the logical functional units communicate with each other and when the logical functional units and the interface units communicate with each other.

4. The clock jitter improvement method according to any one of claims 1 to 3, characterized in that, After obtaining the first system clock corresponding to the logical functional unit and the second system clock corresponding to the interface unit, the process further includes: Recompile to generate a bitstream.

5. The clock jitter improvement method according to claim 3, characterized in that, The memory is a first-in-first-out memory or a random access memory.

6. The clock jitter improvement method according to any one of claims 1 to 3, characterized in that, The configuration of the frequency and / or phase of the local clock via the phase-locked loop includes: The local clock is multiplied or divided by the phase-locked loop.

7. A programmable logic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the clock jitter improvement method as described in any one of claims 1 to 6.

8. A computer storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the clock jitter improvement method as described in any one of claims 1 to 6.

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