A method and device for reducing chip power consumption, an electronic device and a storage medium

Abstract

The application relates to a chip power consumption reduction method and device, electronic equipment and storage medium, and belongs to the integrated circuit field. The method comprises the following steps: deleting a specific clock unit in a functional module of a clock tree synthesized chip; wherein, the end point fanout of the specific clock unit is a flip-flop with a timing margin; clustering the flip-flops with the timing margin in the functional module after the specific clock unit is deleted to obtain a plurality of flip-flop groups; acquiring average position coordinates of the flip-flops in each flip-flop group; moving the positions of the flip-flops in each flip-flop group to the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the flip-flop; and performing clock tree synthesis on the functional module after the positions are moved. The application reduces the dynamic power consumption of the integrated circuit by reducing the number and load of clock units in the integrated circuit.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits, and specifically relates to a method, apparatus, electronic device and storage medium for reducing chip power consumption. Background Technology

[0002] Reducing chip power consumption is a crucial consideration in modern chip design. Chip power consumption is categorized into static power consumption and dynamic power consumption. Dynamic power consumption refers to the power consumption generated by transistors charging and discharging capacitive loads within the integrated circuit, as well as the short-circuit power consumption caused by momentary short circuits during signal transitions. In high-performance logic chips, dynamic power consumption can account for more than half of the total integrated circuit power consumption. Within the cells of an integrated circuit, clock cells in the clock tree generate a significant amount of dynamic power consumption because these clock cells have high signal transition rates and large load networks. Therefore, reducing the number of these clock cells can directly reduce the dynamic power consumption of the integrated circuit. Summary of the Invention

[0003] Therefore, the purpose of this application is to provide a method, apparatus, electronic device, and storage medium for reducing chip power consumption, thereby reducing the dynamic power consumption problem of integrated circuits.

[0004] The embodiments of this application are implemented as follows:

[0005] In a first aspect, embodiments of this application provide a method for reducing chip power consumption, comprising: deleting specific clock units from the functional modules of a chip after clock tree synthesis; wherein the end fan-out of the specific clock units are all triggers with timing margins; clustering the triggers with timing margins in the functional modules after deleting the specific clock units to obtain multiple trigger groups; obtaining the average position coordinates of the triggers in each trigger group; moving the position of the triggers in each trigger group to the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the triggers; and performing clock tree synthesis on the functional modules after the position is moved.

[0006] In this embodiment, specific clock units in the functional modules after clock tree synthesis are deleted, where the final fan-out of each trigger has a timing margin. Then, the triggers with timing margins in the functional modules are clustered, and the positions of the triggers in each trigger group are moved a specified distance towards the average position coordinate. After that, clock tree synthesis is performed on the functional modules after the position is moved. At this time, the number of newly added clock units is definitely less than the number of clock units deleted. By reducing the number of clock units, the dynamic power consumption of the integrated circuit is reduced. Moreover, only clock units in the triggers with final fan-outs have timing margins are deleted, so it will not have an adverse effect on the timing of the original functional modules.

[0007] In one possible implementation of the first aspect embodiment, before deleting a specific clock unit in the functional module of the clock tree synthesized chip, the method further includes: marking the flip-flops in the functional module that meet the timing margin requirements; obtaining the first-level clock unit fan-in for each marked flip-flop; filtering out target clock units from the first-level clock units, wherein the flip-flops fan-out from the target clock units include unmarked flip-flops; deleting the markings of the flip-flops corresponding to the target clock units, wherein the remaining marked flip-flops are the flip-flops with timing margins.

[0008] In this embodiment, the flip-flops that meet the timing margin requirements in the functional module are marked. Then, the first-level clock unit fanned into each marked flip-flop is obtained. The flip-flops fanned out by the first-level clock unit are checked to see if there are any unmarked flip-flops. The target clock unit is then obtained. The mark of the flip-flop corresponding to the target clock unit is then deleted. In this way, the remaining marked flip-flops are the flip-flops with timing margins, and the number is less than that of the flip-flops that meet the timing margin requirements. This ensures that the timing of the original functional module will not be adversely affected.

[0009] In one possible implementation of the first aspect embodiment, deleting a specific clock unit in the functional module of the clock tree synthesized chip includes: checking whether the triggers fanned out at the end of each clock unit in the functional module are all the triggers with timing margin; marking the clock units whose triggers fan out at the end are all the triggers with timing margin; and deleting the marked clock units in the functional module after traversing each clock unit.

[0010] In this embodiment, by iterating through each clock cell to check if all the flip-flops fanned out at the end of the clock cell are flip-flops with timing margins, and marking the clock cells whose flip-flops fan out at the end of the clock cell are all flip-flops with timing margins, the marked clock cells in the functional module are deleted after iterating through each clock cell. This ensures that specific clock cells are deleted, so as to reduce the dynamic power consumption of the integrated circuit as much as possible.

[0011] In one possible implementation of the first aspect embodiment, the triggers with timing margins in the functional module after deleting a specific clock unit are clustered to obtain multiple trigger groups, including: obtaining all clock units in the functional module after deleting the specific clock unit; calculating the distance from each of the triggers with timing margins to each clock unit, and clustering each of the triggers with timing margins according to the distance to obtain multiple trigger groups.

[0012] In this embodiment of the application, when clustering flip-flops with timing margins, all remaining clock units are obtained, and then the distance from each flip-flop with timing margin to each clock unit is calculated. Based on the distance, each flip-flop with timing margin is clustered, thereby obtaining multiple flip-flop groups. Using this method for clustering makes the positions of flip-flops in the same flip-flop group relatively concentrated.

[0013] In one possible implementation of the first aspect embodiment, clustering each of the time-series-remaining triggers according to distance includes: clustering each of the time-series-remaining triggers into the k-th trigger group, where k∈[1,n], n is the number of clock units in the functional module after deleting a specific clock unit, and is an integer greater than or equal to 2, and the distance of the time-series-remaining trigger to the k-th clock unit is the minimum value among the distances to each clock unit.

[0014] In this embodiment, the same standard (clustering each flip-flop with timing margin into the kth flip-flop group) is used to cluster each flip-flop with timing margin, so that the distance between the position of each flip-flop in the same flip-flop group and the same clock unit is minimized compared to other clock units. This can minimize the number of clock units added by subsequent clock tree synthesis, thereby minimizing the dynamic power consumption of the integrated circuit.

[0015] In one possible implementation of the first aspect embodiment, the specified distance is determined based on the timing margin of the trigger and the signal transmission rate. The method further includes: creating a virtual module, wherein the process and library files used by the virtual module are consistent with those used by the functional module, the standard cells used by the virtual module are consistent with those used by the functional module, and the winding rules of the virtual module are consistent with those of the functional module; obtaining the Manhattan distance of the winding of each timing path within the virtual module from the starting point to the ending point, and obtaining the transmission time of each timing path within the virtual module; and obtaining the signal transmission rate based on the Manhattan distance and transmission time of each timing path.

[0016] In this embodiment, the virtual module is constructed using the same process, library files, standard units, and winding rules as the functional module. This ensures that the signal transmission rate obtained based on the virtual module is as consistent as possible with the signal transmission rate of the functional module, thereby improving accuracy.

[0017] In a possible implementation of the first aspect embodiment, if the functional module is a multi-clock domain functional module, the method further includes: for each clock domain in the functional module, deleting specific clock units of the clock tree synthesized functional module in each clock domain; wherein the fan-out endpoints of the specific clock units are all triggers with timing margins; clustering the triggers with timing margins in the functional module after deleting specific clock units to obtain multiple trigger groups; obtaining the average position coordinates of the triggers in each trigger group in each clock domain; moving the positions of the triggers in each trigger group in each clock domain towards the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the triggers; and performing clock tree synthesis on the functional module after the position shift in each clock domain.

[0018] In this embodiment, the same processing flow is performed for each clock domain in the functional module until all clock domains are traversed. By processing different clock domains separately, the dynamic power consumption of the integrated circuit is reduced without causing timing disorder.

[0019] Secondly, embodiments of this application also provide an apparatus for reducing chip power consumption, comprising: a deletion module, a clustering module, a moving module, and a synthesis module; the deletion module is used to delete specific clock units in the functional modules of the chip after clock tree synthesis; wherein the end fan-out of the specific clock units are all triggers with timing margins; the clustering module is used to cluster the triggers with timing margins in the functional modules after deleting the specific clock units to obtain multiple trigger groups; the moving module is used to obtain the average position coordinates of the triggers in each trigger group, and move the position of the triggers in each trigger group to the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the triggers; the synthesis module is used to perform clock tree synthesis on the functional modules after the position is moved.

[0020] Thirdly, embodiments of this application also provide an electronic device, including: a memory and a processor, the processor being connected to the memory; the memory being used to store a program; the processor being used to invoke the program stored in the memory to perform a method provided as described in the first aspect embodiments and / or in combination with any possible implementation of the first aspect embodiments.

[0021] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the method provided by any possible implementation of the first aspect embodiments and / or in combination with the first aspect embodiments.

[0022] The beneficial effects of the second to fourth aspects of the above embodiments are consistent with the beneficial effects of the methods provided by any possible implementation of the first embodiment and / or in combination with the first aspect embodiments, and will not be repeated here.

[0023] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0025] Figure 1 A flowchart illustrating a method for reducing chip power consumption provided in an embodiment of this application is shown.

[0026] Figure 2 This paper presents a schematic diagram of the structure of a clock tree synthesized functional module according to an embodiment of this application.

[0027] Figure 3 This illustration shows a schematic diagram of a trigger with timing margin that is selected from functional modules according to an embodiment of this application.

[0028] Figure 4 This illustration shows a schematic diagram of a specific clock unit in a functional module after deletion, as provided in an embodiment of this application.

[0029] Figure 5 This illustration shows a schematic diagram of clustering triggers with timing margins in a functional module, according to an embodiment of this application.

[0030] Figure 6 This illustration shows a schematic diagram of an embodiment of the present application that moves the position of the triggers in each trigger group a specified distance toward the average position coordinates.

[0031] Figure 7 This illustration shows a schematic diagram of clock tree synthesis of functional modules after position shifting, as provided in an embodiment of this application.

[0032] Figure 8 A schematic diagram of a device for reducing chip power consumption provided in an embodiment of this application is shown.

[0033] Figure 9A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0035] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0037] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "electrical connection" can refer to a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0038] To reduce the dynamic power consumption of integrated circuits, embodiments of this application provide a method, apparatus, electronic device, and storage medium for reducing chip power consumption. By reducing the number and load of clock cells in the integrated circuit, the dynamic power consumption of the integrated circuit is reduced.

[0039] The following is combined Figure 1 The method for reducing chip power consumption provided in the embodiments of this application will be described.

[0040] S1: Delete a specific clock unit from the functional modules of the synthesized clock tree chip.

[0041] A complete chip (integrated circuit) involves many functional modules. In order to speed up the design process, each functional module is usually designed separately in parallel by different designers or teams. Different designers or teams are responsible for the design of different functional modules.

[0042] Integrated circuit design typically involves the following steps: initial design phase, verification and simulation, physical design phase, re-verification, and actual manufacturing phase. The initial design phase includes circuit design, logic design, and physical design. In this phase, designers use specialized EDA (Electronic Design Automation) tools to design the circuit structure, function, and layout of functional modules. After the initial design phase is completed, verification and simulation are performed to ensure the correctness and reliability of the functional modules. In this phase, designers use verification tools and simulators to perform large-scale functional verification, timing verification, and circuit simulation to ensure that the functional module design meets specifications. The physical design phase transforms the logic design into the actual physical structure. It includes placement design, timing optimization, pin assignment, routing, and clock tree synthesis. The goal of physical design is to ensure that the chip's physical connections meet electrical and timing requirements.

[0043] After clock tree synthesis of the chip's functional modules, specific clock units in the synthesized functional modules (hereinafter referred to as functional modules) are deleted. These specific clock units all have flip-flops with timing margins at their end fan-out. Clock units are typically buffers or inverters. This application only deletes clock units whose end fan-outs are all flip-flops with timing margins, thus avoiding any negative impact on timing results.

[0044] This step can be to first obtain the flip-flops with timing margins in the functional module, then obtain the flip-flops fanned out at the end of the clock unit in the functional module; delete the clock units where all the flip-flops fanned out at the end are flip-flops with timing margins, where the clock units where all the flip-flops fanned out at the end are flip-flops with timing margins are specific clock units.

[0045] In one optional implementation, the implementation process of S1 may be: checking whether the triggers fanned out at the end of each clock unit in the functional module are all triggers with timing margins, marking the clock units whose triggers fan out at the end are all triggers with timing margins, and deleting the marked clock units in the functional module after traversing each clock unit.

[0046] Among them, the triggers with timing margins in the functional modules can be obtained in advance and then stored in a specific location, such as a database or memory, so that they can be retrieved directly when needed later.

[0047] In one optional implementation, before step S1, the method further includes: marking the flip-flops in the functional module that meet the timing margin requirements, and obtaining the first-level clock unit fan-in for each marked flip-flop; filtering out target clock units from the first-level clock units, wherein there are unmarked flip-flops fan-out from the target clock units, and deleting the markings of the flip-flops corresponding to the target clock units, wherein the remaining marked flip-flops are flip-flops with timing margins. This method allows for the rapid acquisition of flip-flops with timing margins in the functional module.

[0048] After clock tree synthesis, timing information of functional modules can be extracted. For example, the slack value of the timing path starting and ending at each flip-flop can be extracted. If the slack values ​​of all timing paths starting and ending at a flip-flop meet the timing margin requirement (e.g., slack value > 0), the flip-flop is marked, and the timing margin of each marked flip-flop is recorded as t (which can be the absolute value of the slack value). This process continues until all flip-flops meeting the timing margin requirement are marked. The first-level clock unit fanned into each marked flip-flop is obtained. It is then checked whether there are any unmarked flip-flops fanned out by the first-level clock unit. If so, the first-level clock unit is the target clock unit. Next, the marking of the flip-flop corresponding to the target clock unit is deleted. That is, if the first-level clock unit fanned into by a flip-flop is the target clock unit, the marking of that flip-flop is deleted. This process continues until all target clock units have been traversed. The remaining marked flip-flops are those with timing margins. The number of remaining marked flip-flops will be less than the number of previously marked flip-flops.

[0049] To better understand the above process, the following will combine... Figures 2-4 To illustrate, suppose the structure of the functional modules after clock tree synthesis is as follows: Figure 2 As shown, it contains multiple flip-flops and clock units. Then, flip-flops with timing margins (i.e., the marked flip-flops) are selected from the functional modules, such as... Figure 3 As shown, a specific clock unit in the functional module is then deleted. The schematic diagram after deleting the specific clock unit in the functional module is shown below. Figure 4 As shown. Among them, Figure 3 The CCP involves 8 clock units (numbered C1 to C8 in sequence). Since clock unit 1 (numbered C1) is the root node, Figure 3All flip-flops are fan-out flip-flops at the end of clock unit 1; the fan-out flip-flops at the end of clock unit 2 (numbered C2) include flip-flops connected to clock units 2, 3, and 4; the fan-out flip-flops at the end of clock unit 3 (numbered C3) include flip-flops connected to clock unit 3; the fan-out flip-flops at the end of clock unit 4 (numbered C4) include flip-flops connected to clock unit 4, and so on. Among these, the fan-out flip-flops at the end of clock units 3, 4, 6 (numbered C6), 7 (numbered C7), and 8 (numbered C8) are all flip-flops with timing margins, therefore, they are all specific clock units.

[0050] S2: Cluster the flip-flops with timing margins in the functional modules after deleting specific clock units to obtain multiple flip-flop groups.

[0051] After deleting specific clock units from the functional modules synthesized from the clock tree, the flip-flops with timing margins in the functional modules after deleting specific clock units are clustered to obtain multiple flip-flop groups.

[0052] When clustering triggers with timing margins in a functional module, clustering can be performed based on the location information of the triggers with timing margins, and triggers that are close in distance (e.g., the distance is less than a preset threshold) can be grouped into a cluster group.

[0053] In one optional implementation, step S2 can be implemented as follows: obtaining all clock units in the functional module after deleting a specific clock unit; calculating the distance from each trigger with timing margin to each clock unit, and clustering each trigger with timing margin according to the distance to obtain multiple trigger groups. For example, after calculating the distance from each trigger with timing margin to each clock unit, triggers with similar distances (e.g., the distance difference is less than a preset distance) relative to the same clock unit can be grouped into a cluster group.

[0054] In one optional implementation, when clustering each trigger with timing margin based on distance, the process can be as follows: Each trigger with timing margin is clustered into the kth trigger group, where k ∈ [1, n], n is the number of clock units in the functional module after deleting a specific clock unit, and is an integer greater than or equal to 2. The distance from the trigger with timing margin to the kth clock unit is the minimum among the distances to all clock units. In this implementation, for each trigger with timing margin, after calculating the distances D1 to Dn from the trigger with timing margin to each clock unit, assuming that the distance Dk to the kth clock unit is the smallest among these n distances, the trigger with timing margin is classified into the kth cluster, i.e., C. k Each flip-flop with a timing margin is categorized according to the same principle. After traversing each flip-flop with a timing margin, multiple flip-flop groups can be obtained.

[0055] Since flip-flops with different timing margins are located in different positions, their distances to various clock units also differ. Correspondingly, their classification (C) varies. k They are not entirely the same. For example, for trigger 1 with a timing margin, it is classified into C1, while for trigger 2 with a timing margin, it is classified into C2. That is, different triggers with timing margins are classified into different trigger groups with different group numbers k.

[0056] To better understand, combine Figure 5 Explanation will be provided. In Figure 4 In the process of deleting specific clock units from the synthesized clock tree functional module, the remaining number of clock units in the functional module is 3. The distances D1 to D3 between each marked flip-flop and these 3 clock units are calculated. Based on these distances, each marked flip-flop is clustered to obtain the following... Figure 5 The cluster shown.

[0057] S3: Obtain the average position coordinates of the triggers within each trigger group.

[0058] After obtaining multiple trigger groups, the average position coordinates of the triggers within each trigger group are obtained. This can be done by calculating the average position coordinates of the triggers within each trigger group based on the position of each trigger within that group. S4: The position of the triggers within each trigger group is moved a specified distance towards the average position coordinates, where the specified distance is related to the timing margin of the triggers.

[0059] After obtaining the average position coordinates of the triggers within each trigger group, the position of the triggers in each trigger group is moved a specified distance towards the average position coordinates. This specified distance is related to the timing margin of the triggers; for example, the distance the triggers move (the specified distance) is positively correlated with the timing margin. When moving the positions of the triggers within a trigger group, the triggers in each trigger group are traversed until the position of every trigger in that trigger group has been moved, before traversing the triggers in the next trigger group, and so on, until all trigger groups have been traversed.

[0060] It is understandable that when moving the position of the triggers in each trigger group, it is also possible to move them a specified distance to a position near the average position coordinate. That is, it is not exactly moving them a specified distance to the average position coordinate. Some deviation is allowed, and the movement is allowed within the allowable error range. This can also make the triggers in the trigger group more concentrated.

[0061] Will Figure 5 The diagram obtained by shifting the position of the triggers in each trigger group by a specified distance towards the average position coordinate is shown below. Figure 6 As shown, Figure 6 The dashed box in the figure indicates the position of the pre-movement trigger.

[0062] In one alternative implementation, the specified distance is determined based on the timing margin of the trigger and the signal transmission rate. Assuming the timing margin of the trigger is represented by t, the signal transmission rate by v, and the specified distance by s, then s = t * v. Since the timing margin of each trigger is not exactly the same, the specified distance moved is also not entirely the same.

[0063] The signal transmission rate can be obtained in advance or pre-defined through a virtual module. The virtual module uses the same technology and library files as the functional module. The standard cells (such as buffers, inverters, flip-flops, etc.) used in the virtual module are consistent with those used in the functional module, as are the winding rules. The signal transmission speed is obtained by simulating the signal transmission of the functional module. Different technologies can produce the same standard cells; to avoid differences caused by different technologies, the technology used in the virtual module should be the same as that used in the functional module. Different library files contain different standard cells; the library files used in the virtual module and the functional module should be the same. Since library files contain various standard cells, for example, if they are all buffers, and the library file contains buffers of type x1, x2, x4, x6, and x8, where the numbers x1, x2, x4, x6, and x8 represent different driving capabilities of the buffer, if the functional module uses x2, then the virtual module also uses x2. Similarly, for flip-flops, the library file contains many types of flip-flops; the flip-flops used in the virtual module must be of the same type as those used in the functional module. Similarly, the routing rules of the virtual module are consistent with those of the functional module, so that the signal transmission rate obtained based on the virtual module is as consistent as possible with the signal transmission rate of the functional module.

[0064] In this implementation, the method further includes creating a virtual module, wherein the process and library files used by the virtual module are consistent with those used by the functional module, the standard cells used by the virtual module are consistent with those used by the functional module, and the winding rules of the virtual module are consistent with those of the functional module; obtaining the Manhattan distance L of the winding of each timing path inside the virtual module from the starting point to the ending point, and obtaining the transmission time T of each timing path inside the virtual module; and obtaining the signal transmission rate, such as v = ∑L / ∑T, based on the Manhattan distance and transmission time of each timing path.

[0065] After constructing a virtual module using the same process, library files, standard cells, and winding rules as the functional module, the Manhattan distance L of the winding from the start point to the end point of each timing path inside the virtual module is recorded. An RC extraction tool (R represents resistance, C represents capacitance) can be used to perform RC extraction on the virtual module, generating a SPEF (Standard Parasitic Exchange Format) file. A timing analysis tool is then used to read the design file and SPEF file of the virtual module, extracting the transmission time T of each timing path inside the virtual module. Finally, the signal transmission rate can be obtained based on the Manhattan distance and transmission time of each timing path.

[0066] Among them, the virtual module may include multiple timing paths, and each timing path includes at least two flip - flops and a logic unit (such as a buffer or an inverter) located between the two flip - flops, so as to simulate the transmission time of a signal sent from one of the flip - flops through the logic unit to the other flip - flop.

[0067] S5: Perform clock tree synthesis on the functional module after moving its position.

[0068] After moving the positions of the flip - flops within each flip - flop group by a specified distance towards the average position coordinates, perform clock tree synthesis on the functional module after moving its position. At this time, the number of newly added clock units must be less than the number of clock units deleted in step S1. In this way, the number of clock units can be reduced, and it will not have an adverse impact on the timing of the original functional module.

[0069] Performing clock tree synthesis on the functional module after moving its position will add new clock units to the functional module. Its schematic diagram is as Figure 7 shown. The number of newly added clock units must be less than the number of clock units deleted in step S1. The reasons are as follows: The number of flip - flops that a clock unit can drive is determined by the total load that the clock unit can drive. The total load consists of the wire load and the clock port load of the flip - flop, and the wire load accounts for the vast majority. Inside a cluster, since the positions of the flip - flops become more concentrated, the connection wires from the clock unit to each flip - flop will become shorter, and the wire load will decrease. Therefore, a single clock unit can drive a larger number of flip - flops. Assume that originally a clock unit drives p flip - flops on average, and after re - performing clock tree synthesis, a clock unit drives q flip - flops on average, then p < q. Denote the number of marked flip - flops as N, then That is, the number of newly added clock units must be less than the number of clock units deleted in step S1, achieving the purpose of reducing the total number of clock units inside the chip. Since the number of clock units is reduced, the dynamic power consumption of the integrated circuit can be reduced.

[0070] In one implementation, if the aforementioned functional module is a multi-clock domain functional module, i.e., it contains multiple different clock signals, the method further includes: for each clock domain in the functional module, deleting specific clock units of the clock-tree synthesized functional module in each clock domain; wherein the fan-out endpoints of the specific clock units are all flip-flops with timing margins; clustering the flip-flops with timing margins in the functional module after deleting specific clock units to obtain multiple flip-flop groups; obtaining the average position coordinates of the flip-flops in each flip-flop group under each clock domain; moving the positions of the flip-flops in each flip-flop group under each clock domain towards the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the flip-flops; and performing clock-tree synthesis on the functional module after the position shift in each clock domain. In this implementation, for each clock domain in the functional module, the following steps are performed: Figure 1 The processing flow shown continues until all clock domains have been traversed.

[0071] After performing clock tree synthesis on the functional modules after their relocation, subsequent physical routing and other design steps can be carried out.

[0072] This application also provides a device 100 for reducing chip power consumption, such as... Figure 8 As shown, the device 100 for reducing chip power consumption includes: a deletion module 110, a clustering module 120, a moving module 130, and a synthesis module 140.

[0073] The deletion module 110 is used to delete specific clock units in the functional modules of the chip after clock tree synthesis; wherein, the end fan-out of the specific clock unit is a trigger with timing margin.

[0074] Clustering module 120 is used to cluster the flip-flops with timing margins in the functional modules after deleting specific clock units, and obtain multiple flip-flop groups.

[0075] The moving module 130 is used to obtain the average position coordinates of the triggers in each trigger group, and move the position of the triggers in each trigger group to the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the triggers.

[0076] The synthesis module 140 is used to perform clock tree synthesis on the functional modules after the position is moved.

[0077] Optionally, the deletion module 110 is further configured to: mark the flip-flops in the functional module that meet the timing margin requirements before deleting a specific clock unit in the functional module after clock tree synthesis; obtain the first-level clock unit fan-in for each marked flip-flop; filter out the target clock unit from the first-level clock unit, wherein there are unmarked flip-flops fan-out from the target clock unit; and delete the markings of the flip-flops corresponding to the target clock unit, wherein the remaining marked flip-flops are the flip-flops with timing margins.

[0078] Optionally, the deletion module 110 is specifically used to check whether the triggers fanned out at the end of each clock unit in the functional module are all the triggers with timing margin; to mark the clock units whose triggers fan out at the end are all the triggers with timing margin; and to delete the marked clock units in the functional module after traversing each clock unit.

[0079] Optionally, the clustering module 120 is specifically used to obtain all clock units in the functional module after deleting a specific clock unit; calculate the distance from each of the time-series-remaining triggers to each clock unit, and cluster each of the time-series-remaining triggers according to the distance to obtain multiple trigger groups.

[0080] Optionally, the clustering module 120 is specifically used to cluster each of the triggers with timing margins into the k-th trigger group, where k∈[1, n], n is the number of clock units in the functional module after deleting a specific clock unit, and is an integer greater than or equal to 2. The distance from the trigger with timing margin to the k-th clock unit is the minimum value among the distances to each clock unit. The specified distance is determined based on the timing margin of the trigger and the signal transmission rate. The device 100 for reducing chip power consumption further includes: a signal transmission rate acquisition module, used to create a virtual module, wherein the process and library files used by the virtual module are consistent with those used by the functional module, the standard cells used by the virtual module are consistent with those used by the functional module, and the winding rules of the virtual module are consistent with those of the functional module; the Manhattan distance of the winding from the starting point to the ending point of each timing path inside the virtual module is acquired, and the transmission time of each timing path inside the virtual module is acquired; the signal transmission rate is obtained based on the Manhattan distance and transmission time of each timing path.

[0081] If the functional module is a multi-clock domain functional module, the deletion module 110 is further configured to delete a specific clock unit of the clock tree synthesized functional module in each clock domain for each clock domain in the functional module; wherein the end fanout of the specific clock unit is a trigger with timing margin.

[0082] Clustering module 120 is also used to cluster flip-flops with timing margins in functional modules after deleting specific clock units, to obtain multiple flip-flop groups.

[0083] The moving module 130 is further configured to, based on the average position coordinates of the flip-flops in each flip-flop group under each clock domain, move the position of the flip-flops in each flip-flop group under each clock domain towards the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the flip-flops.

[0084] The synthesis module 140 is also used to perform clock tree synthesis on the functional modules after the position is moved in each clock domain.

[0085] The device 100 for reducing chip power consumption provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0086] like Figure 9 As shown, Figure 9 This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0087] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as... Figure 8 The software functional module shown is the chip power reduction device 100. The chip power reduction device 100 includes at least one software functional module that can be stored in the memory 220 as software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute executable modules stored in the memory 220, such as the software functional module or computer program included in the chip power reduction device 100. For example, the processor 240 is used to execute the aforementioned chip power reduction method.

[0088] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0089] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0090] Among them, the aforementioned electronic devices 200 include, but are not limited to, mobile phones, tablets, computers, etc.

[0091] This application embodiment also provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium) storing a computer program, which, when run by a computer such as the electronic device 200 described above, executes the method for reducing chip power consumption as described above.

[0092] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0094] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0095] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0096] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for reducing chip power consumption, characterized in that, include: Remove specific clock units from the functional modules of the synthesized clock tree chip; wherein, the end fanout of the specific clock unit is a trigger with timing margin. Cluster the flip-flops with timing margins in the functional modules after deleting specific clock units to obtain multiple flip-flop groups; Obtain the average position coordinates of the triggers within each trigger group; The position of the trigger in each trigger group is moved a specified distance toward the average position coordinate, wherein the specified distance is related to the timing margin of the trigger; Perform clock tree synthesis on the functional modules after their relocation; Specifically, flip-flops with timing margins in functional modules after removing specific clock units are clustered to obtain multiple flip-flop groups, including: Retrieve all clock units in the functional module after deleting a specific clock unit; Calculate the distance from each of the time-series-margin flip-flops to each clock unit, and cluster each of the time-series-margin flip-flops according to the distance to obtain multiple flip-flop groups.

2. The method according to claim 1, characterized in that, Before removing specific clock units from the functional modules of the synthesized clock tree chip, the method further includes: Mark the triggers in the functional module that meet the timing margin requirements; Obtain the first-stage clock unit fanned into each marked trigger; Target clock units are selected from the first-level clock units, wherein the fan-out flip-flops of the target clock units include unmarked flip-flops; The markers of the flip-flops corresponding to the target clock unit are deleted, wherein the remaining marked flip-flops are the flip-flops with timing margins.

3. The method according to claim 1, characterized in that, Remove specific clock units from the functional modules of the synthesized clock tree chip, including: Check whether the triggers fanned out at the end of each clock unit in the functional module are all triggers with timing margins. The clock units of all the triggers fanned out at the end point are marked as such; After traversing each clock unit, delete the marked clock units in the functional module.

4. The method according to claim 1, characterized in that, Clustering of each of the aforementioned triggers with timing margins based on distance includes: Each of the aforementioned triggers with timing margins is clustered into the k-th trigger group, where... , n is the number of clock units in the functional module after deleting a specific clock unit, and is an integer greater than or equal to 2. The distance from the trigger with timing margin to the k-th clock unit is the minimum value among the distances to each clock unit.

5. The method according to any one of claims 1-4, characterized in that, The specified distance is determined based on the timing margin of the trigger and the signal transmission rate, and the method further includes: Create a virtual module, wherein the process and library files used by the virtual module are consistent with those used by the functional module, the standard cells used by the virtual module are consistent with those used by the functional module, and the winding rules of the virtual module are consistent with those of the functional module. Obtain the Manhattan distance of the loop from the start point to the end point for each timing path inside the virtual module, and obtain the transmission time of each timing path inside the virtual module. The signal transmission rate is obtained based on the Manhattan distance and transmission time of each timing path.

6. The method according to claim 1, characterized in that, If the functional module is a multi-clock domain functional module, the method further includes: For each clock domain in the functional module, delete the specific clock unit of the functional module under each clock domain after clock tree synthesis; wherein, the end fanout of the specific clock unit is a trigger with timing margin. Cluster the flip-flops with timing margins in the functional modules after deleting specific clock units to obtain multiple flip-flop groups; Obtain the average position coordinates of the flip-flops within each flip-flop group in each clock domain; The position of the flip-flop in each flip-flop group under each clock domain is moved a specified distance toward the average position coordinate, wherein the specified distance is related to the timing margin of the flip-flop; In each clock domain, clock tree synthesis is performed on the functional modules after the position is moved.

7. A device for reducing chip power consumption, characterized in that, include: The deletion module is used to delete specific clock units in the functional modules of the chip after clock tree synthesis; wherein the end fanout of the specific clock unit is a trigger with timing margin. The clustering module is used to cluster flip-flops with timing margins in functional modules after deleting specific clock units, resulting in multiple flip-flop groups. The moving module is used to obtain the average position coordinates of the triggers in each trigger group, and move the position of the triggers in each trigger group to the average position coordinates by a specified distance, wherein the specified distance is related to the timing margin of the triggers; The synthesis module is used to perform clock tree synthesis on the functional modules after the position is moved. Specifically, flip-flops with timing margins in functional modules after removing specific clock units are clustered to obtain multiple flip-flop groups, including: Retrieve all clock units in the functional module after deleting a specific clock unit; Calculate the distance from each of the time-series-margin flip-flops to each clock unit, and cluster each of the time-series-margin flip-flops according to the distance to obtain multiple flip-flop groups.

8. An electronic device, characterized in that, include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, performs the method as described in any one of claims 1-6.

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