Memory semantic solid state disk and data storage system

Abstract

The application discloses a memory semantic solid state disk and a data storage system, the data storage system comprising: a host, a memory semantic solid state disk connected with the host; the host is used for storing data to the memory semantic solid state disk; the memory semantic solid state disk comprises: a CXL subsystem for realizing the interconnection between the host and the memory semantic solid state disk; a flash memory subsystem for storing the data; a memory subsystem for caching the data. In this way, the host writes data to the flash memory space first into the memory, and then is brushed into the flash memory, so that the temporary data continuously operated by the application is always kept in the memory, effectively avoiding invalid wear of the temporary data on the flash memory, and improving the data storage performance.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a memory semantic solid-state drive and data storage system. Background Technology

[0002] Single-Level Storage (SLS) is a computer storage architecture design. Its core idea is to map all storage objects into a unified address space, eliminating the semantic differences between serialized disks and memory. Single-Level Storage systems treat application persistence as a fundamental service of the operating system, aiming to simplify application persistence management, reduce application code complexity, improve programming efficiency, and enhance overall system performance.

[0003] However, existing single-level storage systems based on NVMe SSDs or NVM suffer from problems such as significant write wear caused by temporary data. Summary of the Invention

[0004] The purpose of this application is to provide a memory semantic solid-state drive and data storage system that can effectively avoid the unnecessary wear and tear on flash memory caused by temporary data and improve data storage performance.

[0005] To achieve the above objectives:

[0006] In a first aspect, this application provides a data storage system, including a host and a memory semantic solid-state drive connected to the host;

[0007] The host is used to store data to the memory semantic solid-state drive;

[0008] The memory semantic solid-state drive includes:

[0009] The CXL subsystem is used to enable interconnection between the host and the memory semantic solid-state drive;

[0010] Flash memory subsystem for storing the data;

[0011] A memory subsystem is used to cache the data.

[0012] In one embodiment, the host includes:

[0013] The system silencing module is used to respond to checkpoint operations by controlling the CPU slave cores to enter a silencing state through the CPU main core.

[0014] The checkpoint management module is used to generate checkpoint metadata after the CPU enters a silent state from the core, and to determine the storage addresses of different types of data to be backed up in the checkpoint metadata in the memory semantic solid-state drive.

[0015] The status tracking module is used to incrementally update the data to be backed up to the memory semantic solid-state drive based on the storage address.

[0016] In one embodiment, the host computer further includes:

[0017] The fault recovery module is used to initiate checkpoint recovery operations after an abnormal power failure event is detected.

[0018] In one embodiment, the CXL subsystem includes:

[0019] The CXL interface connected to the host;

[0020] The CXL controller is used to perform functions related to the CXL protocol.

[0021] In one embodiment, the memory subsystem includes:

[0022] The DRAM cache, including a fixed area and a swap area, is used as a data read / write cache for the flash memory subsystem.

[0023] The memory management unit is used to store the data to be backed up in the fixed area or the exchange area according to the storage address of the data to be backed up sent by the host.

[0024] In one embodiment, the flash memory subsystem includes:

[0025] A power-loss protection battery is used to provide power-loss protection for the memory semantic solid-state drive when the host experiences an abnormal power loss.

[0026] Secondly, this application provides a memory-semantic solid-state drive, including:

[0027] The CXL subsystem is used to enable interconnection between the host and the memory semantic solid-state drive;

[0028] The flash memory subsystem is used to store data;

[0029] The memory subsystem is used to cache data.

[0030] In one embodiment, the CXL subsystem includes:

[0031] The CXL interface connected to the host;

[0032] The CXL controller is used to perform functions related to the CXL protocol.

[0033] In one embodiment, the memory subsystem includes:

[0034] The DRAM cache, including a fixed area and a swap area, is used as a data read / write cache for the flash memory subsystem.

[0035] The memory management unit is used to store the data to be backed up in the fixed area or the exchange area according to the storage address of the data to be backed up sent by the host.

[0036] In one embodiment, the flash memory subsystem includes:

[0037] A power-loss protection battery is used to provide power-loss protection for the memory semantic solid-state drive when the host experiences an abnormal power loss.

[0038] The memory semantic solid-state drive and data storage system provided in this application embodiment include: a host and a memory semantic solid-state drive connected to the host; the host is used to store data in the memory semantic solid-state drive; the memory semantic solid-state drive includes: a CXL subsystem for interconnecting the host and the memory semantic solid-state drive; a flash memory subsystem for storing the data; and a memory subsystem for caching the data. In this way, data written by the host to the flash memory is first written to memory and then flushed to the flash memory, ensuring that temporary data continuously manipulated by applications is always kept in memory, effectively avoiding unnecessary wear and tear on the flash memory caused by temporary data and improving data storage performance. Attached Figure Description

[0039] Figure 1 A schematic diagram of the data storage system provided in the embodiments of the present invention. Figure 1 ;

[0040] Figure 2 This is a schematic diagram of the architecture of a data storage system provided in an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of the data storage system provided in the embodiments of the present invention. Figure 2 ;

[0042] Figure 4 This is a schematic diagram of the architecture of the memory semantic solid-state drive in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram illustrating the data access process using the access protocols supported by the CXL subsystem in this embodiment of the invention.

[0044] Figure 6 This is a schematic diagram illustrating the mapping relationship between different types of data and storage space in an embodiment of the present invention. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0046] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0047] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0048] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0049] It should be noted that step designations such as S101 and S102 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the protection scope of this application.

[0050] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0051] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0052] The following is a brief description of the terms that may be involved in the embodiments of this application and the existing related technologies.

[0053] Single-Level Storage (SLS) is a computer storage architecture design. Its core idea is to map all storage objects into a unified address space, eliminating the semantic differences between serialized disks and memory. SLS systems treat application persistence as a fundamental service of the operating system, aiming to simplify application persistence management, reduce application code complexity, improve programming efficiency, and enhance overall system performance. Traditional file systems and virtual memory systems typically require programmers to manage two layers of storage structures: volatile (inaccessible after a power outage) memory pages and persistent (existing after a power outage) disk blocks. Applications moving data back and forth between these two layers leads to complex persistence logic. In contrast, SLS systems implement persistence logic at the operating system kernel level, transparently persisting the entire application to the user. This avoids user intervention in complex and error-prone persistence logic during application development, eliminating the need for users to develop persistence and recovery code. In the event of a system crash, the SLS operating system restores the entire execution state of the application from disk through checkpoints, including CPU registers, system memory, and application memory, resuming execution uninterrupted. Single-level storage (SLS) systems can offer performance improvements in some scenarios because they eliminate the overhead of application-level persistence, allowing the system kernel to efficiently handle persistence. SLS can be used to replace database storage engines, accelerate hot boots, implement time-travel debugging, and provide transparent migration and fault tolerance. However, SLS also faces challenges. SLS requires accurate capture of application state, and the frequency of capture determines the amount of application work lost in the event of a crash. Furthermore, storage device performance limits the upper limit of the capture frequency. In the past few decades, lower storage performance has led to infrequent application persistence, hindering the widespread adoption of SLS. Additionally, SLS's transparent persistence saves all application data to the storage device, resulting in write amplification far greater than traditional storage structures. Moreover, single-level storage systems are highly coupled with other kernel modules, making them difficult to update and iterate in widely used open-source operating systems.

[0054] Memory-Semantic SSDs (MS-SSDs) are a high-performance, byte-addressable storage solution. They expose a large-capacity DRAM block as a read / write cache for the SSD's flash memory to the host, allowing the host to access the flash memory byte-by-byte and achieve extremely low access latency when the cache is hit. The byte-addressable nature of MS-SSDs is similar to that of Non-Volatile Memory (NVM). With software and driver support, it may be possible to integrate them into existing NVM programming models, enabling applications to use them as NVM in a consistent and standardized manner. MS-SSDs are also more cost-effective than NVM, allowing developers to fully leverage the advantages of NVM without incurring the high costs of alternative technologies. As a novel storage technology, MS-SSDs are expected to provide performance and scalability improvements in future computing systems, particularly excelling in applications requiring high-capacity, high-performance data access.

[0055] Compute Express Link (CXL) is a new open interconnect standard designed to provide higher data throughput and lower latency for MS-SSD implementations. CXL is based on the PCIe 5.0 physical and electrical interface, including the PCIe-based block input / output protocol (CXL.io) and new cache coherency protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). CXL addresses the bandwidth and capacity limitations of traditional memory interfaces (such as DDR), communication and data sharing issues among heterogeneous devices (such as GPUs, FPGAs, and ASICs), and the flexible and scalable configuration of computing and storage resources in data centers. CXL also reduces software stack complexity and enables interoperability between different processor, accelerator, and memory device types. CXL represents a significant shift in computer architecture, delivering groundbreaking performance improvements for data-intensive applications such as artificial intelligence, machine learning, and cloud computing.

[0056] The NVMe 1.4 specification introduced the Persistent Memory Region (PMR) feature, which resides in the memory space of the NVMe device and can be read and written via PCIe memory operations. It can also be used to implement MS-SSDs. The main characteristic of PMR is that data written to it is retained even after power loss, controller reset, or PMR enable / disable switching. This feature provides the host with a non-volatile memory region that can be accessed at the block level using logical block addresses or at memory-level read / write speeds using byte addressing. PMR's non-volatility, low latency, and byte addressing characteristics provide greater flexibility in data management, making it suitable for scenarios requiring frequent access to sensitive data that needs persistence.

[0057] Single-level storage systems typically use system-level checkpointing to capture system state. Compared to application-level checkpointing, system-level checkpointing needs to be implemented in the system kernel. When a checkpoint is reached, the kernel pauses all processes that require persistence; this process is called system silencing. The kernel then tracks the changes in application state over a period of time and persists these states. Different operating systems track significantly different states, but logically they are usually divided into three parts: application-related kernel objects, application data, and system data. When the system crashes abnormally, data executed by the application from the last checkpoint to the time of the crash is lost. During system startup, recovery resumes from the last checkpoint, eliminating the need for application data persistence. The performance of the storage device determines the maximum checkpointing frequency, which in turn determines the actual availability of the single-level storage system. In the past, single-level storage systems based on mechanical hard drives could only achieve checkpoints at the second level, making them unsuitable for servers requiring high reliability. However, existing single-level storage systems based on NVMe SSDs or NVM suffer from problems such as high write wear caused by temporary data.

[0058] For the above issues, please refer to Figure 1 This is a schematic diagram of the structure of a data storage system provided in an embodiment of this application, such as... Figure 1 As shown, the data storage system includes: a host 1 and a memory-based solid-state drive 2 connected to the host 1; wherein,

[0059] Host 1 is used to store data to memory semantic solid-state drive 2;

[0060] Memory semantic SSD 2 includes:

[0061] CXL subsystem 20 is used to realize the interconnection between host 1 and memory semantic solid-state drive 2;

[0062] Flash memory subsystem 21 is used for storing data;

[0063] Memory subsystem 22 is used for caching data.

[0064] In this embodiment, the data storage system can also be referred to as a single-level storage system. The flash memory subsystem 21 provides persistent, large-capacity storage space, power-loss protection for the memory subsystem, and terabyte-level addressing space for the host. The memory subsystem 22 provides large-capacity memory space, a caching mechanism for host access to flash memory data, byte addressing capabilities, and improved data read / write performance. Here, for data such as system checkpoint generation and backup, host 1 can first cache it in the memory subsystem 22 via the CXL subsystem 20, and then write it from the memory subsystem 22 to the flash memory subsystem 21 for storage. In this embodiment, by using a memory semantic solid-state drive 2, the persistent memory-to-SSD operation logic implemented in the operating system is offloaded to the memory semantic solid-state drive 2, achieving a simpler and more efficient single-level storage system.

[0065] In one embodiment, host 1 includes:

[0066] System silencing module 10 is used to control the CPU slave core to enter a silencing state in response to the triggering of a checkpoint operation;

[0067] The checkpoint management module 11 is used to generate checkpoint metadata after the CPU enters a silent state from the core, and to determine the storage addresses of different types of data to be backed up in the checkpoint metadata in the memory semantic solid-state drive 2.

[0068] The status tracking module 12 is used to incrementally update the data to be backed up to the memory semantic solid-state drive based on the storage address.

[0069] The system includes a timer to trigger checkpoint operations. Upon the set time, the checkpoint operation is triggered. After the checkpoint operation is triggered, the system silencing module 10 sends an inter-core interrupt from the CPU master core to the CPU slave core, causing the CPU slave core to enter a silencing state upon receiving the interrupt in user space. At this time, the inter-core interrupt is masked in kernel space to prevent interruption of kernel state modifications. After detecting that the CPU slave core has entered a silencing state, the checkpoint management module 11 generates checkpoint metadata, which may include information such as time, current version number, amount of data sent, and data type to be backed up. Simultaneously, the checkpoint management module 11 determines the storage addresses of different types of data to be backed up in the memory semantic SSD based on the type of data. For example, if the memory of the memory semantic SSD 2 is divided into fixed and swap areas, the code segments and heap space of programs that are not frequently accessed will be placed in the swap area, while the stack space, data segments, and BSS segments that are frequently accessed will be placed in the fixed area to avoid wear and tear on the flash memory of the memory semantic SSD 2. Here, after all CPU slave cores enter a quiescent state, the CPU master core begins copying system data and kernel objects, and the state tracking module 12 updates the corresponding increments to the MS-SSD. Furthermore, after the state tracking module 12 completes the enhancement update, the checkpoint management module 11 marks the checkpoint as complete and adds a global version number, indicating that the newly added checkpoint has taken effect. Additionally, the system quiescent module 10 can send an inter-core interrupt from the CPU master core to the CPU slave cores to notify them to exit the quiescent state and resume normal operation.

[0070] In one embodiment, host 1 further includes:

[0071] The fault recovery module 13 is used to initiate a checkpoint recovery operation after an abnormal power failure event is detected.

[0072] Here, the fault recovery module 13 checks the checkpoint storage status during system startup and initiates a checkpoint recovery operation upon detecting an abnormal power failure event. The specific operation process of the checkpoint recovery operation can be found in existing technologies and will not be elaborated upon here.

[0073] In one embodiment, the CXL subsystem 21 includes:

[0074] CXL interface 201 is connected to host 1;

[0075] CXL controller 202 is used to perform CXL protocol-related functions.

[0076] Here, host 1 may have a CXL root port corresponding to CXL interface 201 to enable data transfer between host 1 and memory semantic solid disk 2 based on CXL protocols such as CXL.mem and CXL.io.

[0077] In one embodiment, the flash memory subsystem 21 includes:

[0078] The power-loss protection battery 211 is used to provide power-loss protection for the memory semantic solid-state drive 2 when the host 1 experiences an abnormal power loss.

[0079] Here, compared to the power-loss protection mechanism using capacitor discharge in existing technologies, this embodiment additionally designs a power-loss protection battery 211 in the flash memory subsystem 21. After the power-loss protection battery 211 is fully charged, it can provide several minutes of power-loss protection time, allowing the data in the memory of the memory semantic solid-state drive 2 to be safely saved to the flash memory, achieving persistence. Furthermore, see [further details omitted]. Figure 1 The flash memory subsystem 21 may also include a DMA engine 212, a flash memory master controller 213, and a NAND flash memory 214. The DMA engine 212 can be used to realize direct data transfer with the host 1. The flash memory master controller 213 is used to write data cached in the memory subsystem 22 to the NAND flash memory 214, and to read the corresponding data into the memory subsystem 22 after receiving a data request sent by the memory subsystem 22.

[0080] In one embodiment, the memory subsystem 22 includes:

[0081] DRAM cache 221, including fixed area and swap area, is used as data read and write cache for flash subsystem 21;

[0082] The memory management unit 222 is used to store the data to be backed up to a fixed area or a swap area according to the storage address of the data to be backed up sent by the host 1.

[0083] Here, after obtaining the storage address of the data to be backed up sent by host 1, memory management unit 222 stores the data to be backed up in the fixed area or the swap area according to the address range corresponding to the fixed area and the swap area, respectively, to achieve precise data storage. For example, when the data to be backed up is the code segment and heap space of a program, the data to be backed up can be stored in the swap area, while when the data to be backed up is the stack space, data segment, or BSS segment, the data to be backed up can be stored in the fixed area. In addition, NAND flash memory 214 also includes a fixed area and a swap area, and the fixed area in NAND flash memory 214 corresponds to the fixed area in DRAM cache 22, that is, data cached in the fixed area of ​​DRAM cache 22 will be written to the fixed area in NAND flash memory 214, and the swap area in NAND flash memory 214 corresponds to the swap area in DRAM cache 22, that is, data cached in the swap area of ​​DRAM cache 22 will be written to the swap area in NAND flash memory 214.

[0084] In summary, in the data storage system provided by the above embodiments, the host writes data to the flash memory space first into memory and then flushes it to the flash memory, so that the temporary data continuously operated by the application is always kept in memory, effectively avoiding the unnecessary wear and tear of the flash memory by temporary data and improving data storage performance.

[0085] Based on the same inventive concept as the foregoing embodiments, please refer to the following: Figure 1 This application also provides a memory semantic solid-state drive, including:

[0086] CXL Subsystem 20 is used for interconnection between the host and memory semantic solid-state drives;

[0087] Flash memory subsystem 21 is used to store data;

[0088] Memory subsystem 22 is used for caching data.

[0089] The flash memory subsystem 21 provides persistent, large-capacity storage, power-loss protection for the memory subsystem, and terabyte-level addressing space for the host. The memory subsystem 22 provides large-capacity memory, a caching mechanism for host access to flash memory data, byte addressing capabilities, and improved data read / write performance. Here, for data such as system checkpoint generation and backup, the host can first cache it in the memory subsystem 22 via the CXL subsystem 20, and then write it from the memory subsystem 22 to the flash memory subsystem 21 for storage. In this embodiment, the persistent memory-to-SSD operation logic implemented in the operating system is offloaded to the memory semantic SSD, enabling a simpler and more efficient single-level storage system based on the memory semantic SSD.

[0090] In one embodiment, the CXL subsystem 21 includes:

[0091] CXL interface 201 connects to the host computer;

[0092] CXL controller 202 is used to perform CXL protocol-related functions.

[0093] Here, the host may have a CXL root port corresponding to the CXL interface to enable data transfer between the host and the memory semantic solid-state drive based on CXL protocols such as CXL.mem and CXL.io.

[0094] In one embodiment, the flash memory subsystem 21 includes:

[0095] The power-loss protection battery 211 is used to provide power-loss protection for the memory semantic solid-state drive 2 when the host experiences an abnormal power loss.

[0096] Here, compared to the power-loss protection mechanism through capacitor discharge in the prior art, this embodiment additionally designs a power-loss protection battery 211 in the flash memory subsystem 21. After the power-loss protection battery 211 is fully charged, it can provide several minutes of power-loss protection time, allowing the data in the memory of the memory semantic solid-state drive 2 to be safely saved to the flash memory, achieving persistence. In addition, the flash memory subsystem 21 may also include a DMA engine 212, a flash memory master controller 213, and a NAND flash memory 214. The DMA engine 212 can be used to realize direct data transfer between the host and the flash memory master controller 213 is used to write the data cached in the memory subsystem 22 to the NAND flash memory 214, and to read the corresponding data into the memory subsystem 22 after receiving a data request sent by the memory subsystem 22.

[0097] In one embodiment, the memory subsystem 22 includes:

[0098] DRAM cache 221, including fixed area and swap area, is used as data read and write cache for flash subsystem 21;

[0099] The memory management unit 222 is used to store the data to be backed up to a fixed area or a swap area according to the storage address of the data to be backed up sent by the host.

[0100] Here, after obtaining the storage address of the data to be backed up sent by the host, the memory management unit 222 stores the data to be backed up in the fixed area or the swap area according to the address range corresponding to the fixed area and the swap area, respectively, to achieve precise data storage. For example, when the data to be backed up is the code segment and heap space of a program, the data to be backed up can be stored in the swap area, while when the data to be backed up is the stack space, data segment, or BSS segment, the data to be backed up can be stored in the fixed area. In addition, the NAND flash memory 214 also includes a fixed area and a swap area, and the fixed area in the NAND flash memory 214 corresponds to the fixed area in the DRAM cache 22, that is, data cached in the fixed area of ​​the DRAM cache 22 will be flushed to the fixed area in the NAND flash memory 214, and the swap area in the NAND flash memory 214 corresponds to the swap area in the DRAM cache 22, that is, data cached in the swap area of ​​the DRAM cache 22 will be flushed to the swap area in the NAND flash memory 214.

[0101] In summary, in the memory semantic solid-state drive provided in the above embodiments, the host writes data to the flash memory space first into memory and then flushes it to the flash memory. This ensures that the temporary data continuously operated by the application is always kept in memory, effectively avoiding the unnecessary wear and tear of the flash memory caused by temporary data and improving data storage performance.

[0102] Based on the same inventive concept as the foregoing embodiments, the foregoing embodiments will be described in detail below through a specific example. In this example, the data storage system is referred to as a single-level storage system.

[0103] Existing technologies mainly include two types of single-level storage systems:

[0104] 1. Single-level storage system based on NVMe SSD (abbreviated as DRAM+SSD). With the increasing popularity of NVMe SSDs, their performance, far exceeding that of mechanical hard drives, has made single-level storage systems using SSDs as checkpoint persistence devices available. However, its disadvantages are: 1) SSDs provide services to the host via a block interface, therefore checkpoint persistence must be performed at the block level, while the CPU operates on data at the byte level. This results in even small modifications to data pages generating 4KB writes, leading to high write amplification and reduced lifespan of the flash memory device. 2) The operating system's persistence operations are less efficient. For example, the operating system needs to maintain fine-grained memory semantic access to file data and page swapping logic, resulting in significant software overhead.

[0105] 2. Single-level storage system based on NVM (abbreviated as DRAM+NVM). To address the write amplification problem of block devices, some solutions deploy SLS on NVM devices. By utilizing byte-addressable NVM, the amount of data written for checkpoint backups is reduced, increasing the frequency of checkpointing. However, its disadvantage is that NVM is more expensive.

[0106] Furthermore, a common drawback of the aforementioned existing technologies is that the design of SLS transparent persistence inevitably suffers from write amplification due to temporary data in the application. From the perspective of traditional multi-tiered storage structures, applications are divided into two parts: the volatile part running in memory and the part requiring persistence. Transparent persistence preserves data that the application wouldn't normally need to persist, and the increased checkpoint frequency amplifies this write overhead, which doesn't exist in traditional storage structures. The higher the checkpoint frequency, the greater the write overhead of temporary data, and the greater the wear and tear on the persistence device—this is a drawback in the SLS system design.

[0107] To achieve a low-cost, high-performance, and low-wear single-level storage system, this example proposes a single-level storage system based on MS-SSDs, using CXL technology as the implementation basis. Figure 2 As shown, the system is mainly divided into two parts: the host and the MS-SSD. The host operating system includes four modules: checkpoint management, fault recovery, status tracking, and system silencing, to support single-level storage. The operating system architecture diagram is shown. The MS-SSD hardware consists of a CXL controller, CXL interface, flash memory main controller, NAND flash memory, memory management unit, DRAM cache, power-loss battery, and DMA engine. Figure 3 As shown. MS-SSDs can be functionally divided into three subsystems: the CXL subsystem, the memory subsystem, and the flash memory subsystem, as follows... Figure 4 As shown. The main part of the CXL subsystem is the CXL controller, which performs CXL protocol-related functions, including the transaction layer, link layer, and translation layer. The memory subsystem includes four modules: multi-level page tables, page fault handling, memory management, and prefetching algorithms. Multi-level page tables and page fault handling are implemented by the processor in the memory subsystem or the main controller in the MS-SSD, while memory management is implemented by the memory management unit. The flash memory subsystem is the prototype of a traditional SSD, and its main function is the flash memory translation layer, including modules for address mapping, garbage collection, wear leveling, and power-loss protection.

[0108] This example implements single-level storage-related functional modules within the operating system kernel. The checkpoint management module maintains global checkpoint information and controls the checkpoint generation process. The state tracking module tracks pages modified by the kernel and applications in the current time slice using a copy-on-write mechanism. The fault recovery module checks the checkpoint storage status during system startup and initiates checkpoint recovery upon detecting an abnormal power failure. The system silencing module suspends or resumes application execution on cores other than the main core using inter-core interrupts.

[0109] The basic function of single-level storage is to generate and back up system checkpoints. The process is as follows: 1) System Silence: When the kernel timer triggers the checkpoint mechanism, the CPU master core sends an inter-core interrupt to other cores (i.e., CPU slave cores). Other cores, upon receiving the inter-core interrupt in user space, enter a silent state. In kernel space, the inter-core interrupt is masked to prevent interruption of kernel state modifications. 2) Checkpoint Generation: After system silence, the checkpoint management module generates checkpoint metadata and prepares the addresses for storing various data on the MS-SSD. 3) Kernel State Backup: After all cores are silent, the CPU master core begins copying system data and kernel objects, updating incrementally to the MS-SSD through the state tracking module. 4) User State Backup: Each core incrementally updates the application data running on its local machine to the MS-SSD. 5) The checkpoint management module marks the checkpoint as complete and adds a global version number, indicating that the new checkpoint has taken effect. 6) The CPU master core sends an inter-core interrupt to other cores, notifying them to resume execution.

[0110] Here, the MS-SSD's CXL subsystem supports two access protocols: CXL.mem and CXL.io, such as... Figure 5 As shown. This example supports low-latency memory access via byte-addressing through CXL.mem and traditional block device access through CXL.io. The CXL subsystem enables fast interconnect, the memory subsystem provides the host with access speeds such as extended memory, and the flash subsystem provides ample storage space. The flash space of the MS-SSD can be addressed byte-by-byte through CXL memory. When the host accesses a page that hits a page in CXL memory, it reads and writes directly; when a page miss occurs, a page fault is triggered, and the memory subsystem submits an I / O request to the flash subsystem to read the logical block corresponding to the virtual address into memory.

[0111] The multi-level page tables in the memory subsystem are used to map virtual addresses to physical addresses, with the virtual address range being the size of the flash memory. Since flash memory is much larger than RAM, using multi-level page tables saves memory usage. Page faults are triggered by interrupts in the memory management unit, indicating a page table lookup failure. After an interrupt occurs, the CXL controller assists the memory subsystem in swapping pages in and out. The memory management module is responsible for allocating memory and managing memory swapping in and out. Here, MS-SSD divides memory into two categories: swap space and fixed space. The swap space is similar to the operating system's swap partition (Swap space is a form of virtual memory. To cope with applications that require a lot of memory, the system uses disk space as memory. When physical memory is insufficient, some temporarily unnecessary data is swapped to the swap space, also called the swap file or page file). After memory is exhausted, the least accessed pages are swapped out. Pages in the fixed space are not swapped in or out and are written to the flash memory subsystem for persistence after normal power-off or abnormal power loss. The host can set the page to a fixed area through a custom interface to prevent temporary data from being written to flash memory.

[0112] The flash memory subsystem is structurally similar to that of a traditional SSD, with the key difference being its power-loss protection mechanism. Traditional SSDs can write hundreds of megabytes of data from RAM to flash memory to preserve metadata and ongoing I / O requests. This process typically relies on capacitor discharge, providing millisecond-level power-loss protection. MS-SSDs, however, incorporate an additional power-loss protection battery. Once fully charged, this battery provides several minutes of protection, allowing data in large CXL memory modules to be safely saved to flash memory for persistence. This process is transparent to the host, enabling it to treat the MS-SSD as a persistent memory device. It experiences cache hits with access latency comparable to RAM, and write operations to fixed areas do not cause wear and tear.

[0113] The low write wear checkpoint proposed in this example is achieved through the mechanism described above. For example... Figure 6As shown, the checkpoint management module allocates data to different CXL memory spaces based on data type. Specifically, the program's code segment and heap space are placed in the swap area, while the stack space, data segment, and BSS segment are placed in a fixed area. Code segment data is typically read-only and will not be changed after a single flush, so it is placed in the swap area awaiting swapping out. The heap space is mainly used by applications using single-level storage to store large amounts of data, which will be persisted through the single-level storage mechanism; therefore, the heap space is also placed in the swap partition. Global and local variables stored in the stack space, data segment, and BSS segment are frequently accessed during program execution, so they are allocated to the fixed area to avoid wear and tear on the flash memory. Furthermore, the system kernel is not entirely persisted by checkpoints; all kernel areas are rebuilt during system startup, and the fault recovery module reconstructs the kernel data based on the contents of the checkpoints. Therefore, kernel objects and system data saved in checkpoints change frequently during kernel operation and will also be placed in the fixed area.

[0114] In summary, the data storage system provided in the above embodiments has the following advantages: 1) It eliminates write wear caused by temporary data in the SLS system. MS-SSD uses DRAM as a cache for NAND. Host writes to flash memory first enter DRAM and are then flushed to NAND. Frequently written hot data pages remain in DRAM. Temporary data constantly manipulated by applications falls into this category. Therefore, the DRAM inside the MS-SSD effectively avoids invalid wear of temporary data. 2) It leverages the characteristics of DRAM combined with NAND in MS-SSD to achieve performance similar to the NVM solution at a lower cost. 3) It offloads complex persistence logic to the device, allowing the system to complete data persistence using only simple memory access methods, thus improving the efficiency of the storage stack.

[0115] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0116] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0117] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data storage system, characterized in that, Includes a host computer and a memory-based solid-state drive connected to the host computer; The host is used to store data to the memory semantic solid-state drive; The memory semantic solid-state drive includes: The CXL subsystem is used to enable interconnection between the host and the memory semantic solid-state drive; Flash memory subsystem for storing the data; The memory subsystem is used to cache the data. The host includes: The system silencing module is used to respond to checkpoint operations by controlling the CPU slave cores to enter a silencing state through the CPU main core. The checkpoint management module is used to generate checkpoint metadata after the CPU enters a silent state from the core, and to determine the storage addresses of different types of data to be backed up in the checkpoint metadata in the memory semantic solid-state drive. The status tracking module is used to incrementally update the data to be backed up to the memory semantic solid-state drive according to the storage address; The fault recovery module is used to initiate checkpoint recovery operations after an abnormal power failure event is detected.

2. The data storage system according to claim 1, characterized in that, The CXL subsystem includes: The CXL interface connected to the host; The CXL controller is used to perform functions related to the CXL protocol.

3. The data storage system according to claim 1, characterized in that, The memory subsystem includes: The DRAM cache, including a fixed area and a swap area, is used as a data read / write cache for the flash memory subsystem. The memory management unit is used to store the data to be backed up in the fixed area or the exchange area according to the storage address of the data to be backed up sent by the host.

4. The data storage system according to claim 1, characterized in that, The flash memory subsystem includes: A power-loss protection battery is used to provide power-loss protection for the memory semantic solid-state drive when the host experiences an abnormal power loss.

5. A memory-semantic solid-state drive, applied to the data storage system as described in any one of claims 1 to 4, characterized in that, include: The CXL subsystem is used to enable interconnection between the host and the memory semantic solid-state drive; The flash memory subsystem is used to store data; The memory subsystem is used to cache data.

6. The memory semantic solid-state drive according to claim 5, characterized in that, The CXL subsystem includes: The CXL interface connected to the host; The CXL controller is used to perform functions related to the CXL protocol.

7. The memory semantic solid-state drive according to claim 5, characterized in that, The memory subsystem includes: The DRAM cache, including a fixed area and a swap area, is used as a data read / write cache for the flash memory subsystem. The memory management unit is used to store the data to be backed up in the fixed area or the exchange area according to the storage address of the data to be backed up sent by the host.

8. The memory semantic solid-state drive according to claim 5, characterized in that, The flash memory subsystem includes: A power-loss protection battery is used to provide power-loss protection for the memory semantic solid-state drive when the host experiences an abnormal power loss.

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