A branch target buffer and a method of designing the same

Abstract

The application discloses a branch target buffer and a design method thereof, and comprises the following steps: S1, compressing address offsets contained in different slots of the branch target buffer, so that each branch target buffer entry can store two short address offsets; S2, constructing a common offset bit at the same time in step S1, the size of the common offset bit is set as a difference value between a long branch address offset and a short branch address offset; when the branch target buffer needs to store one long address offset and one short address offset, the common offset bit is used to store a part of the long address offset which cannot be stored, and the slot using the common offset bit is marked. The application discloses the branch target buffer and the design method thereof, solves the resource waste caused by the table entry pairing when one long address offset and one short address offset are stored in the FTB, and ensures that the required address information can be completely stored.

Description

Technical Field

[0001] This invention belongs to the field of electronic computer and microprocessor architecture, and specifically relates to a branch target buffer and its design method. Background Technology

[0002] A branch target buffer (BTB) is a hardware cache primarily used to record the target address of branch instructions. Its main goal is to reduce branch overhead to zero, meaning the predicted branch target address is fetched during the instruction fetch phase (IF segment), and then the next instruction is executed sequentially. In practice, after a branch instruction is successfully executed, its address and its corresponding branch target address are saved in a buffer. This buffer is identified by the branch instruction's address, forming a table-like structure. The main function of the BTB is to determine whether to use the BTB's target address for the jump, while the branch history table determines whether to use the BTB's target address for the jump.

[0003] In existing branch target buffer (BTB) designs, the BTB typically stores the offset of the target address instead of the entire branch target address. This effectively reduces the number of bits in the branch target address, thus compressing the BTB. Leveraging branch locality, the target address bits in the BTB can be set to the size required for short branches. When long-distance branches require more target address bits, the target address is shared by two short branch BTB entries. These two BTB entries form a set, and the corresponding BTB pairing position is set high to indicate the pairing of the two BTB entries.

[0004] A Branch Prediction Buffer (FTB) is a buffer used to store the target address of branch instructions. In modern computer systems, branch prediction is an important optimization technique that helps the processor determine the execution path of the next instruction more quickly, thereby improving program execution speed. The main function of the FTB is to obtain the predicted branch target address during the instruction fetch stage, i.e., the IF segment, and then execute the next instruction sequentially. Specifically, after a branch instruction is successfully executed, the address of the instruction and its corresponding branch target address are saved in a buffer. This buffer is identified by the address of the branch instruction, forming a table-like structure. This design is primarily aimed at improving the accuracy and efficiency of branch prediction.

[0005] FTB is a new type of branch target buffer. FTB uses fetch blocks as the basic unit to limit the branch prediction width to accommodate higher frequencies. Traditional branch target buffers (BTBs) can only store basic information for one branch instruction. FTBs can store branch information for an entire instruction block. However, because each entry in an FTB stores two instructions, when one instruction is a long branch and the other a short branch, it is still considered that an FTB entry needs to be paired. This leads to wasted space resources in the short branch instruction slot's address offset, reducing the space utilization of the FTB. With the same amount of space, the FTB can store less branch information, resulting in more lost branch information. Summary of the Invention

[0006] The first objective of this invention is to provide a design method for a branch target buffer, addressing the problems in the prior art.

[0007] Therefore, the above-mentioned objectives of the present invention are achieved through the following technical solutions:

[0008] A method for designing a branch target buffer, characterized by the following steps:

[0009] S1, Compress the address offsets contained in different slots in the branch target buffer so that each branch target buffer entry can store two short address offsets;

[0010] S2, Simultaneously with step S1, a shared offset bit is constructed. The size of the shared offset bit is set to the difference between the address offsets of the long branch and the short branch. When the branch target buffer needs to store both long and short address offsets, the shared offset bit is used to store the part of the long address offset that cannot be stored. At the same time, the slots using the shared offset bit are marked.

[0011] While adopting the above technical solutions, the present invention may also adopt or combine the following technical solutions:

[0012] As a preferred technical solution of the present invention: when the branch target buffer needs to store two long branches, an entry with an unused shared offset is selected from the corresponding group of branch target buffers for pairing, and the address offset of the other long branch that cannot be stored is written into the shared offset of the paired entry; if the branch target buffer needs to store two long branches, and the shared offsets of other FTBs in the same group are all used, a branch target buffer entry is selected for pairing according to the least recently used algorithm. At this time, it only needs to occupy the shared offset of the paired entry, and the paired entry can still be used to store short branch information of other instruction blocks when the branch target buffer is updated.

[0013] A second objective of this invention is to provide a branch target buffer, addressing the problems in the prior art.

[0014] Therefore, the above-mentioned objectives of the present invention are achieved through the following technical solutions:

[0015] A target buffer, characterized in that it includes slots for storing branch instructions and slots for storing address offsets of jump instructions, wherein the slots for storing address offsets of jump instructions are configured as a shared address offset space, and the branch target buffer entry structure is dynamically adjusted through the shared address offset space.

[0016] This invention offers the following advantages: The branch target buffer and its design method, by dynamically adjusting the branch target buffer entry structure through a shared address offset space, ensures that when the address offset bits within a slot of a branch target buffer entry are insufficient, its own shared address offset space is used first. This cleverly and efficiently solves the resource waste caused by entry pairing when storing two instruction address offsets (one long and one short) in an FTB, while ensuring that the required address information can be stored completely. With the same space, this technical solution can store more branch information, reducing the probability of FTB loss. This not only improves the address offset storage capacity but also provides a more flexible mechanism for FTB management and operation. Attached Figure Description

[0017] Figure 1 A diagram illustrating a compression scheme based on the design of a branch target buffer in the existing technology;

[0018] Figure 2 This is a design diagram of the branch target buffer of the present invention. Detailed Implementation

[0019] The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] A branch target buffer and its design method include the following steps: S1, compressing the address offsets contained in different slots in the FTB so that each FTB entry can store two short address offsets;

[0021] S2, Simultaneously with step S1, a shared offset bit is constructed. The size of the shared offset bit is set to the difference between the address offsets of the long branch and the short branch. When the FTB needs to store both long and short address offsets, the shared offset bit is used to store the portion of the long address offset that cannot be stored. At the same time, the slots using the shared offset bit are marked. When the FTB needs to store two long branches, entries that do not use the shared offset are preferentially selected from the corresponding group of FTBs for pairing. The address offset of the other long branch that cannot be stored is written into the shared offset of the paired entry. If the FTB needs to store two long branches and the shared offsets of other FTBs in the same group are all used, an FTB entry is selected for pairing according to the least recently used algorithm. At this time, it only needs to occupy the shared offset of the paired entry. The paired entry can still store the short branch information of other instruction blocks when the branch target buffer is updated.

[0022] FTB stands for Branch Target Buffer.

[0023] The target buffer of the branch target buffer design method of the present invention includes a slot for storing branch instructions and a slot for storing the address offset of jump instructions. The slot for storing the address offset of jump instructions is set as a shared address offset space, and the FTB table entry structure is dynamically adjusted through the shared address offset space.

[0024] Due to the need to compress the FTB entry space in the branch target buffer, the address offset bits of a single FTB entry may not be sufficient for the address offset requirements of long-distance branches. Therefore, two FTB entries need to be merged into one FTB entry pair and marked by a pairing bit. However, when the two branch instructions stored in the FTB are one long and one short, simple pairing would waste the pairing space corresponding to the short branch instruction. Therefore, a design method is proposed to avoid pairing caused by long and short branches by adding shared space in the FTB. Only when both branches are long branches will they be paired with another FTB entry, thereby improving the utilization rate of FTB space resources.

[0025] Example 1

[0026] like Figure 2As shown, in a branch target buffer of the present invention, two slots are specifically set up to store the address offsets of branch instructions or jump instructions. In the design method of the branch target buffer of the present invention, the initial step is to compress the address offsets contained in different slots in the FTB, so that each FTB entry can store two short address offsets. Simultaneously, a shared offset bit is designed, the size of which is set to the difference between the address offsets of the long branch and the short branch. When the FTB needs to store both long and short address offsets, the shared offset bit is used to store the portion of the long address offset that cannot be stored. The slots using the shared offset bit are marked. When the FTB needs to store two long branches, entries that do not use the shared offset are preferentially selected from the corresponding set of FTBs for pairing, and the address offset of the other long branch that cannot be stored is written into the shared offset of the paired entry. If an FTB needs to store two long branches, and the shared offsets of other FTBs in the same group are all in use, an FTB entry is selected for pairing according to the least recently used algorithm. At this time, it only needs to occupy the shared offset of the paired entry. The paired entry can still store the short branch information of other instruction blocks when the branch target buffer is updated.

[0027] By dynamically adjusting the FTB entry structure by setting a shared address offset space, the problem of wasted space resources caused by pairing two FTB entries with two address offsets of different lengths (one long and one short) is solved, thus achieving a more efficient compression method.

[0028] By setting a shared address offset, when an FTB entry stores two long address offsets, after being paired with an FTB entry, the paired entry can still store two short branch information of the new instruction block. When the number of entries is the same, this technical solution effectively reduces the missing rate of FTB entries compared with the original pairing method.

[0029] like Figure 1 As shown, in the original compression scheme, after the FTB entries are paired, the slot for storing the second branch information or the slot address offset for storing the first branch information will be wasted when storing the address offset of two instructions, one long and one short.

[0030] In the existing technology, the wasted space resources of the storage address offset in the short branch instruction slot lead to a reduction in the space utilization of the FTB. As a result, the FTB can store less branch information in the same space, leading to the loss of more branch information.

[0031] like Figure 2As shown in the example, by setting a general address offset space, the branch target buffer and its design method of this invention avoid the situation where FTB entries storing two instruction address offsets of different lengths are stored in pairs. Such pairing only occurs when two long address offsets need to be stored. Furthermore, this pairing does not affect the stored information of two short address offsets in a new instruction block within the paired entry, thereby achieving maximum efficient utilization of space resources.

[0032] This invention solves the problem by improving space utilization. That is, using this compression scheme in the same space, more branch instruction information can be stored, reducing the risk of branch information loss.

[0033] The above specific embodiments are used to explain and illustrate the present invention, and are only preferred embodiments of the present invention, not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A design method for a branch target buffer, characterized in that: Includes the following steps: S1, Compress the address offsets contained in different slots in the branch target buffer so that each branch target buffer entry can store two short address offsets; S2, Simultaneously with step S1, a shared offset bit is constructed, the size of which is set to the difference between the long branch and short branch address offsets; when the branch target buffer needs to store both long and short address offsets, the shared offset bit is used to store the part that cannot be stored in the long address offset, and the slots using the shared offset bit are marked. The branch target buffer is an FTB.

2. The design method of a branch target buffer as described in claim 1, characterized in that: When a branch target buffer needs to store two long branches, it first selects entries from its corresponding set of branch target buffers that do not use a shared offset for pairing, and writes the address offset of the other long branch that cannot be stored into the shared offset of the paired entry. If the branch target buffer needs to store two long branches, and the shared offsets of other FTBs in the same group are all used, a branch target buffer entry is selected for pairing according to the least recently used algorithm, and only occupies the shared offset of the paired entry. The paired entry is used to store short branch information of other instruction blocks when the branch target buffer is updated.

3. A target buffer based on the design method of a branch target buffer according to claim 1 or 2, characterized in that: It includes slots for storing branch instructions and slots for storing the address offsets of jump instructions. The slots for storing the address offsets of jump instructions are set to a shared address offset space, and the branch target buffer entry structure is dynamically adjusted through the shared address offset space.

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