Dual-cpu system of amd platform and its starting method

Abstract

The application provides a dual-CPU system of an AMD platform and a starting method thereof, and relates to the technical field of computers.The system comprises a first CPU, a second CPU, a starting control unit and a gating switch.The mark pin of the first CPU is configured as a connection mode of a main CPU, the mark pin of the second CPU is configured as a connection mode of a secondary CPU, the functional pins AMPL of the first CPU and the second CPU are respectively connected to the starting control unit, the functional pins USB, PCIe, SPI, MISC and eSPI of the main CPU are respectively connected to the starting control unit, the first end of the gating switch is connected to the first CPU, the second end of the gating switch is connected to the second CPU, and the gating end of the gating switch is connected to the starting control unit.The starting control unit is used for reading the model information of the first CPU and the second CPU through the AMPL signal, and in the case that the model information of the two CPUs is different, the gating switch is controlled to disconnect the connection between the first end and the second end, and the main CPU is controlled to start.The application solves the problem that two CPUs cannot start due to different models in the dual-CPU architecture.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a dual-CPU system on an AMD platform and its boot method. Background Technology

[0002] A server is a computer system used to store, process, and provide network services. Servers are typically equipped with powerful hardware and high-speed network connections, possessing reliability and stability. Server technologies include operating systems, network protocols, security mechanisms, and data storage technologies. Common server types include web servers, database servers, and application servers, which support the operation of websites, data storage, applications, and other network services. The technological background of servers focuses on optimizing performance, improving security, achieving high availability, and handling a large number of concurrent requests. In this network age, high server stability is what all cloud service providers strive for, hoping that users can enjoy stable and smooth services.

[0003] To provide more stable and smoother service, existing AMD server system architectures support AMD platforms with two CPUs within a single server system. Traditional AMD platform dual-CPU architectures, such as... Figure 1 As shown, the two CPUs are interconnected via XGMII, with the main CPU (CPU0) connected to the secondary CPU (CPU1) via XGMII. They exchange data, and CPU1 shares some of the computational work with CPU0, also transmitting hardware information through this connection. Specifically, in the hardware design, certain fixed pins of the two CPUs are configured with voltage settings. These pins can be called marker pins. Different connections to these marker pins indicate whether the CPU is the main CPU or the secondary CPU. For example, the marker pins SA[0] and SA[1] of CPU0 and CPU1 are configured with voltage settings to distinguish between the main CPU and the secondary CPU. Figure 1 In the middle, both SA[0] and SA[1] of CPU0 are grounded, that is, configured as low level, with CPU0 as the main CPU;

[0004] CPU1's SA[0] is configured to high level, and SA[1] is configured to low level, with CPU1 serving as the secondary CPU. The main CPU's functional pins AMPL, USB, PCIe, and eSPI are connected to the corresponding pins of the Baseboard Management Controller (BMC). The functional pin SPI is connected to the SPI Flash, and the functional pin MISC is connected to the CPLD. The CPLD is connected to the eSPI terminal of the BMC. The corresponding functional pins AMPL, USB, PCIe, eSPI, SPI, and MISC on the secondary CPU are all left floating. Figure 1 In the dual-CPU architecture, the connections of each functional pin and the voltage settings of the marked pins are fixed. The master and slave settings of CPU0 and CPU1 cannot be changed in the fixed hardware design. Only the functional pins of CPU0 are connected to the corresponding pins of CPLD and BMC, while these functional pins of CPU1 are left floating, that is, not connected to any place. For example, since CPU1 does not need to control the timing of system boot, the MISC signal (this signal includes the power-on signal, restart signal and power-on status signal, etc.) is left floating.

[0005] Existing dual-CPU architectures based on AMD platforms suffer from the following issues: When CPU0 and CPU1 are different models or generations of CPUs, the server system cannot boot and run normally. For example, if 7th generation and 6th generation AMD CPUs are mixed, the management software in the BMC (Browser Management Center) cannot recognize that CPU0 and CPU1 are different CPUs. CPU0 will interact with CPU1 via xGMII, and this interaction will fail when the two CPUs are different models or generations, resulting in a system crash during boot and inability to boot normally. Due to the complex timelines for server setup and maintenance, data centers are often located in remote areas, or maintenance personnel have other tasks. Without a new solution, servers are often left idle, awaiting disassembly and re-analysis, and unable to continue providing service. Summary of the Invention

[0006] The purpose of this invention is to provide a dual-CPU system for an AMD platform and its boot method, in order to solve the technical problem that the existing dual-CPU architecture cannot boot and run normally when there are two CPUs of different models or generations.

[0007] This invention provides a dual-CPU system for an AMD platform, comprising: a first CPU, a second CPU, a power-on control unit, and a selection switch;

[0008] The first CPU's marker pin is configured as a main CPU connection, and the second CPU's marker pin is configured as a secondary CPU connection. The AMPL function pins of the first CPU and the second CPU are respectively connected to the power-on control unit. The main CPU's USB, PCIe, SPI, MISC, and eSPI function pins are respectively connected to the power-on control unit.

[0009] The first end of the strobe switch is connected to the first CPU, the second end is connected to the second CPU, and the strobe end is connected to the power-on control unit.

[0010] The power-on control unit is used to read the model information of the first CPU and the second CPU through the AMPL signal. If the model information of the two CPUs is different, it controls the gating switch to disconnect the connection between the first terminal and the second terminal and controls the main CPU to power on.

[0011] According to the present invention, a dual-CPU system for an AMD platform includes a power-on control unit comprising: a baseboard management controller, a CPLD, and a memory.

[0012] The AMPL functional pins of the first CPU and the second CPU are respectively connected to the corresponding pins of the baseboard management controller. The SPI functional pin of the main CPU is connected to the memory. The MISC functional pin of the main CPU is connected to the CPLD. The CPLD is connected to the corresponding pins of the baseboard management controller. The USB, PCIe and eSPI functional pins of the main CPU are respectively connected to the corresponding pins of the baseboard management controller. The selection terminal of the strobe switch is connected to the baseboard management controller.

[0013] The baseboard management controller is used to read the model information of the first CPU and the second CPU through the AMPL signal. If the model information of the two CPUs is different, it controls the gating switch to disconnect the connection between the first terminal and the second terminal and controls the main CPU to power on.

[0014] According to the present invention, a dual-CPU system for an AMD platform further includes: a CPU selection unit and a pin configuration circuit for marking pins;

[0015] The first CPU's functional pins USB, PCIe, SPI, MISC, and eSPI are connected to the first input pin group of the CPU selection unit. The second CPU's functional pins USB, PCIe, SPI, MISC, and eSPI are connected to the second input pin group of the CPU selection unit. The CPU selection unit's output pin group is connected to the power-on control unit. The CPU selection unit's selection pin is connected to the power-on control unit. The marking pin configuration circuit is connected to the marking pins of the power-on control unit and the second CPU.

[0016] The power-on control unit is used to read the model information of the first CPU and the second CPU respectively through the AMPL signal. When the model information of the two CPUs is the same, it controls the first and second terminals of the selection switch to remain connected, sends a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, controls the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and controls the main CPU to power on.

[0017] When the model information of the two CPUs is different, the control switch disconnects the connection between the first and second terminals, determines the target CPU, sends a selection command to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, and makes the target CPU the main CPU. If the target CPU is the first CPU, the control switch powers on the main CPU. If the target CPU is the second CPU, the control switch configures the marking pin of the second CPU to change the second CPU from a secondary CPU to a main CPU, and the control switch powers on the main CPU.

[0018] According to the present invention, a dual-CPU system for an AMD platform includes a power-on control unit comprising: a baseboard management controller, a CPLD, a first memory, a second memory, and a multiplexer.

[0019] The AMPL function pins of the first CPU and the second CPU are respectively connected to the corresponding pins of the baseboard management controller. The USB, PCIe, and eSPI output pins of the CPU selection unit are connected to the corresponding pins of the baseboard management controller. The MISC output pin of the CPU selection unit is connected to the CPLD. The CPLD is connected to the corresponding pin of the baseboard management controller. The SPI output pin of the CPU selection unit is connected to the first selection terminal of the multiplexer. The second selection terminal of the multiplexer is connected to the corresponding pin of the baseboard management controller. The third selection terminal of the multiplexer is connected to the first memory. The gating terminal of the multiplexer is connected to the baseboard management controller. The selection pin of the CPU selection unit is connected to the baseboard management controller. The tag pin configuration circuit is connected to the tag pins of the baseboard management controller and the second CPU.

[0020] The baseboard management controller is connected to the second memory and is used to read the model information of the first CPU and the second CPU respectively through the AMPL signal. When the model information of the two CPUs is the same, it controls the first and second terminals of the gating switch to remain connected and sends a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group. It controls the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU. The baseboard management controller is used to confirm that the power-on configuration information of the main CPU is written from the second memory to the first memory through the multiplexer and then controls the main CPU to power on.

[0021] When the model information of the two CPUs is different, the control switch disconnects the connection between the first and second terminals, determines the target CPU, and sends a selection command to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the main CPU. When the target CPU is the first CPU, the baseboard management controller confirms that the power-on configuration information of the main CPU has been written from the second memory to the first memory through the multiplexer, and then controls the main CPU to power on. When the target CPU is the second CPU, the control pin configuration circuit configures the marking pin of the second CPU, changing the second CPU from a secondary CPU to a main CPU. The baseboard management controller confirms that the power-on configuration information of the main CPU has been written from the second memory to the first memory through the multiplexer, and then controls the main CPU to power on.

[0022] According to a dual-CPU system for an AMD platform provided by the present invention, the baseboard management controller is configured to send a gating instruction to the gating terminal of the multiplexer to connect the second and third terminals of the multiplexer to obtain the current first power-on configuration information in the first memory, and to obtain the second power-on configuration information of the target CPU from the second memory according to the determined target CPU. If the first and second power-on configuration information are the same, a gating instruction is sent to the gating terminal of the multiplexer to connect the first and third terminals of the multiplexer, so that the main CPU obtains the power-on configuration information in the first memory via an SPI signal and powers on. If the first and second power-on configuration information are different, the second power-on configuration information is written into the first memory, and a gating instruction is sent to the gating terminal of the multiplexer to connect the first and third terminals of the multiplexer, so that the main CPU obtains the power-on configuration information in the first memory via an SPI signal and powers on.

[0023] According to the present invention, a dual-CPU system for an AMD platform includes a pin configuration circuit comprising: a first MOSFET, a second MOSFET, a third MOSFET, an inverter, a first resistor, a second resistor, a first diode, and a second diode.

[0024] The gate of the first MOS transistor is connected to the substrate management controller, the source is connected to the cathode of the first diode, the anode of the first diode is connected to the gate of the second MOS transistor and connected to the high-level terminal through the first resistor, and the drain of the first MOS transistor is grounded.

[0025] The source of the second MOS transistor is connected to the high-level terminal, and the drain is connected to the marking pin of the second CPU through the second resistor;

[0026] The input terminal of the inverter is connected to the substrate management controller, the output terminal is connected to the gate of the third MOS transistor, the source of the third MOS transistor is connected to the marker pin of the second CPU, and the drain is grounded.

[0027] The anode of the second diode is connected to the voltage monitoring pin of the second CPU, and the cathode is connected to the source of the first MOS transistor.

[0028] This invention also provides a boot method for a dual-CPU system on an AMD platform, implemented based on the aforementioned dual-CPU system on an AMD platform. The method is applied to the boot control unit and includes:

[0029] Obtain the model information of the first CPU and the second CPU;

[0030] If the model information of the first CPU is the same as that of the second CPU, the control gating switch maintains the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

[0031] If the model information of the first CPU is different from that of the second CPU, the control gating switch disconnects the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

[0032] This invention also provides a boot method for a dual-CPU system on an AMD platform, implemented based on the aforementioned dual-CPU system on an AMD platform. The method is applied to the boot control unit and includes:

[0033] Obtain the model information of the first CPU and the second CPU;

[0034] When the model information of the first CPU is the same as that of the second CPU, the first and second terminals of the selection switch are kept connected, a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and the main CPU is powered on.

[0035] If the model information of the first CPU is different from that of the second CPU, the gating switch is controlled to disconnect the connection between the first and second ends, and the target CPU is determined. A selection command is sent to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is controlled to power on. If the target CPU is the second CPU, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a master CPU, and the master CPU is controlled to power on.

[0036] The present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the power-on method for a dual-CPU system of the AMD platform as described above.

[0037] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the boot method for a dual-CPU system of the AMD platform as described above.

[0038] The present invention provides a dual-CPU system for an AMD platform and its boot method. The first CPU's marked pin is configured as the primary CPU connection, and the second CPU's marked pin is configured as the secondary CPU connection. The AMPL function pins of the first and second CPUs are respectively connected to a boot control unit. The primary CPU's USB, PCIe, SPI, MISC, and eSPI function pins are respectively connected to the boot control unit. A strobe switch has its first terminal connected to the first CPU, its second terminal connected to the second CPU, and its strobe terminal connected to the boot control unit. The boot control unit reads the model information of the first and second CPUs via the AMPL signal. If the model information differs, the control unit controls the strobe switch to disconnect the first and second terminals and boots the primary CPU. Because a strobe switch is set between the first and second CPUs, when the boot control unit detects a difference in model information between the first and second CPUs, it controls the strobe switch to disconnect the connection between the two CPUs. The primary CPU no longer interacts with the secondary CPU of a different model; instead, it boots and runs as a single CPU, thus avoiding the problem of boot failure due to different models of the primary and secondary CPUs. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the architecture of a dual-CPU system on the AMD platform in the existing technology;

[0041] Figure 2 This is one of the architectural diagrams of a dual-CPU system on the AMD platform provided by the present invention;

[0042] Figure 3 This is the second schematic diagram of the architecture of the dual-CPU system on the AMD platform provided by the present invention;

[0043] Figure 4 This is one of the schematic diagrams of the boot method for a dual-CPU system on an AMD platform provided by the present invention;

[0044] Figure 5 This is the second schematic diagram of the boot method for a dual-CPU system on an AMD platform provided by the present invention;

[0045] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0047] The hot-swap identification method for hot-swapable components provided by the present invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0048] The dual-CPU system architecture of the AMD platform in this embodiment of the invention is as follows: Figure 2 As shown, it includes: a first CPU, a second CPU, a power-on control unit, and a selection switch. The first CPU is... Figure 2 CPU0 is the first CPU, and the second CPU is the second CPU. Figure 2 CPU1.

[0049] The marking pin of the first CPU is configured as the main CPU connection, and the marking pin of the second CPU is configured as the secondary CPU connection. The AMPL function pins of the first CPU and the second CPU are respectively connected to the power-on control unit. The function pins USB, PCIe, SPI, MISC, and eSPI of the main CPU are respectively connected to the power-on control unit. Among them, the pins SA[0] and SA[1] of CPU0 and CPU1 are marking pins. The connection mode of the marking pins indicates whether it is the main CPU or the secondary CPU. In this embodiment, the CPU with both SA[0] and SA[1] connected to a low level is the main CPU, SA[0] is connected to a high level, and SA[1] is connected to a low level is the secondary CPU. That is, CPU0 is the main CPU and CPU1 is the secondary CPU. The function pins USB, PCIe, SPI, MISC, and eSPI of CPU0, which is the main CPU, are respectively connected to the power-on control unit, and the function pins of CPU1, which is the secondary CPU, are left floating.

[0050] The first terminal of the gating switch is connected to the first CPU, the second terminal is connected to the second CPU, and the gating terminal is connected to the power-on control unit. The gating switch is an xGMI multiplexer (xGMI MUX), and the first and second terminals of the xGMI MUX are connected to CPU0 and CPU1 respectively via xGMII.

[0051] The power-on control unit is used to read the model information (including CPU model and CPU generation) of the first CPU and the second CPU respectively through the AMPL signal. If the model information of the two CPUs is different, the control unit controls the gating switch to disconnect the connection between the first terminal and the second terminal and controls the main CPU to power on.

[0052] In this embodiment of the AMD platform dual-CPU system, a gating switch is set between the first CPU and the second CPU. When the power-on control unit detects that the model information of the first CPU and the second CPU are different, it controls the gating switch to disconnect the connection between the first CPU and the second CPU. The primary CPU no longer interacts with the secondary CPU of a different model, but instead powers on and runs as a single CPU, thus avoiding the problem of the server failing to power on due to the different models of the primary and secondary CPUs. After the server powers on and runs, only one CPU is running, which can temporarily handle business at lower performance, reducing or even avoiding business losses. The appropriate CPU can be replaced when staff have time.

[0053] In some embodiments, the power-on control unit includes: a baseboard management controller ( Figure 2 BMC), CPLD and memory ( Figure 2 (SPI Flash).

[0054] The AMPL pins of the first and second CPUs are respectively connected to the corresponding pins of the baseboard management controller. The SPI pin of the main CPU is connected to the memory. The MISC pin of the main CPU is connected to the CPLD. The CPLD is connected to the corresponding pin of the baseboard management controller. The USB, PCIe, and eSPI pins of the main CPU are respectively connected to the corresponding pins of the baseboard management controller. The selector of the gating switch is connected to the baseboard management controller. Specifically, the AMPL pin of CPU0 is connected to the CPU0_AMPL pin of the BMC, the USB pin is connected to the USB pin of the BMC, the PCIe pin is connected to the PCIe×1 pin of the BMC, the eSPI pin is connected to the eSPI pin of the BMC, the SPI pin is connected to the memory, the MISC pin is connected to the MISC pin of the CPLD, the control terminal of the CPLD is connected to the eSPI pin of the BMC, the AMPL pin of CPU1 is connected to the CPU1_AMPL pin of the BMC, and the selector of the gating switch, SEL, is connected to the corresponding pin of the BMC through XGMI_MUX_SEL.

[0055] The baseboard management controller (BMC) reads the model information of the first CPU and the second CPU via the AMPL signal. If the model information differs, the BMC controls the gating switch to disconnect the connection between the first and second terminals and controls the main CPU to power on. Specifically, if the model information of CPU0 and CPU1 differs, the BMC controls the gating switch to disconnect via the XGMI_MUX_SEL signal (signal 1), applies a startup voltage to the MISC pin of CPU0 via the CPLD, and controls CPU0 via the eSPI signal, causing CPU0 to read the pre-stored CPU0 startup configuration information from memory via the SPI pin, thereby powering on CPU0. If the model information of CPU0 and CPU1 are the same, the BMC controls the gating switch to maintain the connection between the first and second terminals via the XGMI_MUX_SEL signal (signal 0). The power-on process is the same as in the prior art and will not be described further here.

[0056] In this embodiment, a gating switch is added to the existing dual-CPU architecture, and the gating terminal of the gating switch is connected to the BMC. The AMPL pin of CPU1 is connected to the corresponding pin of the BMC. That is, by adding a gating switch, two lines and corresponding control logic in the BMC to the existing architecture, the server can be started by CPU0, which is the main CPU, when the two CPU signals are different. The system architecture is simple and easy to implement.

[0057] like Figure 3 As shown, in some embodiments, the dual-CPU system of the AMD platform also includes: a CPU selection unit (such as...) Figure 3FPGA and pin configuration circuit.

[0058] The function pins of the first CPU (CPU0), namely USB, PCIe, SPI, MISC, and eSPI, are connected to the first input pin group of the CPU selection unit. The function pins of the second CPU (CPU1), namely USB, PCIe, SPI, MISC, and eSPI, are connected to the second input pin group of the CPU selection unit. The output pin group of the CPU selection unit is connected to the power-on control unit. The selection pin of the CPU selection unit is connected to the power-on control unit, and the marking pin configuration circuit is connected to the marking pins of the power-on control unit and the second CPU. Specifically, the CPU selection unit is a hardware circuit unit implemented by an FPGA. The first input pin group, the second input pin group, and the output pin group are all provided with pins corresponding to USB, PCIe, SPI, MISC, and eSPI. The selection pin of the CPU selection unit can be connected to the power-on control unit via I2C.

[0059] The power-on control unit is used to read the model information of the first CPU and the second CPU respectively via the AMPL signal, and control the gating switch when the model information of the two CPUs is the same. Figure 3 The first and second terminals of the xGMI MUX are kept connected, and a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group with the output pin group. This controls the marking pin configuration circuit to configure the marking pin of the second CPU as a secondary CPU and controls the main CPU to power on. Specifically, when CPU0 and CPU1 have the same model information, the first input pin group and output pin group corresponding to CPU0 are connected, while the second input pin group and output pin group corresponding to CPU1 are not connected, essentially left floating. The power-on control unit controls CPU0 to power on and start the server.

[0060] When the model information of CPU0 and CPU1 differs, the control switch disconnects the connection between the first and second terminals, identifies the target CPU, and sends a selection command to the selection pin of the CPU selection unit to connect the input pin group and output pin group corresponding to the target CPU, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is powered on. If the target CPU is the second CPU, the marking pin configuration circuit configures the marking pin of the second CPU, changing the second CPU from a secondary CPU to a master CPU, and the master CPU is powered on. Specifically, when the model information of CPU0 and CPU1 differs, the power-on control unit can display alarm information about the different models through the human-machine interface and prompt the user to select a CPU as the target CPU for power-on. After receiving the user's selected CPU, the target CPU can be determined, or the more powerful CPU can be determined automatically based on the model information of the two CPUs. By determining the more powerful CPU as the target CPU, the server has higher processing performance after powering on with the target CPU as the master CPU.

[0061] In some embodiments, such as Figure 3 As shown, the power-on control unit includes: a baseboard management controller ( Figure 3 BMC), CPLD, first memory ( Figure 3 BIOS Flash), Secondary Memory ( Figure 3 TF Card) and multiplexer Figure 3 (MUX).

[0062] The AMPL function pins of the first CPU and the second CPU are respectively connected to the corresponding pins of the substrate management controller. The USB, PCIe, and eSPI output pins of the CPU selection unit are connected to the corresponding pins of the substrate management controller. The MISC output pin of the CPU selection unit is connected to the CPLD. The CPLD is connected to the corresponding pin of the substrate management controller. The SPI output pin of the CPU selection unit is connected to the first selection terminal of the multiplexer. The second selection terminal of the multiplexer is connected to the corresponding pin of the substrate management controller. The third selection terminal of the multiplexer is connected to the first memory. The gating terminal of the multiplexer is connected to the substrate management controller. The selection pin of the CPU selection unit is connected to the substrate management controller. The tag pin configuration circuit is connected to the tag pins of the substrate management controller and the second CPU. The substrate management controller is connected to the second memory.

[0063] The first CPU is Figure 3 CPU0 is the first CPU, and the second CPU is the second CPU. Figure 3 The specific connection lines between CPU1, CPU0, CPU1, the baseboard management controller, the selection switch, the CPLD, the CPU selection unit, the first memory, the second memory, and the multiplexer are as follows: Figure 3 As shown.

[0064] The baseboard management controller is used to read the model information of the first CPU and the second CPU respectively through the AMPL signal. When the model information of the two CPUs is the same, it controls the first and second terminals of the gating switch to remain connected, sends a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, and controls the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU. The baseboard management controller is used to confirm that the power-on configuration information of the main CPU is written to the first memory from the second memory through the multiplexer, and then controls the main CPU to power on.

[0065] Specifically, when the BMC detects that the model information of CPU0 and CPU1 are the same, it controls the first and second terminals of the gating switch to remain connected through the XGMI_MUX_SEL signal (signal 0), and sends a selection command to the selection pin of the CPU selection unit through the I2C signal to connect the first input pin group with the output pin group. It controls the marking pin configuration circuit to configure the marking pin of CPU1 to configure CPU1 as a secondary CPU, that is, to connect SA[0] of CPU1 to a high level and SA[1] to a low level. The BMC is used to confirm that the boot configuration information of CPU0 is written to the BIOS Flash by TF_Card through MUX, and then controls CPU0 to boot up to start the server. Among them, the boot information of each CPU is pre-stored in TF_Card.

[0066] When the model information of the two CPUs differs, the baseboard management controller controls the gating switch to disconnect the connection between the first and second terminals, determines the target CPU, and sends a selection command to the selection pin of the CPU selection unit via an I2C signal to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. When the target CPU is the first CPU, the baseboard management controller confirms that the power-on configuration information of the master CPU has been written from the second memory to the first memory via the multiplexer, and then controls the master CPU to power on. When the target CPU is the second CPU, the controller controls the marking pin configuration circuit to configure the marking pin of the second CPU, changing the second CPU from a secondary CPU to a master CPU. The baseboard management controller confirms that the power-on configuration information of the master CPU has been written from the second memory to the first memory via the multiplexer, and then controls the master CPU to power on.

[0067] Specifically, when the BMC detects that CPU0 and CPU1 have different model information, it controls the gating switch to disconnect the connection between the first and second terminals via the XGMI_MUX_SEL signal (signal 1), determines the target CPU, and sends a selection command to the selection pin of the CPU selection unit via an I2C signal to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the main CPU. Specifically, the BMC can be configured as follows: when the determined target CPU is CPU0, the character '0' is sent to the selection pin of the CPU selection unit via I2C; when the determined target CPU is CPU1, the character '1' is sent to the selection pin of the CPU selection unit via I2C. When the CPU selection unit receives the character '0', it connects the first input pin group with the output pin group; when the CPU selection unit receives the character '1', it connects the second input pin group with the output pin group.

[0068] When the target CPU is CPU0, i.e., CPU0 is the main CPU, the BMC is used to confirm that the boot configuration information of the main CPU is written to the BIOS Flash by TF_Card through MUX, and then controls the main CPU to boot.

[0069] When the target CPU is CPU1, the marking pin configuration circuit is controlled to configure the marking pins of CPU1, so that CPU1 is changed from a secondary CPU to a primary CPU, that is, both SA[0] and SA[1] of CPU1 are connected to a low level. The BMC is used to confirm that the boot configuration information of the primary CPU is written to the BIOS Flash by TF_Card through MUX, and then controls the primary CPU to boot.

[0070] In this embodiment, the baseboard management controller sends a gating instruction to the gating terminal of the multiplexer to connect the second and third terminals of the multiplexer, thereby obtaining the current first power-on configuration information in the first memory. Based on the determined target CPU, it obtains the second power-on configuration information of the target CPU from the second memory. If the first and second power-on configuration information are the same, a gating instruction is sent to the gating terminal of the multiplexer to connect the first and third terminals of the multiplexer, allowing the main CPU to obtain the power-on configuration information in the first memory via the SPI signal and power on. If the first and second power-on configuration information are different, the second power-on configuration information is written into the first memory, and a gating instruction is sent to the gating terminal of the multiplexer to connect the first and third terminals of the multiplexer, allowing the main CPU to obtain the power-on configuration information in the first memory via the SPI signal and power on. Specifically, the BMC sends a strobe command to the SEL terminal of the MUX via the SPI_MUX_SEL signal (signal 1), connecting the second terminal CH1 and the third terminal SPI of the MUX, thus connecting the BIOS Flash and the BMC. The BMC obtains the current first boot configuration information from the BOIS_Flash via the BIOS_SPI signal, and obtains the second boot configuration information of the target CPU from the TF_Card according to the determined target CPU. If the first boot configuration information and the second boot configuration information are the same, the BMC sends a strobe command to the SEL terminal of the MUX via the SPI_MUX_SEL signal (signal 0) to connect the first terminal CH0 and the third terminal SPI of the MUX, so that the main CPU obtains the boot configuration information in the BIOS Flash via the SPI signal and boots up. When the first boot configuration information and the second boot configuration information are different, the BMC writes the second boot configuration information into the BIOS Flash through the BIOS_SPI signal, and then sends a strobe instruction to the strobe terminal SEL of the MUX through the SPI_MUX_SEL signal (signal 0) to connect the first terminal CH0 and the third terminal SPI of the MUX, so that the main CPU can obtain the boot configuration information in the BIOS Flash through the SPI signal and boot up.

[0071] Figure 3 In the process, regardless of whether the main CPU is CPU0 or CPU1, the boot process is the same: the BMC uses the CPLD_BMC_I2C signal to trigger the CPLD to apply the working voltage to the main CPU through MISC, and controls the main CPU through the eSPI signal, so that the main CPU reads the current boot configuration information from the BIOS Flash through the SPI pin, thereby realizing the boot of the main CPU.

[0072] like Figure 3As shown, the pin configuration circuit includes: a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, an inverter F, a first resistor R1, a second resistor R2, a first diode S1, and a second diode S2.

[0073] The gate of the first MOSFET M1 is connected to the substrate management controller, the source is connected to the cathode of the first diode S1, the anode of the first diode S1 is connected to the gate of the second MOSFET M2, and is connected to the high-level terminal through the first resistor R1. The drain of the first MOSFET M1 is grounded.

[0074] The source of the second MOS transistor M2 is connected to the high-level terminal, and the drain is connected to the marking pin SA[0] of the second CPU through the second resistor R2.

[0075] The input terminal of the inverter F is connected to the substrate management controller, the output terminal is connected to the gate of the third MOS transistor M3, the source of the third MOS transistor M3 is connected to the marker pin SA[0] of the second CPU, and the drain is grounded.

[0076] The anode of the second diode S2 is connected to the voltage monitoring pin GPIO of the second CPU, and the cathode is connected to the source of the first MOS transistor M1.

[0077] Specifically, the gate of the first MOS transistor M1 and the input of the inverter F are connected to the BMC via the CPU_SEL signal. When the BMC detects that CPU0 and CPU1 are of the same model, the BMC controls the marking pin configuration circuit to configure the marking pin of CPU1 to configure CPU1 as a secondary CPU. The specific configuration method is as follows: the BMC sets the CPU_SEL signal to a high level, so that the first MOS transistor M1 is turned on. The high level VDD_18 is grounded through R1, S1 and M1, so that the gate of M2 is at a high level and M2 is also turned on. At this time, due to the effect of the inverter F, the gate of M3 is at a low level and M3 is turned off. Therefore, the high level VDD_18 is loaded to the marking pin SA[0] of CPU1 through M2. The marking pin SA[1] of CPU1 is grounded by default, thereby configuring CPU1 as a secondary CPU.

[0078] If the BMC detects that CPU0 and CPU1 are different models, and the target CPU is CPU0, then because the MISC pin of CPU1 is floating, no startup voltage will be applied, and the strobe switch is also off, so CPU1 will not work, and instead CPU0 will power on. Therefore, the BMC does not need to set the CPU_SEL signal, meaning that no matter how the marking pin configuration circuit is configured, it will not affect the power-on of CPU0.

[0079] If the target CPU is CPU1, the BMC sets the CPU_SEL signal to low level, causing the first MOS transistor M1 to turn off. The high level VDD_18 cannot be grounded through R1, S1 and M1, so the gate of M2 is low level, and M2 is also turned off. The high level VDD_18 cannot be applied to the marking pin SA[0] of CPU1 through M2. At this time, due to the action of the inverter F, the gate of M3 is high level, M3 is turned on, and the marking pin SA[0] of CPU1 is directly grounded. The marking pin SA[1] of CPU1 is grounded by default, thus configuring CPU1 as the main CPU. Since the target CPU is CPU1, the MISC pin of CPU0 is floating and will not be loaded with the startup voltage. Moreover, the gating switch is also turned off, so CPU0 does not work. The setting of the marking pin of CPU0 does not affect the startup of CPU1.

[0080] The pin configuration circuit of this embodiment has a simple structure, low cost, and is easy to implement.

[0081] The boot method of the dual-CPU system on the AMD platform provided by the present invention is described below. The boot method of the dual-CPU system on the AMD platform described below can be referred to in correspondence with the dual-CPU system on the AMD platform described above.

[0082] like Figure 4 As shown, the boot method for a dual-CPU system on an AMD platform provided by this invention is based on... Figure 2 A dual-CPU system implementation on an AMD platform, wherein the method is applied to the power-on control unit, and the method includes:

[0083] Step S410: Obtain the model information of the first CPU and the second CPU respectively.

[0084] Step S420: Compare whether the model information of the first CPU is the same as that of the second CPU.

[0085] Step S430: If the model information of the first CPU is the same as that of the second CPU, control the gating switch to maintain the connection between the first CPU and the second CPU, and power on the computer with the first CPU as the main CPU.

[0086] Step S440: If the model information of the first CPU is different from that of the second CPU, control the gating switch to disconnect the connection between the first CPU and the second CPU, and power on the computer with the first CPU as the main CPU.

[0087] In the power-on method of the dual-CPU system on the AMD platform of the present invention, since a gating switch is set between the first CPU and the second CPU, when the power-on control unit detects that the model information of the first CPU and the model information of the second CPU are different, it controls the gating switch to disconnect the connection between the first CPU and the second CPU. The main CPU no longer interacts with the secondary CPU with a different model, but powers on and runs in the form of a single CPU, thereby avoiding the problem of the main CPU and the secondary CPU being unable to power on due to different models.

[0088] like Figure 5 As shown, the boot method for a dual-CPU system on an AMD platform provided by this invention is based on... Figure 3 A dual-CPU system implementation on an AMD platform, wherein the method is applied to the power-on control unit, and the method includes:

[0089] Step S510: Obtain the model information of the first CPU and the second CPU respectively.

[0090] Step S520: Compare whether the model information of the first CPU is the same as that of the second CPU.

[0091] Step S530: When the model information of the first CPU is the same as that of the second CPU, control the first and second ends of the selection switch to remain connected, send a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, control the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and control the main CPU to power on.

[0092] Step S540: If the model information of the first CPU is different from that of the second CPU, control the gating switch to disconnect the connection between the first and second ends, determine the target CPU, send a selection command to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, and make the target CPU the main CPU. If the target CPU is the first CPU, control the main CPU to power on; if the target CPU is the second CPU, control the marking pin configuration circuit to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a main CPU, and control the main CPU to power on.

[0093] In the boot method of the dual-CPU system on the AMD platform of the present invention, since a selection switch is set between the first CPU and the second CPU, when the boot control unit detects that the model information of the first CPU and the model information of the second CPU are different, it controls the selection switch to disconnect the connection between the first CPU and the second CPU. The main CPU no longer interacts with the secondary CPU of a different model, but boots up and runs in single-CPU mode, thereby avoiding the problem of boot failure due to different models of the main CPU and the secondary CPU. Moreover, by determining the target CPU, a higher-performance CPU can be selected as the main CPU, improving the operating performance of the server in single-CPU mode after boot.

[0094] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute a boot method for a dual-CPU system on an AMD platform, the method including:

[0095] Obtain the model information of the first CPU and the second CPU.

[0096] If the model information of the first CPU is the same as that of the second CPU, the control gating switch maintains the connection between the first CPU and the second CPU, and the first CPU is used as the master CPU for power-on.

[0097] If the model information of the first CPU is different from that of the second CPU, the control gating switch disconnects the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

[0098] Alternatively, the method includes:

[0099] Obtain the model information of the first CPU and the second CPU.

[0100] When the model information of the first CPU is the same as that of the second CPU, the first and second terminals of the selection switch are kept connected, a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and the main CPU is powered on.

[0101] If the model information of the first CPU is different from that of the second CPU, the gating switch is controlled to disconnect the connection between the first and second ends, and the target CPU is determined. A selection command is sent to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is controlled to power on. If the target CPU is the second CPU, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a master CPU, and the master CPU is controlled to power on.

[0102] The aforementioned electronic device can be the power-on control unit in the dual-CPU system embodiment of the AMD platform, specifically the BMC. Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute the boot method for a dual-CPU system on an AMD platform provided by the methods described above, the method comprising:

[0104] Obtain the model information of the first CPU and the second CPU.

[0105] If the model information of the first CPU is the same as that of the second CPU, the control gating switch maintains the connection between the first CPU and the second CPU, and the first CPU is used as the master CPU for power-on.

[0106] If the model information of the first CPU is different from that of the second CPU, the control gating switch disconnects the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

[0107] Alternatively, the method includes:

[0108] Obtain the model information of the first CPU and the second CPU.

[0109] When the model information of the first CPU is the same as that of the second CPU, the first and second terminals of the selection switch are kept connected, a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and the main CPU is powered on.

[0110] If the model information of the first CPU is different from that of the second CPU, the gating switch is controlled to disconnect the connection between the first and second ends, and the target CPU is determined. A selection command is sent to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is controlled to power on. If the target CPU is the second CPU, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a master CPU, and the master CPU is controlled to power on.

[0111] In another aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the boot method of the dual-CPU system of the AMD platform provided above, the method comprising:

[0112] Obtain the model information of the first CPU and the second CPU.

[0113] If the model information of the first CPU is the same as that of the second CPU, the control gating switch maintains the connection between the first CPU and the second CPU, and the first CPU is used as the master CPU for power-on.

[0114] If the model information of the first CPU is different from that of the second CPU, the control gating switch disconnects the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

[0115] Alternatively, the method includes:

[0116] Obtain the model information of the first CPU and the second CPU.

[0117] When the model information of the first CPU is the same as that of the second CPU, the first and second terminals of the selection switch are kept connected, a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and the main CPU is powered on.

[0118] If the model information of the first CPU is different from that of the second CPU, the gating switch is controlled to disconnect the connection between the first and second ends, and the target CPU is determined. A selection command is sent to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is controlled to power on. If the target CPU is the second CPU, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a master CPU, and the master CPU is controlled to power on.

[0119] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-CPU system for an AMD platform, characterized in that, include: First CPU, second CPU, power-on control unit, and selection switch; The first CPU's marker pin is configured as a main CPU connection, and the second CPU's marker pin is configured as a secondary CPU connection. The AMPL function pins of the first CPU and the second CPU are respectively connected to the power-on control unit. The main CPU's USB, PCIe, SPI, MISC, and eSPI function pins are respectively connected to the power-on control unit. The first end of the strobe switch is connected to the first CPU, the second end is connected to the second CPU, and the strobe end is connected to the power-on control unit. The power-on control unit is used to read the model information of the first CPU and the second CPU through the AMPL signal. If the model information of the two CPUs is different, it controls the gating switch to disconnect the connection between the first terminal and the second terminal and controls the main CPU to power on.

2. The dual-CPU system for the AMD platform according to claim 1, characterized in that, The power-on control unit includes: a baseboard management controller, a CPLD, and a memory; The AMPL functional pins of the first CPU and the second CPU are respectively connected to the corresponding pins of the baseboard management controller. The SPI functional pin of the main CPU is connected to the memory. The MISC functional pin of the main CPU is connected to the CPLD. The CPLD is connected to the corresponding pins of the baseboard management controller. The USB, PCIe and eSPI functional pins of the main CPU are respectively connected to the corresponding pins of the baseboard management controller. The selection terminal of the strobe switch is connected to the baseboard management controller. The baseboard management controller is used to read the model information of the first CPU and the second CPU through the AMPL signal. If the model information of the two CPUs is different, it controls the gating switch to disconnect the connection between the first terminal and the second terminal and controls the main CPU to power on.

3. The dual-CPU system for the AMD platform according to claim 1, characterized in that, It also includes: CPU selection unit and tag pin configuration circuit; The first CPU's functional pins USB, PCIe, SPI, MISC, and eSPI are connected to the first input pin group of the CPU selection unit. The second CPU's functional pins USB, PCIe, SPI, MISC, and eSPI are connected to the second input pin group of the CPU selection unit. The CPU selection unit's output pin group is connected to the power-on control unit. The CPU selection unit's selection pin is connected to the power-on control unit. The marking pin configuration circuit is connected to the marking pins of the power-on control unit and the second CPU. The power-on control unit is used to read the model information of the first CPU and the second CPU respectively through the AMPL signal. When the model information of the two CPUs is the same, it controls the first and second terminals of the selection switch to remain connected, sends a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, controls the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and controls the main CPU to power on. When the model information of the two CPUs is different, the control switch disconnects the connection between the first and second terminals, determines the target CPU, sends a selection command to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, and makes the target CPU the main CPU. If the target CPU is the first CPU, the control switch powers on the main CPU. If the target CPU is the second CPU, the control switch configures the marking pin of the second CPU to change the second CPU from a secondary CPU to a main CPU, and the control switch powers on the main CPU.

4. The dual-CPU system for the AMD platform according to claim 3, characterized in that, The power-on control unit includes: a baseboard management controller, a CPLD, a first memory, a second memory, and a multiplexer; The AMPL function pins of the first CPU and the second CPU are respectively connected to the corresponding pins of the baseboard management controller. The USB, PCIe, and eSPI output pins of the CPU selection unit are connected to the corresponding pins of the baseboard management controller. The MISC output pin of the CPU selection unit is connected to the CPLD. The CPLD is connected to the corresponding pin of the baseboard management controller. The SPI output pin of the CPU selection unit is connected to the first selection terminal of the multiplexer. The second selection terminal of the multiplexer is connected to the corresponding pin of the baseboard management controller. The third selection terminal of the multiplexer is connected to the first memory. The gating terminal of the multiplexer is connected to the baseboard management controller. The selection pin of the CPU selection unit is connected to the baseboard management controller. The tag pin configuration circuit is connected to the tag pins of the baseboard management controller and the second CPU. The baseboard management controller is connected to the second memory and is used to read the model information of the first CPU and the second CPU respectively through the AMPL signal. When the model information of the two CPUs is the same, it controls the first and second terminals of the gating switch to remain connected and sends a selection command to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group. It controls the marking pin configuration circuit to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU. The baseboard management controller is used to confirm that the power-on configuration information of the main CPU is written from the second memory to the first memory through the multiplexer and then controls the main CPU to power on. When the model information of the two CPUs is different, the control switch disconnects the connection between the first and second terminals, determines the target CPU, and sends a selection command to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the main CPU. When the target CPU is the first CPU, the baseboard management controller confirms that the power-on configuration information of the main CPU has been written from the second memory to the first memory through the multiplexer, and then controls the main CPU to power on. When the target CPU is the second CPU, the control pin configuration circuit configures the marking pin of the second CPU, changing the second CPU from a secondary CPU to a main CPU. The baseboard management controller confirms that the power-on configuration information of the main CPU has been written from the second memory to the first memory through the multiplexer, and then controls the main CPU to power on.

5. The dual-CPU system for the AMD platform according to claim 4, characterized in that, The baseboard management controller is used to send a selection command to the selection terminal of the multiplexer to connect the second and third terminals of the multiplexer to obtain the current first power-on configuration information in the first memory, and to obtain the second power-on configuration information of the target CPU from the second memory according to the determined target CPU. If the first power-on configuration information and the second power-on configuration information are the same, a selection command is sent to the selection terminal of the multiplexer to connect the first and third terminals of the multiplexer, so that the main CPU obtains the power-on configuration information in the first memory through the SPI signal and powers on. If the first power-on configuration information and the second power-on configuration information are different, the second power-on configuration information is written into the first memory, and a selection instruction is sent to the selection terminal of the multiplexer to connect the first terminal and the third terminal of the multiplexer, so that the main CPU obtains the power-on configuration information in the first memory through the SPI signal and powers on.

6. The dual-CPU system for the AMD platform according to claim 4, characterized in that, The pin configuration circuit includes: a first MOSFET, a second MOSFET, a third MOSFET, an inverter, a first resistor, a second resistor, a first diode, and a second diode; The gate of the first MOS transistor is connected to the substrate management controller, the source is connected to the cathode of the first diode, the anode of the first diode is connected to the gate of the second MOS transistor and connected to the high-level terminal through the first resistor, and the drain of the first MOS transistor is grounded. The source of the second MOS transistor is connected to the high-level terminal, and the drain is connected to the marking pin of the second CPU through the second resistor; The input terminal of the inverter is connected to the substrate management controller, the output terminal is connected to the gate of the third MOS transistor, the source of the third MOS transistor is connected to the marker pin of the second CPU, and the drain is grounded. The anode of the second diode is connected to the voltage monitoring pin of the second CPU, and the cathode is connected to the source of the first MOS transistor.

7. A boot method for a dual-CPU system on an AMD platform, characterized in that, Based on the dual-CPU system implementation of the AMD platform according to claim 1 or 2, the method is applied to the power-on control unit, and the method includes: Obtain the model information of the first CPU and the second CPU; If the model information of the first CPU is the same as that of the second CPU, the control gating switch maintains the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on. If the model information of the first CPU is different from that of the second CPU, the control gating switch disconnects the connection between the first CPU and the second CPU, and the first CPU is used as the main CPU for power-on.

8. A boot method for a dual-CPU system on an AMD platform, characterized in that, Based on a dual-CPU system implementation of the AMD platform according to any one of claims 3 to 6, the method is applied to the power-on control unit, and the method includes: Obtain the model information of the first CPU and the second CPU; When the model information of the first CPU is the same as that of the second CPU, the first and second terminals of the selection switch are kept connected, a selection command is sent to the selection pin of the CPU selection unit to connect the first input pin group and the output pin group, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU to configure the second CPU as a secondary CPU, and the main CPU is powered on. If the model information of the first CPU is different from that of the second CPU, the gating switch is controlled to disconnect the connection between the first and second ends, and the target CPU is determined. A selection command is sent to the selection pin of the CPU selection unit to connect the input pin group corresponding to the target CPU with the output pin group, making the target CPU the master CPU. If the target CPU is the first CPU, the master CPU is controlled to power on. If the target CPU is the second CPU, the marking pin configuration circuit is controlled to configure the marking pin of the second CPU, so that the second CPU changes from a secondary CPU to a master CPU, and the master CPU is controlled to power on.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the boot method for a dual-CPU system of the AMD platform as described in claim 7 or 8.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the boot method for a dual-CPU system on an AMD platform as described in claim 7 or 8.

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