A memory cell with integrated encryption function and its application

Abstract

This invention discloses a memory cell with integrated encryption functionality and its application. The memory cell includes a P-type tunneling field-effect transistor (TST) as a write transistor, an N-type tunneling field-effect transistor (NTT) as a read transistor, and a ferroelectric capacitor. The write transistor, read transistor, and ferroelectric capacitor are interconnected to form a memory node SN. The gate of the write transistor is connected to the write word line, the drain to the write bit line, and the source to SN. The gate of the read transistor is connected to SN, the drain to the read bit line, and the source to ground. One end of the ferroelectric capacitor is connected to SN, and the other end is connected to the read word line. SN stores plaintext information, and the ferroelectric capacitor stores key information. The ferroelectric capacitor has two polarization states, corresponding to two different capacitance values, which can achieve different voltage divisions during memory cell readout, thereby realizing encryption and decryption functions between plaintext and key information. This invention increases the security of the storage circuit, reduces hardware costs, and increases the storage window and array size.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a memory cell with integrated encryption function and its application. Background Technology

[0002] With the rapid development of AIoT, the importance of hardware security has increased, leading to a greater demand for low-cost, high-security chips among the numerous IoT edge and node chips. Establishing a chip trust root requires three circuit components: key generation, encryption, and storage. Typically, these three circuit components are independent, resulting in significant hardware costs and creating a design trade-off between hardware security and cost for IoT edge and node chips. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a memory unit with integrated encryption function and its application. The memory unit of this invention can perform data encryption in the storage circuit, which improves the security of stored information while reducing hardware costs.

[0004] The technical solution of this invention is as follows:

[0005] A memory cell with integrated encryption function includes a P-type tunneling field-effect transistor as a write transistor, an N-type tunneling field-effect transistor as a read transistor, and a ferroelectric capacitor. The write transistor, read transistor, and ferroelectric capacitor are interconnected to form a memory node SN. The source electrode of the write transistor is connected to the memory node SN, the gate electrode is connected to the write word line WWL, and the drain electrode is connected to the write bit line WBL. The gate electrode of the read transistor is connected to the memory node SN, the drain electrode is connected to the read bit line RBL, and the source electrode is connected to 0V. One end of the ferroelectric capacitor is connected to the memory node SN, and the other end is connected to the read word line RWL.

[0006] The ferroelectric capacitor has two polarization states: polarization upward and polarization downward. It maintains both polarization states even without an applied voltage. Therefore, the memory unit has two storage components: a storage node SN for storing plaintext information and a ferroelectric capacitor for storing key information. The two polarization states of the ferroelectric capacitor correspond to two different capacitance values, enabling different voltage divisions during memory unit readout, thus achieving encryption and decryption between plaintext and key information.

[0007] The P / N type tunneling field-effect transistor has a source terminal including a source metal layer and a source semiconductor layer that wraps the source metal layer. The source terminal of the tunneling field-effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has bidirectional conduction characteristics. Its drain terminal is a certain distance from the gate boundary, which can suppress the bipolar current of the tunneling field-effect transistor and reduce the device off-state current.

[0008] Furthermore, the peak doping concentration of the source semiconductor layer of the P / N tunneling field-effect transistor is 1e20cm⁻¹. -3 and above,

[0009] The width of the source semiconductor layer is 5 nm or more wider than the width of the source metal layer in the horizontal direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than the thickness of the source metal layer in the vertical direction.

[0010] Furthermore, the drain of the P / N tunneling field-effect transistor is 10 nm to 100 nm away from the gate.

[0011] This invention proposes an operation method for the aforementioned memory cell, comprising five steps: writing 1 to the ferroelectric capacitor, writing 0 to the ferroelectric capacitor, writing 1 to the storage node SN, writing 0 to the storage node SN, and encrypting and reading the stored information, as detailed below:

[0012] In the hold state, i.e., when there are no write 1, write 0, or read operations, the voltages of the write word line WWL, write bit line WBL, read word line RWL, and read bit line RBL in the memory cell are all 0V; if the information stored in the memory node SN is "0", then the voltage of the memory node SN is 0V; if the information stored in the memory node SN is "1", then the voltage of the memory node SN is V0; if the information stored in the ferroelectric capacitor is "0", then the polarization direction of the ferroelectric capacitor is from RWL to SN; if the information stored in the ferroelectric capacitor is "1", then the polarization direction of the ferroelectric capacitor is from SN to RWL.

[0013] The steps for writing 1 to a ferroelectric capacitor are as follows: apply voltage V1 to the write word line WWL, apply voltage V2 to the write bit line WBL, and keep the voltages of the read word line RWL and read bit line RBL unchanged; at this time, the write transistor is turned on, and the voltage V2 is transmitted from the write bit line WBL to the storage node SN, and the polarization direction of the ferroelectric capacitor is reversed to point from SN to RWL; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL are both restored to 0V;

[0014] The steps for writing 0 to a ferroelectric capacitor are as follows: apply voltage V1 to the write word line WWL, apply voltage 0V to the write bit line WBL, apply voltage V2 to the read word line RWL, and keep the voltage of the read bit line RBL unchanged; at this time, the write transistor is turned on, and the voltage 0V is transmitted from the write bit line WBL to the storage node SN, and the polarization direction of the ferroelectric capacitor is reversed to point from RWL to SN; after the writing is completed, the voltages of both the write word line WWL and the read word line RWL return to 0V;

[0015] The steps for writing 0 to the storage node SN are as follows: apply voltage V1 to the write word line WWL, apply voltage 0V to the write bit line WBL, and keep the voltages of the read word line RWL and the read bit line RBL unchanged; at this time, the write transistor is turned on, and the voltage 0V is transmitted from the write bit line WBL to the storage node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL are both restored to 0V.

[0016] The steps for writing 1 to the storage node SN are as follows: apply voltage V1 to the write word line WWL, apply voltage V0 to the write bit line WBL, and keep the voltages of the read word line RWL and the read bit line RBL unchanged; at this time, the write transistor is turned on, and the voltage V0 is transmitted from the write bit line WBL to the storage node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL are both restored to 0V.

[0017] The steps for encrypting and reading the memory cell are as follows: After pre-charging the read bit line RBL to voltage V2, the read bit line RBL is placed in a floating state. Voltage V2 is applied to the write word line WWL and the read word line RWL, while the write bit line WBL voltage remains unchanged. At this time, if the information stored in the storage node SN and the ferroelectric capacitor is both 0, the read transistor current is small, the read bit line RBL voltage is V3, and the output voltage after inputting to the tri-state comparator circuit is V2, i.e., the ciphertext information is 1. If the information stored in the storage node SN and the ferroelectric capacitor is both 1, the read transistor current is large, the read bit line RBL voltage drops to V4, and the tri-state comparator circuit is input. After the comparator circuit outputs V2, the encrypted information is 1. If the information stored in the storage node SN is "0" and the information stored in the ferroelectric capacitor is "1", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to V5, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. If the information stored in the storage node SN is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to V6, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. After reading, the voltages of the write word line WWL, the read word line RWL, and the read bit line RBL all return to 0V. Before and after the read operation, the voltage and ferroelectric polarization of the storage node SN remain unchanged.

[0018] Furthermore, in the encryption reading step, the ferroelectric capacitor stores the key information Key, and the storage node SN stores the plaintext information Wi. After the information read from the memory unit is input into the tri-state comparison circuit, the output information Xe is obtained. The whole process is equivalent to performing an XOR operation on the key information Key and the plaintext information Wi, that is, Xe = Key + ○Wi. The output information Xe is the encrypted ciphertext information after encryption.

[0019] The present invention also proposes a memory array with encryption function composed of the memory cells, wherein the memory cells are arranged in a matrix structure by repeating them horizontally and vertically. The memory cells in the same row share a write word line WWL and a read word line RWL, and the memory cells in the same column share a write bit line WBL and a read bit line RBL.

[0020] This invention proposes a corresponding operation method for the memory array. The method is characterized by the following steps when controlling the memory cells in the array: writing keys column-wise, writing plaintext row-wise, and reading ciphertext row-wise. For writing information to ferroelectric capacitors, first write 1 to all memory cells in the selected column, then write 0 to the required memory cells in that column to complete the key writing operation. For writing information to a storage node SN, information can be written to all memory cells in a row simultaneously to complete the plaintext writing operation. For encrypted reading, ciphertext information in all cells of the selected row can be read simultaneously.

[0021] The operation method of the memory array includes three parts: writing the key, writing the plaintext, and reading the ciphertext. For each memory cell, the order of these three operations is: first write the key, then write the plaintext, and then read the ciphertext.

[0022] Furthermore, the operation method of the memory array is as follows:

[0023] (1) The specific method for writing the key is as follows:

[0024] First, write a 1 to the ferroelectric capacitor of the memory cell with key 1 in the selected column. Specifically, apply voltage V1 to all write word lines WWL, apply voltage V2 to the corresponding write bit line WBL, and keep the voltage of the other write bit lines at 0V. The voltage of the read word line RWL corresponding to the memory cell with key 1 is 0V, the voltage of the read word line RWL corresponding to the memory cell with key 0 is V2, and the voltage of all read bit lines RBL remains unchanged. At this time, the write transistors of all cells in the array are turned on, and the voltage across the ferroelectric capacitor of the memory cell with key 1 in the selected column is V2, which exceeds the coercivity voltage V of the ferroelectric capacitor. C The polarization direction of the ferroelectric capacitor is reversed from SN to RWL. The voltage across the ferroelectric capacitors of the remaining memory cells in the array is 0V, and the ferroelectric polarization does not reverse. After writing is complete, all WWL, WBL and RWL voltages return to 0V.

[0025] Next, write 0 to the ferroelectric capacitor of the memory cell with key 0 in the selected column. Specifically, apply voltage V1 to the write word line WWL of the corresponding cell, apply voltage 0V to WBL of the selected column, and simultaneously apply voltage V2 to the remaining WBLs and all RWLs, while keeping the voltage of the read bit line RBL unchanged. At this time, the write transistors of the corresponding memory cell and other cells in the same row are turned on. The voltage across the ferroelectric capacitor of the corresponding memory cell in the selected column is V2, and the polarization direction of the ferroelectric capacitor is reversed from RWL to SN. The voltage across the ferroelectric capacitors of other cells in the same row is 0V, and the ferroelectric polarization does not reverse. The write transistors of the memory cells in the remaining rows of the selected column are turned off, because the write... The low off-state current and small gate-source capacitance of the transistor result in a small coupling voltage between the SN node and WWL. The voltage of the SN node discharges slowly through the off-state current of the write transistor, so the RWL voltage is almost entirely coupled to the SN node, and the voltage across the ferroelectric capacitor is approximately 0V, with no ferroelectric polarization switching. For the remaining memory cells in the other rows and columns, the write transistor is off, and the WBL voltage is transmitted to the memory node SN through the forward bias PIN current of the write transistor. Since the remaining WBLs and all RWLs are simultaneously subjected to voltage V2, the voltage across the ferroelectric capacitor is 0V, and no ferroelectric polarization switching occurs. After the write operation is complete, all WWL voltages, WBL voltages, and RWL voltages return to 0V.

[0026] By repeating the above operation on other columns in the memory array, key information can be written to all cells in the array.

[0027] (2) The specific method for writing plaintext is as follows:

[0028] Plaintext information is written to the memory cells of the selected row. Specifically, a voltage V1 is applied to the WWL of the selected row, a voltage of 0V is applied to the write bit line WBL corresponding to the cell with plaintext 0, and a voltage V0 is applied to the write bit line WBL corresponding to the cell with plaintext 1. The voltages of the read word line RWL and the read bit line RBL remain unchanged. At this time, the write transistor of the selected row is turned on, and the voltage is transferred from the write bit line WBL to the memory node SN. After the writing is completed, all WWL and WBL voltages return to 0V. Since V0 is less than the coercive voltage V of the ferroelectric capacitor... C During the writing of plaintext information, the ferroelectric capacitor does not flip, and the key information is not destroyed.

[0029] By repeating the above operation on other rows in the memory array, plaintext information can be written to all cells in the array.

[0030] (3) The method for reading ciphertext is as follows:

[0031] The encrypted information of the selected row's memory cell is read. Specifically, after pre-charging all read bit lines RBL to V2, the read bit lines RBL are placed in a floating state. V2 is applied to the write word line WWL of the selected row, and V2 is applied to the read word line RWL of the selected row, while the write bit line WBL voltage remains unchanged. At this time, if the information stored in the memory node SN and the ferroelectric capacitor is both 0, the read transistor current is small, the read bit line RBL voltage is V3, and the output voltage after inputting into the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in the memory node SN and the ferroelectric capacitor is both 1, the read transistor current is large, the read bit line RBL voltage drops to V4, and the output voltage after inputting into the tri-state comparator circuit is V2. The output voltage is V2, meaning the encrypted information is 1. If the information stored in the storage node SN is "0" and the information stored in the ferroelectric capacitor is "1", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to V5, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. If the information stored in the storage node SN is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to V6, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. After reading, the voltages of the write word line WWL, the read word line RWL, and the read bit line RBL all return to 0V. Before and after the read operation, the voltage and ferroelectric polarization of the storage node SN remain unchanged.

[0032] Furthermore, the voltage V0 is between 0V and 2V, approximately equal to the turn-on voltage of the readout tube; the voltage V1 is between 0V and -5V; the voltage V2 is between 0V and 5V; the voltage V3 is between 0V and V2; the voltages V5 and V6 are between 0V and V3; the voltage V4 is a positive number less than V5 and V6; and V5 and V6 are approximately equal.

[0033] This invention discloses a memory cell with integrated encryption function and its application. The proposed memory cell with integrated encryption function and its array circuit have encrypted read function, which increases the security of the storage circuit while reducing the hardware cost; it can enhance the ability to resist row hammer attacks and improve the security of the storage circuit; it can extend the memory retention time, reduce the refresh frequency and refresh power consumption; it can reduce the leakage current of the read bit line, alleviate the read crosstalk problem, and increase the storage window and array size. Attached Figure Description

[0034] Figure 1 This is a schematic equivalent circuit diagram of the memory cell proposed in this invention;

[0035] In the diagram: 1 – Write tube; 2 – Read tube; 3 – Amplification unit;

[0036] Figure 2A schematic diagram of the tunneling field-effect transistor that constitutes the memory cell proposed in this invention;

[0037] In the diagram: 04 – Gate; 05 – Source metal layer; 06 – Source semiconductor layer; 07 – Drain.

[0038] 08—Substrate;

[0039] Figure 3 This is a cross-sectional view of the memory cell in a specific embodiment of the present invention during actual integrated circuit fabrication;

[0040] Figure 4 This is a schematic equivalent circuit diagram of a memory array in a specific embodiment of the present invention;

[0041] In the picture:

[0042] 4—High-resistivity silicon substrate;

[0043] 5 – Shallow trench isolation; 6 – Upper isolation trap;

[0044] 7—Lower isolation trap; 8—Gate dielectric layer;

[0045] 9—Gate conductive layer of N-type device; 10—Gate conductive layer of P-type device;

[0046] 11—Compensation isolation layer; 12—Composite main isolation layer;

[0047] 13 – N+SD area; 14 – P+SD area;

[0048] 15—N+ extended region; 16—P+ extended region;

[0049] 17—Self-aligned silicide; 18—Inter-hole dielectric layer;

[0050] 19 – Contact hole; 20 – WBL metal interconnect;

[0051] 21—WWL metal interconnect; 22—SN metal interconnect;

[0052] 23—RBL metal interconnect; 24—GND metal interconnect;

[0053] 25—Intermetallic dielectric layer; 26—Lower electrode of capacitor;

[0054] 27—Ferroelectric layer; 28—Upper plate of capacitor;

[0055] 29 – Metal interconnect via; 30 – RWL metal interconnect. Detailed Implementation

[0056] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0057] Figure 1 This is a schematic equivalent circuit diagram of the memory cell proposed in this invention. The diagram shows the connection relationships between the various parts of the proposed memory cell. Write transistor 1 is a P-type tunneling field-effect transistor. The gate electrode of write transistor 1 is connected to the write word line WWL, the drain electrode of write transistor 1 is connected to the write bit line WBL, and the source electrode of write transistor 1 is connected to the memory node SN. Read transistor 2 is an N-type tunneling field-effect transistor. The gate electrode of read transistor 2 is connected to the memory node SN, the drain electrode of read transistor 2 is connected to the read bit line RBL, and the source electrode of read transistor 2 is connected to 0V. 3 is a ferroelectric capacitor, with one end connected to the memory node SN and the other end connected to the memory node RWL. Figure 1 The tunneling field-effect transistor (TFET) in the memory should meet the following conditions: The P-type TFET used as the write transistor needs to suppress bipolar current and its off-state current should be lower than the off-state current of a silicon-based CMOS device at the same process node. It also needs to have bidirectional conduction characteristics within the required read / write voltage range. The N-type TFET used as the read transistor needs to suppress bipolar current and its off-state current should be lower than the off-state current of a silicon-based CMOS device at the same process node. It also needs to have a large turn-on voltage such that the turn-on voltage is approximately equal to the memory node voltage V corresponding to "1". SN Given that existing tunneling field-effect transistors (TFETs) fail to meet the above requirements, this invention provides a specific structural description of a TFET that satisfies these requirements. Figure 2 The device structure that conforms to the description is shown. Figure 2 The source terminal of the tunneling field-effect transistor shown consists of a source metal layer 05 and a source semiconductor layer 06 enclosing the source metal layer 05, and the doping concentration of the source semiconductor layer 06 is as high as 1e20cm. -3The source semiconductor layer 06 is 10 nm wider than the source metal layer 05 laterally, and its thickness is 10 nm thicker than the source metal layer 05 vertically, thus preventing complete depletion of the source semiconductor layer 06. The boundary between the source metal layer 05 and the source semiconductor layer 06 is located near the boundary of the gate 04 of the tunneling field-effect transistor (TFPT), making the source terminal of the TFPT physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, achieving bidirectional conduction characteristics. The turn-on voltage can be adjusted by changing the distance between the boundary of 04 and the boundaries between 05 and 06. The drain terminal 07 of the TFPT is spaced a distance from the gate 04, achieving the characteristic of suppressing bipolar current and having a lower off-state current than silicon-based CMOS devices at the same process node.

[0058] Figure 3 Showing Figure 1 The figure shows a cross-sectional view of a memory cell in actual integrated circuit fabrication. It illustrates one possible tunneling field-effect transistor (TFPT) structure; however, based on existing techniques and the memory structure design requirements proposed in this invention, the TFPT can be replaced with other structures. Figure 3The tunneling field-effect transistor shown is a planar device structure fabricated on a high-resistivity silicon substrate 4, with devices isolated from each other by shallow trench isolation 5. The gate dielectric layer 8 and gate conductive layers 9 and 10 form the gate region of the device. Only one side of the gate sidewall with the compensation isolation layer 11 corresponds to the source terminal, while the other side with the compensation isolation layer 11 and the composite main isolation layer 12 corresponds to the drain terminal. The self-aligned silicide 17, SD regions 13 and 14, and extended regions 15 and 16 form the source and drain terminals of the device. Each device's substrate region includes an upper isolation well 6 and a lower isolation well 7, used to isolate leakage current between source and drain regions of the same doping type between adjacent devices through the substrate. The source, gate, and drain electrodes of the device are led out through contact holes 19 and metal interconnects 20, 21, 22, 23, and 24, respectively. The device on the left is a P-type tunneling field-effect transistor, a write transistor. The gate conductive layer 10 of the P-type device is the gate conductive layer of this device, led out through WWL metal interconnects. The N+SD region 13, N+ extended region 15, and self-aligned silicide 17 form the source terminal of the write transistor, which is connected to the gate electrode and one end of the ferroelectric capacitor of the read transistor via the SN metal interconnect 22. The P+SD region 14, P+ extended region 16, and self-aligned silicide 17 form the drain terminal of the write transistor, which is led out via the WBL metal interconnect 20. The device on the right is an N-type tunneling field-effect transistor, which is the read transistor. The gate conductive layer 9 of the N-type device is the gate conductive layer of this device, which is connected to the source electrode and one end of the ferroelectric capacitor of the write transistor via the SN metal interconnect. The N+SD region 13, N+ extended region 15, and self-aligned silicide 17 form the drain terminal of the read transistor, which is led out via the RBL metal interconnect 23. The P+SD region 14, P+ extended region 16, and self-aligned silicide 17 form the source terminal of the read transistor, which is led out via the GND metal interconnect 24. The ferroelectric capacitor 3 consists of a lower electrode 26, a ferroelectric layer 27, and an upper electrode 28. It is located between the metal interconnects of adjacent layers and will not affect the back-end interconnect parameters and performance of the CMOS device.

[0059] By arranging the proposed memory cells in a regular, repetitive manner, a schematic equivalent circuit diagram of the memory array structure proposed in this invention can be obtained, such as... Figure 4 As shown. Memory cells in the same row share a single write word line WWL, from WWL0 to WWL. m A total of m+1 rows of write word lines WWL are used. Memory cells in the same row share a single read word line RWL, from RWL0 to RWL... m There are a total of m+1 read word lines RWL. Memory cells in the same column share a single write bit line WBL, from WBL0 to WBL... n A total of n+1 columns are written to the bit line WBL. Memory cells in the same column share a single read bit line RBL, from RBL0 to RBL... n A total of n+1 columns are written to the bit line RBL.

[0060] for Figure 4 The array structure shown allows for key writing, plaintext writing, and encrypted readout of selected memory cells using the proposed control method. First, information is written to all cells in the memory array, starting with the first column. The ferroelectric capacitor of the memory cell with a key of 1 in that column is written with a value of 1. Specifically, a voltage of -2.5V is applied to all write word lines WWL, a voltage of 2.5V is applied to the write bit line WBL0, and the voltages of the remaining write bit lines are 0V. The read word line RWL corresponding to the memory cell with a key of 1 has a voltage of 0V, and the read word line RWL corresponding to the memory cell with a key of 0 has a voltage of 2.5V. The voltages of all read bit lines RBL remain unchanged. At this time, the write transistors of all cells in the array are turned on, and the voltage across the ferroelectric capacitor of the memory cell with a key of 1 in the first column is 2.5V, exceeding its coercive voltage V. C =1V, the polarization direction of the ferroelectric capacitor reverses from SN to RWL. The voltage across the ferroelectric capacitors of the remaining memory cells in the array is 0V, and the ferroelectric polarization does not reverse. After the write operation is complete, all WWL, WBL, and RWL voltages return to 0V.

[0061] Next, write 0 to the ferroelectric capacitor of the cell with key 0 in the first column. Specifically, apply a voltage of -2.5V to the write word line WWL of the corresponding cell, apply a voltage of 0V to WBL0, and apply a voltage of 2.5V to the remaining WBLs and all RWLs simultaneously, while keeping the voltage of the read bit line RBL unchanged. At this time, the write transistors of the corresponding memory cell and other cells in the same row are turned on. The voltage across the ferroelectric capacitor of the corresponding memory cell in the first column is 2.5V, and the polarization direction of the ferroelectric capacitor flips from RWL to SN. The voltage across the ferroelectric capacitors of other cells in the same row is 0V, and the ferroelectric polarization does not flip. The write transistors of the memory cells in the remaining rows of the first column are turned off. Due to the low off-state current and small gate-source capacitance of the write transistor, the coupling voltage between the SN node and WWL is small. The voltage of the SN node discharges slowly through the off-state current of the write transistor, so the RWL voltage is almost entirely coupled to the SN node, and the voltage across the ferroelectric capacitor is approximately 0V, with the ferroelectric polarization not flipping. For the remaining memory cells in the remaining rows and columns, the write transistor is off, and the WBL voltage is transmitted to the memory node SN through the forward bias pin current of the write transistor. Since the remaining WBLs and all RWLs are simultaneously subjected to a voltage of 2.5V, the voltage across the ferroelectric capacitors is 0V, and the ferroelectric polarization does not flip. After the write operation is complete, all WWL voltages, WBL voltages, and RWL voltages return to 0V.

[0062] Next, repeat the above operation to write key information to all cells in the array.

[0063] Next, plaintext information is written to the first row of memory cells. Specifically, a voltage of -2.5V is applied to the write word line WWL0, a voltage of 0V is applied to the write bit line WBL corresponding to the cell with plaintext 0, and a voltage of 0.5V is applied to the write bit line WBL corresponding to the cell with plaintext 1. The voltages of the read word line RWL and the read bit line RBL remain unchanged. At this time, the write transistor of the first row is turned on, transmitting voltage from the write bit line WBL to the memory node SN. After the writing is completed, the voltages of the write word line WWL0 and all write bit lines WBL return to 0V.

[0064] Next, repeat the above operation to write plaintext information to all cells in the array.

[0065] Next, the encrypted information of a specific memory cell is read. Specifically, all read bit lines RBL are pre-charged to 2.5V and then floated. 2.5V is applied to the write word line WWL and the read word line RWL of the selected row, while the write bit line WBL voltage remains constant. At this point, if the information stored in the memory node SN and the ferroelectric capacitor is both 0, the read transistor current is small, the read bit line RBL voltage is 2.1V, and after input to the tri-state comparator circuit, the output is 2.5V, indicating the encrypted information is 1. If the information stored in the memory node SN and the ferroelectric capacitor is both 1, the read transistor current is large, the read bit line RBL voltage drops to 1.1V, and after input to the tri-state comparator circuit, the output is 2.5V, indicating the encrypted information is 1. If the information stored in the memory node SN is "0" and the information stored in the ferroelectric capacitor is "1", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to 1.61V, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. If the information stored in the memory node SN is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is moderate, the voltage of the read bit line RBL drops to 1.59V, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. After the read operation is complete, the voltages of the write word line WWL, the read word line RWL, and the read bit line RBL all return to 0V. Before and after the read operation, the voltage and ferroelectric polarization of the memory node SN remain unchanged.

[0066] Next, repeat the above operation to read the ciphertext information of all cells in the array.

[0067] In summary, the memory cell and its array circuit with integrated encryption function proposed in this invention have encrypted readout capabilities, increasing the security of the storage circuit while reducing hardware costs. The memory array circuit of this invention enhances resistance to row hammer attacks and improves the security of the storage circuit: for memory cells without selected rows, their write transistors are in the off state; due to the low off-state current and small gate-source capacitance of the write transistors, the coupling voltage between the SN node and WWL is small, and the SN node voltage discharges slowly through the off-state current of the write transistors. Therefore, the RWL voltage is almost entirely coupled to the SN node, the voltage across the ferroelectric capacitor is approximately 0V, the ferroelectric polarization does not reverse, and the SN node voltage remains unchanged before and after the RWL voltage is applied; therefore, it is difficult to change the stored information by continuously applying voltage to the RWL. The memory circuit of this invention effectively resists row hammer attacks. The invention's memory array circuit can also extend the memory's hold time and reduce refresh frequency and power consumption. Unlike the symmetrical gate capacitance of MOSFET devices, tunneling field-effect transistors (TFETs) have asymmetrical gate capacitance, with their gate-source capacitance being much smaller than their gate-drain capacitance. Connecting the source electrode of the TFET to the memory node SN, the smaller gate-source capacitance of the TFET results in a smaller coupling voltage between the write word line WWL and the memory node SN. This voltage is less than the coupling voltage between WWL and SN caused by a MOSFET device with the same process node and gate area as the write transistor. Therefore, using a TFET as the write transistor will not degrade the memory's write speed and hold time due to the coupling voltage between WWL and SN. Furthermore, when the TFET is in the off state, the tunneling window is closed, resulting in a low off-state current. Silicon-based tunneling field-effect transistors have been experimentally proven to have lower off-state current than silicon-based CMOS devices at the same process node. In the memory cell of this invention, in the hold state, only the leakage path from the memory node SN to the write bit line WBL causes the SN node voltage to drop. Using a tunneling field-effect transistor (TFET) as the write transistor, the low off-state current advantage of TFET results in a lower leakage current from SN to WBL, thus achieving a longer hold time than when using a MOSFET as the write transistor, thereby reducing the refresh frequency and refresh power consumption.The memory array circuit of this invention can also reduce read bit line leakage, alleviate read crosstalk problems, and increase the storage window and array size. If the read transistor is a MOSFET, due to the low threshold voltage of MOSFETs, when the information stored in the memory cell is "1", the corresponding read transistor is in the hold state. Regardless of whether the cell is selected or not, the corresponding read transistor will charge and discharge the read bit line RBL, thus deteriorating the read speed and storage window. Furthermore, the more cells in the same column of unselected cells that store information "1", the more severe the negative impact. In the memory cell of this invention, in the hold state, if the memory cell stores information "1", the gate voltage of the read transistor is V0, which is approximately equal to the voltage of the read transistor. The gate voltage of the read transistor is 0V, meaning the read transistor is not turned on. If the information stored in the memory cell is "0", the gate voltage of the read transistor is 0V, and the read transistor is not turned on. To read the stored information of a memory cell, a voltage V2 is applied to RWL. Through the capacitive coupling voltage of the ferroelectric capacitor, the SN voltage is raised, thereby turning on the read transistor and discharging RBL. At this time, for the unselected memory cells in the same column, their read transistors are not turned on and will not charge or discharge RBL. Therefore, the memory structure and control method of the present invention can reduce read bit line leakage. Only the read transistor of the selected cell in the same column discharges RBL, thereby alleviating read crosstalk problems and increasing the storage window and array size.

[0068] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A memory unit with integrated encryption function, characterized in that, Includes a P-type tunneling field-effect transistor as The system consists of a write transistor, an N-type tunneling field-effect transistor as a read transistor, and a ferroelectric capacitor. The write transistor, read transistor, and ferroelectric capacitor are interconnected to form a memory node SN. The source electrode of the write transistor is connected to the memory node SN, the gate electrode is connected to the write word line WWL, and the drain electrode is connected to the write bit line WBL. The gate electrode of the read transistor is connected to the memory node SN, the drain electrode is connected to the read bit line RBL, and the source electrode is connected to 0V. One end of the ferroelectric capacitor is connected to the memory node SN, and the other end is connected to the read word line RWL. The ferroelectric capacitor has two polarization states: polarization upward and polarization downward. It maintains both polarization states even without an applied voltage. Therefore, the memory unit has two storage components: a storage node SN for storing plaintext information and a ferroelectric capacitor for storing key information. The two polarization states of the ferroelectric capacitor correspond to two different capacitance values, enabling different voltage divisions during memory unit readout, thus achieving encryption and decryption between plaintext and key information. The P-type tunneling field-effect transistor and the N-type tunneling field-effect transistor have a source terminal including a source metal layer and a source semiconductor layer enclosing the source metal layer. The source terminal of the tunneling field-effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has bidirectional conduction characteristics. The drain terminal is at a certain distance from the gate boundary, which is between 10nm and 100nm, which can suppress the bipolar current of the tunneling field-effect transistor and reduce the device off-state current.

2. A memory unit with integrated encryption function as described in claim 1, characterized in that, The P-type tunnel The peak doping concentration of the source semiconductor layer of the field-effect transistor and the N-type tunneling field-effect transistor is 1e20cm. -3 The width of the source semiconductor layer is 5 nm or more wider than the width of the source metal layer in the horizontal direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than the thickness of the source metal layer in the vertical direction.

3. A method for controlling the operation of a memory cell as described in claim 1, characterized in that, The process includes five steps: writing 1 to a ferroelectric capacitor, writing 0 to a ferroelectric capacitor, writing 1 to the storage node's serial number (SN), writing 0 to the storage node's SN, and encrypting and reading the stored information. The details are as follows: In the hold state, i.e., when there are no write 1, write 0, or read operations, the voltages of the write word line WWL, write bit line WBL, read word line RWL, and read bit line RBL in the memory cell are all 0V; if the information stored in the memory node SN is "0", then the voltage of the memory node SN is 0V; if the information stored in the memory node SN is "1", then the voltage of the memory node SN is V0; if the information stored in the ferroelectric capacitor is "0", then the polarization direction of the ferroelectric capacitor is from RWL to SN; if the information stored in the ferroelectric capacitor is "1", then the polarization direction of the ferroelectric capacitor is from SN to RWL. The steps for writing 1 to a ferroelectric capacitor are as follows: apply voltage V1 to the write word line WWL, apply voltage V2 to the write bit line WBL, and keep the voltages of the read word line RWL and the read bit line RBL unchanged. At this time, the write transistor is turned on, transmitting voltage V2 from the write bit line WBL to the storage node SN, and the polarization direction of the ferroelectric capacitor is reversed from SN to RWL; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL are both restored to 0V. The steps for writing 0 to a ferroelectric capacitor are as follows: apply voltage V1 to the write word line WWL, apply voltage 0V to the write bit line WBL, apply voltage V2 to the read word line RWL, and keep the voltage of the read bit line RBL unchanged. At this time, the write transistor is turned on, transmitting the voltage 0V from the write bit line WBL to the storage node SN, and the polarization direction of the ferroelectric capacitor is reversed from RWL to SN. After writing is complete, the voltages of both the write word line WWL and the read word line RWL return to 0V. The steps for writing 0 to the storage node SN are as follows: apply voltage V1 to the write word line WWL, apply voltage 0V to the write bit line WBL, and keep the voltages of the read word line RWL and the read bit line RBL unchanged. At this time, the write transistor is turned on, transmitting a voltage of 0V from the write bit line WBL to the storage node SN. After writing is complete, the voltage of both the write word line WWL and the write bit line WBL returns to 0V. The steps for writing 1 to the storage node SN are as follows: apply voltage V1 to the write word line WWL, apply voltage V0 to the write bit line WBL, and keep the voltages of the read word line RWL and the read bit line RBL unchanged. At this time, the write transistor is turned on, transmitting voltage V0 from the write bit line WBL to the storage node SN; After writing is complete, the voltage of both the write word line WWL and the write bit line WBL returns to 0V. The steps for encrypted reading of the memory cell are as follows: After pre-charging the read bit line RBL to voltage V2, the read bit line RBL is placed in a floating state. Voltage V2 is applied to the write word line WWL and the read word line RWL, while the write bit line WBL voltage remains unchanged. At this time, if the information stored in the storage node SN and the ferroelectric capacitor is both 0, the read transistor current is small, the read bit line RBL voltage is V3, and the output voltage after inputting to the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in the storage node SN and the ferroelectric capacitor is both 1, the read transistor current is large, the read bit line RBL voltage drops to V4, and the output voltage after inputting to the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in the storage node SN is... If the information stored in the ferroelectric capacitor is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is between the smaller and larger values ​​of the read transistor current. The voltage of the read bit line RBL drops to V5, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. If the information stored in the storage node SN is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is between the smaller and larger values ​​of the read transistor current. The voltage of the read bit line RBL drops to V6, and after inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. After reading, the voltages of the write word line WWL, the read word line RWL, and the read bit line RBL all return to 0V. Before and after the read operation, the voltage and ferroelectric polarization of the storage node SN remain unchanged.

4. The operating method as described in claim 3, characterized in that, In the encryption reading step, the ferroelectric capacitor stores... The key information is stored in the memory cell SN, and the plaintext information is stored in the storage node SN. After the read information of the memory cell is input into the tri-state comparison circuit, the output information is the encrypted ciphertext information read out.

5. A memory array composed of the memory cells described in claim 1, characterized in that, By the memory unit The elements are arranged in a matrix structure with repetition along the horizontal and vertical axes. The memory cells in the same row share a write word line WWL and a read word line RWL, and the memory cells in the same column share a write bit line WBL and a read bit line RBL.

6. A method for controlling the operation of a memory array as described in claim 5, characterized in that, For the memory in the array When a unit performs control operations, it needs to write the key by column, write the plaintext by row, and read the ciphertext by row. If it is writing information to a ferroelectric capacitor, it needs to write 1 to all memory cells in the selected column first, and then write 0 to the memory cells in the column that are needed to complete the key writing operation. If writing information to the storage node SN, information can be written to all memory cells in a row at the same time, thus completing the plaintext writing operation; if reading encrypted information, encrypted information in all cells of the selected row can be read at the same time. The operation method of the memory array includes three parts: writing the key, writing the plaintext, and reading the ciphertext. For each memory cell, the order of these three operations is: first write the key, then write the plaintext, and then read the ciphertext.

7. The memory array operation method as described in claim 6, characterized in that, Specifically as follows: (1) The specific method for writing the key is as follows: First, write a 1 to the ferroelectric capacitor of the memory cell with key 1 in the selected column. Specifically, apply voltage V1 to all write word lines WWL, apply voltage V2 to the corresponding write bit line WBL, and keep the voltage of the other write bit lines at 0V. The voltage of the read word line RWL corresponding to the memory cell with key 1 is 0V, the voltage of the read word line RWL corresponding to the memory cell with key 0 is V2, and the voltage of all read bit lines RBL remains unchanged. At this time, the write transistors of all cells in the array are turned on, and the voltage across the ferroelectric capacitor of the memory cell with key 1 in the selected column is V2, which exceeds the coercivity voltage V of the ferroelectric capacitor. C The polarization direction of the ferroelectric capacitor is reversed from SN to RWL. The voltage across the ferroelectric capacitors of the remaining memory cells in the array is 0V, and the ferroelectric polarization does not reverse. After writing is complete, all WWL, WBL and RWL voltages return to 0V. Next, write 0 to the ferroelectric capacitor of the memory cell with key 0 in the selected column. Specifically, apply voltage V1 to the write word line WWL of the corresponding cell, apply voltage 0V to WBL of the selected column, and apply voltage V2 to the remaining WBL and all RWLs at the same time. The voltage of the read bit line RBL remains unchanged. At this time, the write transistors of the corresponding memory cell and other cells in the same row are turned on. The voltage across the ferroelectric capacitor of the corresponding memory cell in the selected column is V2, and the polarization direction of the ferroelectric capacitor is reversed from RWL to SN. The voltage across the ferroelectric capacitor of other cells in the same row is 0V, and the ferroelectric polarization does not reverse. The write transistors of the memory cells in the remaining rows of the selected column are turned off. Due to the low off-state current and small gate-source capacitance of the write transistor, the coupling voltage between the SN node and WWL is small. The voltage of the SN node is discharged slowly through the off-state current of the write transistor. Therefore, the RWL voltage is almost entirely coupled to the SN node, and the voltage across the ferroelectric capacitor is approximately 0V, and the ferroelectric polarization does not reverse. For the remaining rows and columns of memory cells, the write transistor is turned off, and the WBL voltage is transmitted to the memory node SN through the forward bias PIN current of the write transistor. Since the remaining WBL and all RWL are simultaneously subjected to voltage V2, the voltage across the ferroelectric capacitor is 0V, and the ferroelectric polarization does not flip. After the write is completed, all WWL voltages, WBL voltages, and RWL voltages return to 0V. Repeating the above operation on other columns in the memory array allows key information to be written to all cells in the array. (2) The specific method for writing plaintext is as follows: Plaintext information is written to the memory cell of the selected row. Specifically, voltage V1 is applied to WWL of the selected row, voltage 0V is applied to the write bit line WBL corresponding to the cell with plaintext 0, voltage V0 is applied to the write bit line WBL corresponding to the cell with plaintext 1, and the voltages of read word line RWL and read bit line RBL remain unchanged. At this time, the write transistor of the selected row is turned on, transmitting voltage from the write bit line WBL to the storage node SN; After the writing is complete, all WWL and WBL voltages return to 0V; since V0 is less than the coercive voltage V of the ferroelectric capacitor. c During the writing of plaintext information, the ferroelectric capacitor does not flip, and the key information is not destroyed. By repeating the above operation on other rows in the memory array, plaintext information can be written to all cells in the array. (3) The method for reading ciphertext is as follows: The encrypted information of the selected row's memory cell is read. Specifically, after pre-charging all read bit lines RBL to V2, the read bit lines RBL are placed in a floating state. V2 is applied to the write word line WWL of the selected row, and V2 is applied to the read word line RWL of the selected row, while the write bit line WBL voltage remains unchanged. At this time, if the information stored in the memory node SN and the ferroelectric capacitor is 0, the read transistor current is small, the read bit line RBL voltage is V3, and the output voltage after inputting into the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in the memory node SN and the ferroelectric capacitor is 1, the read transistor current is large, the read bit line RBL voltage drops to V4, and the output voltage after inputting into the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in the memory node SN and the ferroelectric capacitor is 1, the read transistor current is large, the read bit line RBL voltage drops to V4, and the output voltage after inputting into the tri-state comparator circuit is V2, i.e., the encrypted information is 1. If the information stored in node N is "0" and the information stored in the ferroelectric capacitor is "1", then the current of the read transistor is between the smaller and larger values ​​of the read transistor current, and the voltage of the read bit line RBL drops to V5. After inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. If the information stored in node SN is "1" and the information stored in the ferroelectric capacitor is "0", then the current of the read transistor is between the smaller and larger values ​​of the read transistor current, and the voltage of the read bit line RBL drops to V6. After inputting into the tri-state comparator circuit, the output is 0V, meaning the encrypted information is 0. After reading, the voltages of the write word line WWL, read word line RWL, and read bit line RBL all return to 0V. Before and after the read operation, the voltage and ferroelectric polarization of node SN remain unchanged.

8. The operating method as described in claim 3 or claim 7, characterized in that, The voltage V0 is between 0V and 2V. The voltages V1, V2, V3, V5, and V6 are approximately equal to the turn-on voltage of the readout tube. V1 is between 0V and -5V, V2 is between 0V and 5V, V3 is between 0V and V2, V5 and V6 are between 0V and V3, and V4 is a positive number less than V5 and V6. V5 and V6 are approximately equal.

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