A tunneling field effect transistor based dynamic random access memory array and method of controlling the same

Abstract

The application provides a dynamic random access memory array based on tunneling field effect transistor and a control method thereof. The memory array is formed by repeatedly arranging storage units in horizontal and vertical directions, the same row of storage units sharing a write word line and a read word line, and the same column of storage units sharing a write bit line and a read bit line; the storage unit comprises a P-type tunneling field effect transistor as a write transistor, an N-type tunneling field effect transistor as a read transistor, and a capacitor as an amplification unit, the write transistor, the read transistor and the capacitor are connected to form a storage node SN, the gate of the write transistor is connected to the write word line, the drain is connected to the write bit line, and the source is connected to the storage node, the gate of the read transistor is connected to the storage node, the drain is connected to the read bit line, and the source is connected to the ground, and the capacitor is connected to the storage node at one end and to the read word line at the other end. The application can prolong the retention time of dynamic random access memory, reduce power consumption, relieve read crosstalk problem, increase storage window and array size.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a dynamic random access memory array based on tunneling field-effect transistors and its control method. Background Technology

[0002] The development of AIoT technology has placed higher demands on semiconductor memory. Both edge and node devices in AIoT require low-power, low-cost, and relatively large-scale memory.

[0003] However, among traditional volatile memories, static random access memory (SRAM) has high hardware costs and high static power consumption, while dynamic random access memory (DRAM) has short retention times and high refresh power consumption. Therefore, inventing a low-hardware-cost, low-power volatile memory is of great significance. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a dynamic random access memory array based on tunneling field-effect transistors and its control method. In terms of dynamic random access memory, it can extend the hold time of dynamic random access memory, reduce the refresh frequency and refresh power consumption, thereby reducing read bit line leakage in dynamic random access memory, alleviating read crosstalk problems, and increasing the memory window and array size.

[0005] The technical solution of this invention is as follows:

[0006] A dynamic random access memory array based on tunneling field-effect transistors is characterized in that it is composed of memory cells arranged repeatedly in the horizontal and vertical directions, with memory cells in the same row sharing a write word line WWL and a read word line RWL, and memory cells in the same column sharing a write bit line WBL and a read bit line RBL.

[0007] The memory cell includes a P-type tunneling field-effect transistor as a write transistor, an N-type tunneling field-effect transistor as a read transistor, and a capacitor as an amplification unit. The write transistor, read transistor, and capacitor are interconnected to form a memory node SN. The gate electrode of the write transistor is connected to the write word line WWL, the drain electrode of the write transistor is connected to the write bit line WBL, and the source electrode of the write transistor is connected to the memory node SN. The gate electrode of the read transistor is connected to the memory node SN, the drain electrode of the read transistor is connected to the read bit line RBL, and the source electrode of the read transistor is connected to 0V. The capacitor, which serves as the amplification unit, is connected at one end to the memory node SN and at the other end to the read word line RWL.

[0008] The P / N type tunneling field-effect transistor has a source terminal including a source metal layer and a source semiconductor layer that wraps the source metal layer. The source terminal of the tunneling field-effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has bidirectional conduction characteristics. Its drain terminal is a certain distance from the gate boundary, which can suppress the bipolar current of the transistor and reduce the off-state current.

[0009] Furthermore, when the capacitor device used as the amplification unit is selected as the gate capacitance of a gate-controlled diode composed of a MOSFET device with connected source and drain, the gate of the MOSFET device is connected to the storage node SN, the source and drain electrodes of the MOSFET device are connected to the read word line RWL, and the substrate electrode of the MOSFET device is separately led out as the electrode CON for adjusting the capacitance.

[0010] Furthermore, the capacitor used as the amplification unit is selected as a capacitor with a high dielectric constant, or a capacitor provided by mature silicon-based CMOS technology: MOM capacitor, MIM capacitor, or PIP capacitor.

[0011] Furthermore, the peak doping concentration of the source semiconductor layer of the P / N tunneling field-effect transistor is 1e20cm⁻¹. -3 The width of the source semiconductor layer is 5 nm or more wider than the width of the source metal layer in the horizontal direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than the thickness of the source metal layer in the vertical direction.

[0012] Furthermore, the drain of the P / N tunneling field-effect transistor is 10 nm to 100 nm away from the gate.

[0013] The present invention also provides a method for controlling the dynamic random access memory array based on tunneling field-effect transistors, characterized by comprising four steps: holding, writing 1, writing 0, and reading, as follows:

[0014] In the hold state, i.e., when there are no write 1, write 0, or read operations, all write word line (WWL), write bit line (WBL), read word line (RWL), and read bit line (RBL) voltages in the dynamic random access memory array are 0V; if there is an electrode CON that controls the capacitance, then CON is subjected to a constant voltage V. B Furthermore, the voltage of CON remains unchanged during the read and write processes. In this dynamic random access memory array, if the information stored in a certain storage cell is "0", then the voltage of the corresponding storage node SN is 0V, and if the information stored in a certain storage cell is "1", then the voltage of the corresponding storage node SN is V0.

[0015] The steps for selecting a memory cell to write 0 in the dynamic random access memory array are as follows: apply voltage V1 to the write word line WWL of the selected memory cell, apply voltage 0V to the write bit line WBL of the selected memory cell, and keep the voltages of the other write word lines WWL, the other write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; at this time, the write transistor in the selected memory cell is turned on, and the voltage 0V is transmitted from the write bit line WBL to the memory node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected memory cell are both restored to 0V.

[0016] The steps for selecting a memory cell to write 1 to in the dynamic random access memory array are as follows: apply voltage V1 to the write word line WWL of the selected memory cell, apply voltage V0 to the write bit line WBL of the selected memory cell, and keep the voltages of the other write word lines WWL, the other write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; at this time, the write transistor in the selected memory cell is turned on, and the voltage V0 is transmitted from the write bit line WBL to the memory node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected memory cell are both restored to 0V.

[0017] The steps for selecting a specific memory cell to read from the dynamic random access memory array are as follows: The voltage of the read bit line RBL of the selected memory cell is pre-charged to voltage V2. Then, RBL is placed in a floating state. Voltage V2 is applied to the write word line WWL and the read word line RWL of the selected memory cell. The voltages of the remaining write word lines WWL, RBL, RWL, and WBL remain unchanged. At this time, if the information stored in the memory cell is "0", then the read operation is performed. When the output current is small, the read bit line RBL voltage is V3, which becomes V2 after being amplified by the sensitive amplifier. If the information stored in the memory cell is "1", then the read current is large, the read bit line RBL voltage drops to V4, and becomes 0V after being amplified by the sensitive amplifier. After reading, all read bit line RBL voltages are changed back to V2, then all write word line WWL and all read word line RWL voltages are restored to 0V, and finally all read bit line RBL voltages are restored to 0V. Before and after the read operation, the voltage of the memory node SN remains unchanged.

[0018] Furthermore, the voltage V0 is between 0V and 2V, approximately equal to the turn-on voltage of the readout tube; the voltage V1 is between 0V and -5V; the voltage V2 is between 0V and 5V; the voltage V3 is between 0V and V2; the voltage V4 is between 0V and V3; and the voltage V4 is 200mV or more lower than the voltage V3.

[0019] This invention discloses a dynamic random access memory array based on tunneling field-effect transistors and its control method. In terms of dynamic random access memory, it can extend the hold time of dynamic random access memory, reduce the refresh frequency and refresh power consumption; it can also reduce the leakage current of read bit lines in dynamic random access memory, alleviate read crosstalk problems, and increase the memory window and array size. Attached Figure Description

[0020] Figure 1 is a schematic equivalent circuit diagram of the memory cell proposed in this invention, wherein:

[0021] (1) is a schematic equivalent circuit diagram when the amplification unit is the gate capacitance of a MOSFET device;

[0022] (2) is a schematic equivalent circuit diagram when the amplification unit is a capacitor and a high dielectric constant capacitor provided in mature CMOS technology;

[0023] In the diagram: 1 – Write tube; 2 – Read tube; 3 – Amplification unit;

[0024] Figure 2 A schematic diagram of the tunneling field-effect transistor that constitutes the memory cell proposed in this invention;

[0025] In the diagram: 04 – Gate; 05 – Source metal layer; 06 – Source semiconductor layer; 07 – Drain.

[0026] 08—Substrate;

[0027] Figure 3 A cross-sectional view of an embodiment of an integrated circuit fabricated according to the unit circuit proposed in this invention;

[0028] In the picture:

[0029] 4—High-resistivity silicon substrate;

[0030] 5 – Shallow trench isolation; 6 – Upper isolation trap;

[0031] 7—Lower isolation trap; 8—Gate dielectric layer;

[0032] 9—Gate conductive layer of N-type device; 10—Gate conductive layer of P-type device;

[0033] 11—Compensation isolation layer; 12—Composite main isolation layer;

[0034] 13 – N+SD area; 14 – P+SD area;

[0035] 15—N+ extended region; 16—P+ extended region;

[0036] 17—Self-aligned silicide; 18—Inter-hole dielectric layer;

[0037] 19 – Contact hole; 20 – WBL metal interconnect;

[0038] 21—WWL metal interconnect; 22—SN metal interconnect;

[0039] 23—RBL metal interconnect; 24—GND metal interconnect;

[0040] 25—Intermetallic dielectric layer; 26—Lower electrode of capacitor;

[0041] 27—Capacitor dielectric layer; 28—Capacitor upper plate;

[0042] 29 – Metal interconnect via; 30 – RWL metal interconnect;

[0043] Figure 4 A schematic equivalent circuit diagram is provided for the array structure proposed according to the present invention;

[0044] Figure 5 This is a voltage waveform diagram of reading and writing operations on the storage cells in the array, as proposed in an embodiment of the present invention. Detailed Implementation

[0045] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0046] Figure 1 is a schematic equivalent circuit diagram of the memory cell constituting the dynamic random access memory array proposed in this invention. The figure shows the connection relationship between the parts in the proposed memory cell. Write transistor 1 is a P-type tunneling field-effect transistor. The gate electrode of write transistor 1 is connected to the write word line WWL, the drain electrode of write transistor 1 is connected to the write bit line WBL, and the source electrode of write transistor 1 is connected to the memory node SN. Read transistor 2 is an N-type tunneling field-effect transistor. The gate electrode of read transistor 2 is connected to the memory node SN, the drain electrode of read transistor 2 is connected to the read bit line RBL, and the source electrode of read transistor 2 is connected to 0V. The amplification unit 3 in Figure 1(1) is the gate capacitor of the MOSFET. The gate of the MOSFET is connected to the memory node SN as one end of the capacitor. The source and drain of the MOSFET are connected together as the other end of the capacitor and connected to the read word line RWL. The substrate electrode of the MOSFET is brought out separately as the electrode CON for adjusting the size of the capacitor. The amplification unit 3 in Figure 1(2) is a capacitor provided in mature silicon-based CMOS technology: MOM capacitor, MIM capacitor or PIP capacitor, or a high dielectric constant capacitor. One end of the capacitor is connected to the storage node SN, and the other end of the capacitor is connected to the read word line RWL.

[0047] The tunneling field-effect transistors (TFETs) in Figure 1 should meet the following conditions: The P-type TFET acting as the write transistor needs to suppress bipolar current and its off-state current must be lower than the off-state current of silicon-based CMOS devices at the same process node. It also needs to have bidirectional conduction characteristics within the required read / write voltage range. The N-type TFET acting as the read transistor needs to suppress bipolar current and its off-state current must be lower than the off-state current of silicon-based CMOS devices at the same process node. It also needs to have a large turn-on voltage such that the turn-on voltage is approximately equal to the memory node voltage V corresponding to "1". SN Given that existing tunneling field-effect transistors (TFETs) fail to meet the above requirements, this invention provides a specific structural description of a TFET that satisfies these requirements. Figure 2 The device structure that conforms to the description is shown. Figure 2 The source terminal of the tunneling field-effect transistor shown consists of a source metal layer 05 and a source semiconductor layer 06 enclosing the source metal layer 05, and the doping concentration of the source semiconductor layer 06 is as high as 1e20cm. -3，The width of the source semiconductor layer 06 is 10 nm or more wider than the width of the source metal layer 05 in the lateral direction, and the thickness of the source semiconductor layer 06 is 10 nm or more thicker than the thickness of the source metal layer 05 in the vertical direction, thus preventing the source semiconductor layer 06 from being completely depleted. The boundary between the source metal layer 05 and the source semiconductor layer 06 is located near the boundary of the gate 04 of the tunneling field-effect transistor, making the source terminal of the tunneling field-effect transistor physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, achieving bidirectional conduction characteristics. The turn-on voltage can be adjusted by changing the distance between the boundary of 04 and the boundaries between 05 and 06. The drain terminal 07 of the tunneling field-effect transistor is spaced a distance from the gate 04, achieving the characteristic of suppressing bipolar current and having an off-state current lower than that of silicon-based CMOS devices at the same process node.

[0048] Figure 3 The figure shows a cross-sectional view of the memory cell in Figure 1 during actual integrated circuit fabrication. The figure illustrates one possible tunneling field-effect transistor (TFPT) structure; however, based on existing techniques and the memory structure design requirements proposed in this invention, the TFPT can be replaced with other structures. Figure 3The tunneling field-effect transistor shown is a planar device structure fabricated on a high-resistivity silicon substrate 4, with devices isolated from each other by shallow trench isolation 5. The gate dielectric layer 8 and gate conductive layers 9 and 10 form the gate region of the device. Only one side of the gate sidewall with the compensation isolation layer 11 corresponds to the source terminal, while the other side with the compensation isolation layer 11 and the composite main isolation layer 12 corresponds to the drain terminal. The self-aligned silicide 17, SD regions 13 and 14, and extended regions 15 and 16 form the source and drain terminals of the device. Each device's substrate region includes an upper isolation well 6 and a lower isolation well 7, used to isolate leakage current between source and drain regions of the same doping type between adjacent devices through the substrate. The source, gate, and drain electrodes of the device are led out through contact holes 19 and metal interconnects 20, 21, 22, 23, and 24, respectively. The device on the left is a P-type tunneling field-effect transistor, a write transistor. The gate conductive layer 10 of the P-type device is the gate conductive layer of this device, led out through WWL metal interconnects. The N+SD region 13, N+ extended region 15, and self-aligned silicide 17 form the source terminal of the write transistor, which is connected to the gate electrode and one end of the amplification unit of the read transistor via the SN metal interconnect 22. The P+SD region 14, P+ extended region 16, and self-aligned silicide 17 form the drain terminal of the write transistor, which is led out via the WBL metal interconnect 20. The device on the right is an N-type tunneling field-effect transistor, which is the read transistor. The gate conductive layer 9 of the N-type device is the gate conductive layer of this device, which is connected to the source electrode and one end of the amplification unit of the write transistor via the SN metal interconnect. The N+SD region 13, N+ extended region 15, and self-aligned silicide 17 form the drain terminal of the read transistor, which is led out via the RBL metal interconnect 23. The P+SD region 14, P+ extended region 16, and self-aligned silicide 17 form the source terminal of the read transistor, which is led out via the GND metal interconnect 24. MOSFET gate capacitors, MOM capacitors, MIM capacitors, and PIP capacitors are all capacitors available in mature CMOS processes, and cross-sectional views are not shown here. This section shows the case where amplifier unit 3 uses a high-dielectric-constant capacitor. This capacitor consists of a lower electrode 26, a dielectric layer 27, and an upper electrode 28, located between metal interconnects of adjacent layers. It does not affect the parameters and performance of the corresponding back-end interconnects of the CMOS device. The dielectric layer is made of a high-dielectric-constant dielectric material.

[0049] By arranging the proposed memory cells in a regular, repetitive manner, and taking Figure 1(2) as an example, the schematic equivalent circuit diagram of the dynamic random access memory array structure proposed in this invention can be obtained, as follows: Figure 4 As shown. Storage cells in the same row share a single write word line WWL, from WWL0 to WWL. m A total of m+1 rows of write word lines WWL are used. Storage cells in the same row share a single read word line RWL, from RWL0 to RWL. mThere are a total of m+1 read word lines RWL. Storage cells in the same column share a single write bit line WBL, from WBL0 to WBL... n A total of n+1 columns are written to the bit line WBL. Storage cells in the same column share a single read bit line RBL, from RBL0 to RBL... n A total of n+1 columns are written to the bit line RBL.

[0050] for Figure 4 The array structure shown allows for writing and reading from selected memory cells using the proposed method. Figure 5 An example of read and write voltage waveforms is given. When writing information, the write word line (WWL) voltage of the row containing the selected cell is pulled low from 0V to -2.5V, while the WWL voltage of the other rows remains at 0V. The write bit line (WBL) voltage corresponding to the memory cell in the selected row that needs to be written with a "0" is 0V, and the write bit line (WBL) voltage corresponding to the memory cell that needs to be written with a "1" is pulled high from 0V to 0.5V. After writing is complete, all WWL and WBL voltages return to 0V. The SN node voltage corresponding to the memory cell written with a "0" is 0V, and the SN node voltage corresponding to the memory cell written with a "1" is 0.5V. When reading information, the write word line WWL voltage of the row containing the selected cell is pulled high from 0V to 2.5V, and the read bit line RBL voltage corresponding to the memory cell in that row is pre-charged to 2.5V, then RBL is floated. The read word line RWL voltage of the row containing the selected cell is pulled high from 0V to 2.5V. Due to the voltage coupling effect of the amplification unit, the SN node voltage rises, and the SN node voltage corresponding to the cell containing the information "1" is higher than the original voltage. The SN node voltage corresponds to the cell storing information "0". Therefore, the read transistor corresponding to the cell storing information "1" discharges through RBL faster, resulting in a lower RBL voltage, which is pulled down to 0V after passing through the sensitive amplifier. Conversely, the read transistor corresponding to the cell storing information "0" discharges through RBL more slowly, resulting in a higher RBL voltage, which is pulled up to 2.5V after passing through the sensitive amplifier. To ensure that the SN node voltage does not change before and after reading, after reading is complete, all RBL voltages are pulled up to 2.5V, and then all RWL and WWL voltages are restored to 0V. Finally, all RBL voltages are restored to 0V, returning to the hold state.

[0051] Unlike the symmetrical gate capacitance of MOSFET devices, the tunneling field-effect transistor (TF-FET) of this invention exhibits asymmetrical gate capacitance, with its gate-source capacitance being significantly smaller than its gate-drain capacitance. Connecting the source electrode of the TF-FET to the memory node SN, the smaller gate-source capacitance of the TF-FET results in a lower coupling voltage between the write word line WWL and the memory node SN, which is less than the coupling voltage between WWL and SN when using a MOSFET device with the same gate area and process node as the write transistor. Therefore, using a TF-FET as the write transistor does not degrade the memory's write speed or hold time due to the coupling voltage between WWL and SN. Furthermore, when the TF-FET is in the off state, the tunneling window is closed, resulting in a low off-state current. Silicon-based TF-FETs have been experimentally proven to have lower off-state currents than silicon-based CMOS devices at the same process node. In the memory cell structure proposed in this invention, during the hold state, only the leakage path from the memory node SN to the write bit line WBL causes a drop in the SN node voltage. Using a tunneling field-effect transistor (TFTS) as the write transistor results in a lower leakage current from the SN to the WBL due to the TFTS's low off-state current advantage. This allows for a longer hold time than when using a MOSFET as the write transistor, thus reducing the refresh frequency and refresh power consumption.

[0052] If the read transistor is a MOSFET, since the threshold voltage of the MOSFET is relatively small, when the information stored in the memory cell is "1", the corresponding read transistor is in the hold state and will be turned on. Regardless of whether the cell is selected or not, the corresponding read transistor will charge and discharge the read bit line RBL, which will degrade the read speed and memory window. Moreover, the more cells in the same column of unselected cells that store information "1", the more serious the negative impact will be.

[0053] In the circuit structure proposed in this invention, the tunneling field-effect transistor (TFET) acts as the read signal. In the held state, if the stored information in the cell structure is "1", the gate voltage of the read signal is V0, approximately equal to the turn-on voltage of the read signal, meaning the read signal is not turned on. If the stored information in the cell structure is "0", the gate voltage of the read signal is 0V, and the read signal is also not turned on. To read the stored information in a particular cell structure, a voltage V2 is applied to the read line (RWL). Through the capacitor coupling voltage (acting as an amplification unit), the SN voltage is raised, thereby turning on the read signal and discharging the read line (RBL). At this time, for unselected cell structures in the same column, their read signals are not turned on and do not charge or discharge the read line (RBL). Therefore, the memory cell array proposed in this invention can reduce read bit line leakage in dynamic random access memory. Only the read signal of the selected cell in the same column discharges the read line (RBL), thereby alleviating read crosstalk problems and increasing the memory window and array size.

[0054] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A dynamic random access memory array based on tunneling field-effect transistors, characterized in that, It is composed of memory cells arranged repeatedly in the horizontal and vertical directions. The memory cells in the same row share one write word line WWL and one read word line RWL, and the memory cells in the same column share one write bit line WBL and one read bit line RBL. The memory cell includes a P-type tunneling field-effect transistor as a write transistor, an N-type tunneling field-effect transistor as a read transistor, and a capacitor as an amplification unit. The write transistor, read transistor, and capacitor are interconnected to form a memory node SN. The gate electrode of the write transistor is connected to the write word line WWL, the drain electrode of the write transistor is connected to the write bit line WBL, and the source electrode of the write transistor is connected to the memory node SN. The gate electrode of the read transistor is connected to the memory node SN, the drain electrode of the read transistor is connected to the read bit line RBL, and the source electrode of the read transistor is connected to 0V. The capacitor, which serves as the amplification unit, is connected at one end to the memory node SN and at the other end to the read word line RWL. The P-type tunneling field-effect transistor and the N-type tunneling field-effect transistor have a source terminal including a source metal layer and a source semiconductor layer that encapsulates the source metal layer. The source terminal of the tunneling field-effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has bidirectional conduction characteristics. Its drain terminal is a certain distance from the gate boundary, which can suppress the bipolar current of the transistor and reduce the off-state current.

2. The dynamic random access memory array based on tunneling field-effect transistors as described in claim 1, characterized in that, When the capacitor device used as the amplification unit is selected as the gate capacitance of the gate-controlled diode composed of a MOSFET device with connected source and drain, the gate of the MOSFET device is connected to the storage node SN, the source and drain electrodes of the MOSFET device are connected to the read word line RWL, and the substrate electrode of the MOSFET device is separately led out as the electrode CON for adjusting the capacitance.

3. The dynamic random access memory array based on tunneling field-effect transistors as described in claim 1, characterized in that, The capacitor used as the amplification unit is selected as a capacitor with a high dielectric constant, or a capacitor provided by mature silicon-based CMOS technology: MOM capacitor, MIM capacitor, or PIP capacitor.

4. A dynamic random access memory array based on a tunneling field-effect transistor as described in claim 1, characterized in that, The peak doping concentration of the source semiconductor layer of the P-type tunneling field-effect transistor and the N-type tunneling field-effect transistor is 1e20cm. -3 The width of the source semiconductor layer is 5 nm or more wider than the width of the source metal layer in the horizontal direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than the thickness of the source metal layer in the vertical direction.

5. A dynamic random access memory array based on a tunneling field-effect transistor as described in claim 1, characterized in that, The drain terminals of the P-type tunneling field-effect transistor and the N-type tunneling field-effect transistor are 10 nm to 100 nm away from the gate boundary.

6. A method for controlling a dynamic random access memory array based on a tunneling field-effect transistor as described in claim 1, characterized in that, It includes four steps: holding, writing 1, writing 0, and reading, as detailed below: In the hold state, i.e., when there are no write 1, write 0, or read operations, all write word line (WWL), write bit line (WBL), read word line (RWL), and read bit line (RBL) voltages in the dynamic random access memory array are 0V; if there is an electrode CON that controls the capacitance, then CON is subjected to a constant voltage V. B Furthermore, the voltage of CON remains unchanged during the read and write processes; In this dynamic random access memory array, if the information stored in a certain memory cell is "0", then the voltage of the corresponding memory node SN is 0V; if the information stored in a certain memory cell is "1", then the voltage of the corresponding memory node SN is V0. The steps for selecting a memory cell to write 0 in the dynamic random access memory array are as follows: apply voltage V1 to the write word line WWL of the selected memory cell, apply voltage 0V to the write bit line WBL of the selected memory cell, and keep the voltages of the remaining write word line WWL, the remaining write bit line WBL, the read word line RWL and the read bit line RBL unchanged. At this time, the write transistor in the selected memory cell is turned on, transmitting a voltage of 0V from the write bit line WBL to the memory node SN. After the writing is complete, the voltage of the write word line WWL and the write bit line WBL of the selected memory cell both return to 0V. The steps for selecting a memory cell to write 1 to in the dynamic random access memory array are as follows: apply voltage V1 to the write word line WWL of the selected memory cell, apply voltage V0 to the write bit line WBL of the selected memory cell, and keep the voltages of the remaining write word line WWL, the remaining write bit line WBL, the read word line RWL and the read bit line RBL unchanged. At this time, the write transistor in the selected memory cell is turned on, transmitting voltage V0 from the write bit line WBL to the memory node SN. After the writing is complete, the voltage of the write word line WWL and the write bit line WBL of the selected memory cell both return to 0V. The steps for selecting a memory cell to read from the dynamic random access memory array are as follows: The voltage of the read bit line RBL of the selected memory cell is pre-charged to voltage V2. Then, RBL is placed in a floating state. Voltage V2 is applied to the write word line WWL and the read word line RWL of the selected memory cell. The voltages of the remaining write word lines WWL, RBL, RWL, and WBL remain unchanged. If the information stored in the memory cell is "0", the voltage of the read bit line RBL is V3, which is amplified to V2 by a sensitive amplifier. If the information stored in the memory cell is "1", the voltage of the read bit line RBL drops to V4, which is amplified to 0V by a sensitive amplifier. After reading, all read bit line RBL voltages are returned to V2. Then, all write word lines WWL and all read word lines RWL voltages are restored to 0V, and finally, all read bit line RBL voltages are restored to 0V. The voltage of the memory node SN remains unchanged before and after the read operation. The voltage V0 is between 0V and 2V, approximately equal to the turn-on voltage of the readout tube. The voltage V1 is between 0V and -5V. The voltage V2 is between 0V and 5V. The voltage V3 is between 0V and V2. The voltage V4 is between 0V and V3. The voltage V4 is 200mV or more lower than the voltage V3.

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