Dynamic random access memory testing method and apparatus

Abstract

The present disclosure provides a dynamic random memory testing method and device, and relates to the technical field of memory. The dynamic random memory comprises a substrate and a plurality of memory cells, each memory cell comprising a storage capacitor and a first transistor (NMOS transistor), the first plate of the storage capacitor of each memory cell being electrically connected with the drain of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each memory cell being electrically connected with the substrate. The method comprises: charging the storage capacitor of each memory cell by applying a first voltage on the substrate and a second voltage on the second plate of the storage capacitor of each memory cell, the first voltage being higher than the second voltage; and performing a reading operation on each memory cell after the storage capacitor of each memory cell is charged for a predetermined time length, so as to perform a burn-in test on the dynamic random memory. The method can avoid the loss of related circuits caused by the instruction actions of activation, writing and pre-charging in the burn-in test.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a method and apparatus for testing dynamic random access memory (DRAM). Background Technology

[0002] The aging test for Dynamic Random Access Memory (DRAM) chips eliminates early failures by controlling the chip's operating state and applying temperature stress. The main purpose of the aging test vector is to increase the internal test stress of the device, improve aging efficiency, and induce abnormal phenomena in the device, thereby eliminating defective products at an early stage.

[0003] The capacitance aging test of DRAM chips requires writing a background. In related technologies, background writing involves activating each word line (WL) individually, and then writing each bit line (BL) after each word line is activated. After all bit lines are written, a precharge is performed before activating the next word line. This results in circuit losses exceeding capacitor losses, potentially leading to insufficient DRAM capacitance aging efficiency. Some components, such as WL circuits, BL circuits, sense amplifier (SA) circuits, or other circuits, may prematurely enter their wear-out failure period.

[0004] As mentioned above, how to reduce the losses of circuits such as WL, BL, and SA caused by write background during capacitor aging tests has become an urgent problem to be solved.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a dynamic random access memory (DRAM) testing method and apparatus that can at least reduce the losses of circuits such as WL, BL, and SA caused by write background during capacitor aging tests.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to one aspect of this disclosure, a method for testing dynamic random access memory (DRAM) is provided, comprising: the DRAM includes a substrate and a plurality of memory cells, each memory cell including a storage capacitor and a first transistor, the first transistor being an NMOS transistor; the first plate of the storage capacitor of each memory cell is electrically connected to the drain of the corresponding first transistor; the P-type silicon substrate of the first transistor of each memory cell is electrically connected to the substrate; the method includes: charging the storage capacitor of each memory cell by applying a first voltage to the substrate and applying a second voltage to the second plate of the storage capacitor of each memory cell, wherein the first voltage is higher than the second voltage; and after the storage capacitor of each memory cell has been charged for a predetermined period of time, performing a read operation on each memory cell to perform an aging test on the DRAM.

[0009] According to one embodiment of this disclosure, applying a first voltage to the substrate and a second voltage to the second plates of each storage capacitor includes: sending a first input signal to the input terminal of a voltage switching circuit to switch the voltage applied to the substrate from a third voltage to the first voltage, and switching the voltage applied to the second plates of each storage capacitor from a fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

[0010] According to one embodiment of this disclosure, the voltage switching circuit includes a first inverter and a second inverter, with the input terminal of the first inverter connected to the input terminal of the second inverter; sending a first input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from a third voltage to the first voltage, and to switch the voltage applied on the second plates of each storage capacitor from a fourth voltage to the second voltage, includes: sending the first input signal to a common input terminal of the first inverter and the second inverter to switch the voltage applied on the substrate from the third voltage to the first voltage via the first inverter, and to switch the voltage applied on the second plates of each storage capacitor from the fourth voltage to the second voltage via the second inverter.

[0011] According to one embodiment of this disclosure, after the storage capacitors of each storage cell have been charged for a predetermined period of time, a read operation is performed on each storage cell, including: after the storage capacitors of each storage cell have been charged for a predetermined period of time, sending a second input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and switching the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

[0012] According to one embodiment of this disclosure, the voltage switching circuit includes a first inverter and a second inverter, the first inverter and the second inverter sharing an input terminal; sending a second input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and to switch the voltage applied on the second plates of each storage capacitor from the second voltage to the fourth voltage, includes: sending the second input signal to the shared input terminal of the first inverter and the second inverter to switch the voltage applied on the substrate from the first voltage to the third voltage through the first inverter, and to switch the voltage applied on the second plates of each storage capacitor from the second voltage to the fourth voltage.

[0013] According to one embodiment of this disclosure, the method further includes: obtaining the region size of the plurality of memory cells; determining the voltage difference between a first voltage and a second voltage based on the region size of the plurality of memory cells, so as to obtain the first voltage and the second voltage.

[0014] According to another aspect of this disclosure, a dynamic random access memory (DRAM) testing apparatus is provided, comprising: the DRAM including a substrate and a plurality of memory cells, each memory cell including a storage capacitor and a first transistor, the first transistor being an NMOS transistor, the first plate of the storage capacitor of each memory cell being electrically connected to the drain of the corresponding first transistor, and the P-type silicon substrate of the first transistor of each memory cell being electrically connected to the substrate; the apparatus comprising: a control module for charging the storage capacitor of each memory cell by applying a first voltage to the substrate and applying a second voltage to the second plate of the storage capacitor of each memory cell, wherein the first voltage is higher than the second voltage; and a testing module for performing a read operation on each memory cell after the storage capacitor of each memory cell has been charged for a predetermined period of time, so as to perform an aging test on the DRAM.

[0015] According to an embodiment of this disclosure, the control module is further configured to: send a first input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from a third voltage to the first voltage, and to switch the voltage applied on the second plates of each storage capacitor from a fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

[0016] According to one embodiment of this disclosure, the voltage switching circuit includes a first inverter and a second inverter, with the input terminal of the first inverter connected to the input terminal of the second inverter; the control module is further configured to: send the first input signal to the common input terminal of the first inverter and the second inverter, so as to switch the voltage applied on the substrate from the third voltage to the first voltage through the first inverter, and switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

[0017] According to an embodiment of this disclosure, the control module is further configured to: after the storage capacitors of each storage cell have been charged for a predetermined period of time, send a second input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

[0018] According to one embodiment of this disclosure, the voltage switching circuit includes a first inverter and a second inverter, the first inverter and the second inverter sharing an input terminal; the control module is further configured to: send a second input signal to the shared input terminal of the first inverter and the second inverter, so as to switch the voltage applied on the substrate from the first voltage to the third voltage through the first inverter, and switch the voltage applied on the second plates of each storage capacitor from the second voltage to the fourth voltage.

[0019] According to one embodiment of this disclosure, the apparatus further includes: a determining module, further configured to obtain the region size of the plurality of storage cells; and to determine the voltage difference between a first voltage and a second voltage based on the region size of the plurality of storage cells, so as to obtain the first voltage and the second voltage.

[0020] According to another aspect of this disclosure, a dynamic random access memory (DRAM) testing apparatus is provided, comprising a DRAM under test and a voltage switching circuit, wherein: the DRAM under test includes a substrate and a plurality of memory cells, each memory cell including a storage capacitor and a first transistor, the first transistor being an NMOS transistor; the first plate of the storage capacitor of each memory cell is electrically connected to the drain of the corresponding first transistor; and the P-type silicon substrate of the first transistor of each memory cell is electrically connected to the substrate; the voltage switching circuit includes a first output terminal and a second output terminal; the first output terminal of the voltage switching circuit is electrically connected to the substrate and is used to apply a first voltage to the substrate; the second output terminal of the voltage switching circuit is electrically connected to the second plate of each storage capacitor and is used to apply a second voltage to the second plate of each storage capacitor; the first voltage is higher than the second voltage, so as to charge the storage capacitor of each memory cell.

[0021] According to one embodiment of this disclosure, the voltage switching circuit includes a first inverter and a second inverter, the input terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the first inverter is the first output terminal, and the output terminal of the second inverter is the second output terminal.

[0022] According to one embodiment of this disclosure, both the first inverter and the second inverter are CMOS transistors.

[0023] According to one embodiment of this disclosure, the drains of the NMOS transistor and the PMOS transistor of the first inverter are connected to the first output terminal. The input voltage of the source of the PMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the NMOS transistor of the first inverter is a third voltage. The drains of the NMOS transistor and the PMOS transistor of the second inverter are connected to the second output terminal. The input voltage of the source of the PMOS transistor of the second inverter is the second voltage, and the input voltage of the source of the NMOS transistor of the second inverter is a fourth voltage, which is higher than the third voltage. The input terminals of the first inverter and the second inverter are used to receive a first input signal to turn on the PMOS transistors of the first inverter and the second inverter, and to turn off the NMOS transistors of the first inverter and the second inverter.

[0024] According to one embodiment of this disclosure, the input terminals of the first inverter and the second inverter are further configured to receive a second input signal, so as to turn off the PMOS transistors of the first inverter and the second inverter, and turn on the NMOS transistors of the first inverter and the second inverter.

[0025] According to one embodiment of this disclosure, the drains of the NMOS transistor and the PMOS transistor of the first inverter are connected to the first output terminal. The input voltage of the source of the NMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the PMOS transistor of the first inverter is the third voltage. The drains of the NMOS transistor and the PMOS transistor of the second inverter are connected to the second output terminal. The input voltage of the source of the NMOS transistor of the second inverter is the second voltage, and the input voltage of the source of the PMOS transistor of the second inverter is the fourth voltage, which is higher than the third voltage. The input terminals of the first inverter and the second inverter are used to receive a first input signal to turn on the NMOS transistors of the first inverter and the second inverter, and to turn off the PMOS transistors of the first inverter and the second inverter.

[0026] According to one embodiment of this disclosure, the input terminals of the first inverter and the second inverter are further configured to receive a second input signal, so as to turn off the NMOS transistors of the first inverter and the second inverter, and turn on the PMOS transistors of the first inverter and the second inverter.

[0027] According to one embodiment of this disclosure, the first output terminal of the voltage switching circuit is electrically connected to the substrate via a connecting plug.

[0028] According to another aspect of this disclosure, an electronic device is provided, comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor, when executing the executable instructions, implements any of the methods described above.

[0029] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, which, when executed by a processor, implement any of the methods described above.

[0030] The dynamic random access memory (DRAM) testing method provided in the embodiments of this disclosure applies a first voltage to a substrate electrically connected to the P-type silicon substrate of the first transistor of each memory cell, and applies a second voltage lower than the first voltage to the second plates of each memory capacitor electrically connected to the drain of the corresponding first transistor. This charges the memory capacitor of each memory cell. After the memory capacitor of each memory cell has been charged for a predetermined period of time, a read operation is performed on each memory cell to perform a aging test on the DRAM. This method can replace the word line activation, bit line writing, and pre-charging instruction actions used in the capacitor aging test of related technologies, thereby avoiding the loss of circuits involved in these instruction actions due to the write background.

[0031] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0032] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0033] Figure 1 An example flowchart of a background writing operation is shown.

[0034] Figure 2 A graph showing the relationship between the failure period and failure rate of a device is presented.

[0035] Figure 3 A schematic diagram of a DRAM architecture according to an embodiment of this disclosure is shown.

[0036] Figure 4 It is based on Figure 3 The diagram shows a side view of the structure of a wafer in a DRAM array.

[0037] Figure 5 A flowchart illustrating a method for testing a dynamic random access memory (DRAM) according to an embodiment of this disclosure is shown.

[0038] Figure 6 This is a schematic diagram of a voltage switching circuit according to an exemplary embodiment.

[0039] Figure 7 This is a schematic diagram of another voltage switching circuit according to an exemplary embodiment.

[0040] Figure 8 It is based on Figures 5 to 7 A flowchart of another dynamic random access memory testing method is shown.

[0041] Figure 9 It is based on Figure 8 The diagram illustrates a process for writing background information.

[0042] Figure 10 It is based on Figure 8 The diagram shows a flow chart of a read operation.

[0043] Figure 11 A block diagram of a dynamic random access memory testing apparatus according to an embodiment of the present disclosure is shown.

[0044] Figure 12 A block diagram of another dynamic random access memory testing apparatus is shown in an embodiment of this disclosure.

[0045] Figure 13A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0046] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0047] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0048] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0049] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0050] Aging testing eliminates early failures by controlling the chip's operating state and applying temperature stress. Aging tests can be divided into static aging, dynamic aging, and aging-in-process testing. Static aging refers to providing voltage only to the circuit's power supply terminals, without providing aging vectors to the signal input pins; in this case, the internal transistors essentially do not flip. Aging-in-process testing involves sampling the circuit's electrical parameters during dynamic aging to complete all or part of the functional testing during the aging process. Dynamic aging involves providing the circuit's power supply voltage and aging vectors, enabling the circuit to perform a certain function during aging and causing the internal transistors to flip. The main purpose of aging test vectors is to increase the internal test stress of the device, improve aging efficiency, and induce abnormal phenomena in the device, thereby eliminating defective products at an early stage.

[0051] The capacitance aging test vector of DRAM chips requires writing to the background. Related technologies use Active, Write, and Precharge instructions to sequentially activate the WL (Wasteland Level) during background writing, or employ Design for Test (DFT) to activate a large number of WLs simultaneously. Figure 1 An exemplary flowchart of a background writing operation is shown. Figure 1 As shown, taking a memory array connected to X word lines and Y bit lines as an example, the current word line is activated (S102), and after each word line is activated, "1" is written to each bit line one by one (S104). While writing "1", the process waits for n (n is a positive integer) DeviceDeselected (DES) instructions (S106), where DES instructions are defined in the DRAM command truth table. Then, after traversing and writing Y bit lines (S107), the current word line is precharged (S108), and then the activation action of the next word line is entered to traverse X word lines (S109). This causes the circuit losses involved in these instruction actions to be greater than the capacitor losses, resulting in insufficient DRAM capacitor aging efficiency, but some devices prematurely entering the wear and tear failure period.

[0052] Figure 2 A graph showing the relationship between the failure period and failure rate of a device is presented, such as... Figure 2 As shown, the method of writing background in the aging test used in related technologies may cause DRAM capacitors to still be in the early failure period, while some devices, such as WL circuits, BL circuits, sense amplifier (SA) circuits, or other circuits, have entered the wear and tear failure period.

[0053] Therefore, this disclosure provides a dynamic random access memory (DRAM) testing method. A first voltage is applied to a substrate electrically connected to the P-type silicon substrate of the first transistor of each memory cell, and a second voltage lower than the first voltage is applied to the second plates of each memory capacitor electrically connected to the drain of the corresponding first transistor. This charges the memory capacitor of each memory cell. After the memory capacitor of each memory cell has been charged for a predetermined period, a read operation is performed on each memory cell to perform a aging test on the DRAM. This method can replace the word line activation, bit line writing, and pre-charging instruction actions used in the capacitor aging test of related technologies, thereby avoiding the circuitry losses caused by the write background in these instruction actions.

[0054] Figure 3 An exemplary DRAM architecture 30 is shown that the dynamic random access memory (DRAM) testing method or DRAM testing apparatus of this disclosure can be applied to illustrate the DRAM architecture 30 as the DRAM to be tested in the embodiments of this disclosure.

[0055] The architecture 30 of the dynamic random access memory to be tested may include multiple memory cells. Figure 3 Two memory cells, 3062 and 3064, are shown in the figure. Figure 4 , Figure 4 Storage capacitors 4062 and 4064 are connected to the drains 4082 and 4084 of two NMOS transistors (i.e., the first transistor) via NC (Node Contact). The two transistors share a source 3066. Storage capacitor 4062 and its connected transistors together form storage cell 3062, and storage capacitor 4064 and its connected transistors together form storage cell 3064. The two NMOS transistors share a source 3066 connected to BL304, and their gates 4086 and 4088 are connected to WL306. Figure 3 The memory cell array in the middle can be set up Figure 4 On substrate 402.

[0056] Figure 4 It is based on Figure 3 This is a schematic diagram of the structure of a memory cell in a DRAM array, shown from the side view. (Refer to...) Figure 3 , Figure 4A side cross-sectional view of a memory cell group 306 with two shared source capacitors 3066 is shown. The memory capacitors 4062 and 4064 share a common top cell plate (TCP) (i.e., the second plate) 404, and the voltage applied to the TCP 404 is a second voltage V2. The lower plates (i.e., the first plates) of the memory capacitors 4062 and 4064 are connected to the drains 4082 and 4084 of the two transistors respectively via NC. The P-type silicon substrates (also called P-wells) of the two transistors are disposed on a substrate 402 and electrically connected to the substrate, so that the memory capacitors 4062 and 4064 are electrically connected to the substrate through the PN junctions of the two transistors.

[0057] In some embodiments, a connection plug 410 electrically connected to the substrate 402 may be provided, through which a first voltage V1 is applied to the substrate 402, i.e., to the lower plate of storage capacitors 4062 and 4064. The connection plug 410 is shallow trench isolated (STI) from the PN junction.

[0058] In some embodiments, a voltage switching circuit can be configured to change the voltage applied to the substrate 402 and the voltage applied to the TCP 404. For example, the first output terminal of the voltage switching circuit can be electrically connected to the substrate 402 via a connecting plug 410 to switch the voltage applied to the substrate 402 from a third voltage to a first voltage higher than the third voltage, and switch the voltage applied to the TCP 404 from a fourth voltage higher than the third voltage to a second voltage lower than the first voltage to charge the storage capacitors 4062 and 4064.

[0059] It should be understood that Figure 3 The number of storage units shown is merely illustrative. Depending on implementation requirements, any number of storage units can be used.

[0060] Figure 5 This is a flowchart illustrating a dynamic random access memory (DRAM) testing method according to an exemplary embodiment. Figure 5 The method shown can be applied, for example, to... Figure 3 and Figure 4 The multiple storage units shown.

[0061] refer to Figure 5 The method 50 provided in this embodiment may include the following steps.

[0062] In step S502, the storage capacitor of each storage cell is charged by applying a first voltage to the substrate and applying a second voltage to the second plate of the storage capacitor of each storage cell. The first voltage is higher than the second voltage.

[0063] In some embodiments, a voltage switching circuit electrically connected to the substrate can be provided. By sending a first input signal to the input terminal of the voltage switching circuit, the voltage applied to the substrate can be switched from a third voltage to a first voltage, and the voltage applied to the second plates of each storage capacitor can be switched from a fourth voltage to a second voltage. The third voltage is lower than the first voltage, and the fourth voltage is higher than the second voltage. Detailed embodiments can be found in [reference needed]. Figure 6 and Figure 7 .

[0064] In some embodiments, the voltage difference between the first voltage and the second voltage used in the aging test may be determined according to the manufacturing process.

[0065] In some embodiments, the voltage difference between the first voltage and the second voltage can also be determined by considering the number of storage cells, i.e., the size of the area where the storage cells to be aged are located. Specific implementation methods can be found in [reference needed]. Figure 8 and Figure 9 .

[0066] In step S504, after the storage capacitors of each storage cell have been charged for a predetermined period of time, a read operation is performed on each storage cell to perform an aging test on the dynamic random access memory.

[0067] In some embodiments, after switching the voltage applied to the substrate from a third voltage to a first voltage and switching the voltage applied to the second plate of each storage capacitor from a fourth voltage to a second voltage, a read operation is performed on each memory cell bit by bit and word by word after waiting for a preset number of command clocks (tCK) to perform an aging test on the dynamic random access memory. The preset number of command clocks can be, for example, the duration of n DES instructions. Detailed implementation can be found in [reference needed]. Figure 8 and Figure 9 .

[0068] According to the dynamic random access memory (DRAM) testing method provided in this disclosure, a first voltage is applied to a substrate electrically connected to the P-type silicon substrate of the first transistor of each memory cell, and a second voltage lower than the first voltage is applied to the second plates of each memory capacitor electrically connected to the drain of the corresponding first transistor. This charges the memory capacitor of each memory cell. After the memory capacitor of each memory cell has been charged for a predetermined period, a read operation is performed on each memory cell to perform a aging test on the DRAM. This method can replace the word line activation, in-bit line writing, and pre-charging instruction actions used in the capacitor aging test of related technologies, thereby avoiding the circuitry losses caused by writing background in these instruction actions. Furthermore, while achieving the same capacitor test coverage as related technologies, it saves the time of activation, writing, and pre-charging instruction actions, reduces the time spent writing background in the capacitor aging test, and improves test efficiency.

[0069] Figure 6 This is a schematic diagram of a voltage switching circuit according to an exemplary embodiment. Figure 6 The voltage switching circuit shown can be used to... Figure 4 A voltage is applied to substrate 402 and a voltage is applied to TCP 404 to implement... Figure 5 The method shown.

[0070] like Figure 6 As shown, the voltage switching circuit may include a first output terminal 6042 and a second input terminal 6044. The first output terminal 6042 of the voltage switching circuit is electrically connected to the substrate 402, and the second input terminal 6044 is electrically connected to TCP 404. The voltage switching circuit may include a first inverter and a second inverter. The input terminals of the first inverter and the second inverter are connected to receive the input signal 602. The output terminal of the first inverter is the first output terminal 6042, and the output terminal of the second inverter is the second output terminal 6044.

[0071] Both the first inverter and the second inverter can be CMOS (Complementary Metal Oxide Semiconductor) transistors. The drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the first output terminal 6042 of the voltage switching circuit. The input voltage of the source of the NMOS transistor M2 of the first inverter is the third voltage V3, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the first voltage V1.

[0072] In some embodiments, the third voltage V3 can be the substrate normal operating voltage, such as ground (0V); the first voltage V1 can be a high voltage, such as VDD (the operating voltage inside the device).

[0073] The drains of the NMOS transistor M3 and the PMOS transistor M4 of the second inverter are connected to the second output terminal 6044. The input voltage of the source of the PMOS transistor M4 of the second inverter is the second voltage V2, and the input voltage of the source of the NMOS transistor M3 of the second inverter is the fourth voltage V4. The fourth voltage V4 is higher than the third voltage V3.

[0074] In some embodiments, the fourth voltage V4 can be the normal operating voltage of the TCP, for example, it can be Vcc (the power supply voltage of the circuit) / 2; the second voltage V2 can be a low voltage, for example, it can be Vss (the common ground voltage of the circuit).

[0075] Reference Figure 6 The input signal 602 sent to the input terminal of the first inverter can be a low-level first input signal, so that the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned off, and the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned on, thereby applying a first voltage V1 to the substrate and a second voltage V2 to the TCP, that is, applying a high voltage difference between the upper and lower plates of each storage capacitor, which can charge the storage capacitor of each storage cell.

[0076] In some embodiments, the input signal 602 sent to the input terminal of the first inverter can also be a high-level second input signal, so that the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned off, and the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned on, thereby applying a third voltage V3 to the substrate and a fourth voltage V4 to the TCP, stopping the charging of the storage capacitor of each memory cell.

[0077] By switching between sending a first input signal and a second input signal to the input terminal of the first inverter, it is possible to switch between applying a first voltage V1 and a third voltage V3 to the substrate, and to switch between applying a second voltage V2 and a fourth voltage V4 to the TCP.

[0078] Figure 7 This is a schematic diagram of another voltage switching circuit according to an exemplary embodiment. Figure 7 The voltage switching circuit shown can be used to... Figure 4 A voltage is applied to the substrate 402 and a voltage is applied to the TCP404 to implement... Figure 5 The method shown.

[0079] like Figure 7As shown, the voltage switching circuit may include a first output terminal 7042 and a second input terminal 7044. The first output terminal 7042 of the voltage switching circuit is electrically connected to the substrate 402, and the second input terminal 7044 is electrically connected to TCP 404. The voltage switching circuit may include a first inverter and a second inverter. The input terminals of the first inverter and the second inverter are connected to receive the input signal 702. The output terminal of the first inverter is the first output terminal 7042, and the output terminal of the second inverter is the second output terminal 7044.

[0080] Both the first inverter and the second inverter can be CMOS transistors. The drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the first output terminal 7042 of the voltage switching circuit. The input voltage of the source of the NMOS transistor M2 of the first inverter is the first voltage V1, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the third voltage V3.

[0081] In some embodiments, the third voltage V3 can be the substrate normal operating voltage, such as ground (0V); the first voltage V1 can be a high voltage, such as VDD (the operating voltage inside the device).

[0082] The drains of the NMOS transistor M3 and the PMOS transistor M4 of the second inverter are connected to the second output terminal 7044. The input voltage of the source of the PMOS transistor M4 of the second inverter is the fourth voltage V4, and the input voltage of the source of the NMOS transistor M3 of the second inverter is the second voltage V2. The fourth voltage V4 is higher than the third voltage V3.

[0083] In some embodiments, the fourth voltage V4 can be the normal operating voltage of the TCP, for example, it can be Vcc (the power supply voltage of the circuit) / 2; the second voltage V2 can be a low voltage, for example, it can be Vss (the common ground voltage of the circuit).

[0084] Reference Figure 7 The input signal 702 sent to the input terminal of the first inverter can be a high-level first input signal, so that the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned on, and the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned off, thereby applying a first voltage V1 to the substrate and applying a second voltage V2 to the TCP, that is, applying a high voltage difference between the upper and lower plates of each storage capacitor, which can charge the storage capacitor of each storage cell.

[0085] In some embodiments, the input signal 702 sent to the input terminal of the first inverter can also be a low-level second input signal, so as to turn on the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter, and turn off the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter, thereby applying a third voltage V3 to the substrate and applying a fourth voltage V4 to the TCP, stopping the charging of the storage capacitor of each memory cell.

[0086] By switching between the first input signal and the second input signal sent to the input terminal of the first inverter, it is possible to switch between applying a first voltage V1 and a third voltage V3 to the substrate, and to switch between applying a second voltage V2 and a fourth voltage V4 to the TCP.

[0087] Figure 8 It is based on Figures 5 to 7 A flowchart of another dynamic random access memory testing method is shown.

[0088] refer to Figure 8 The method 80 provided in this embodiment may include the following steps.

[0089] In step S802, the area size of multiple storage cells is obtained.

[0090] In some embodiments, the area size of the multiple storage cells may be, for example, the product of the number of rows and columns of an array of storage cells.

[0091] In step S804, the voltage difference between the first voltage and the second voltage is determined based on the area size of the multiple memory cells to obtain the first voltage and the second voltage.

[0092] In some embodiments, the region where the memory cell to be aged can be positively correlated with the voltage difference between the first voltage and the second voltage. The larger the region of multiple memory cells, the greater the voltage difference between the first voltage and the second voltage.

[0093] In step S806, a first input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage.

[0094] In some embodiments, it may be used Figure 6 or Figure 7 The voltage switching circuit shown switches between the voltage applied to the substrate and the voltage applied to the TCP. For a detailed implementation, please refer to [reference needed]. Figure 6 and Figure 7 .

[0095] In step S808, after the storage capacitors of each storage cell have been charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and to switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

[0096] In some embodiments, after the storage capacitors of each memory cell have been charged for a predetermined period of time, such as after waiting for a preset number of command clock cycles, the voltage applied to the substrate can be switched from a first voltage to a third voltage by sending a second input signal to the input of the voltage switching circuit, and the voltage applied to the second plate of each storage capacitor can be switched from a second voltage to a fourth voltage, thereby stopping the charging of the storage capacitors of each memory cell.

[0097] In step S810, each memory cell is read to perform an aging test on the dynamic random access memory.

[0098] In some embodiments, after charging the capacitors of the entire memory cell area (i.e., writing "1"), read operations can be performed on each memory cell bit by bit and word by word to perform an aging test on the dynamic random access memory under a preset temperature stress. Specific implementation methods can be found in [reference needed]. Figure 10 .

[0099] Figure 9 It is based on Figure 8 This diagram illustrates a process for writing background data. (Refer to...) Figure 8 The operation in step S806, which switches the voltage applied to the substrate from a third voltage to a first voltage and the voltage applied to the second plates of each storage capacitor from a fourth voltage to a second voltage, can be called entering the design for test (Entry DFT). The operation in step S808, which switches the voltage applied to the substrate from a first voltage to a third voltage and the voltage applied to the second plates of each storage capacitor from a second voltage to a fourth voltage, can be called exiting the design for test (Exit DFT). Figure 9 As shown, using Figure 8 When writing to the background using the method shown, the first and second voltages can be determined using methods S802 and S804, entering the design for testability (S902). After waiting for n DES instructions (S904), the design for testability is exited (S906), and then the charging area of ​​the storage capacitor is changed (S908). After determining the first and second voltages using methods S802 and S804, the process returns to S902. Once all storage capacitors to be aging tested have been fully charged (and there are no more storage capacitor charging areas to be changed), the background writing process ends (S910).

[0100] Reference Figure 1 ,use Figure 1 The method involves writing a background "1" to a memory cell array with X word lines and Y bit lines, requiring n*Y*X DES instructions in writing time. The writing time using the method of this embodiment is Entry DFT + n DES instructions + Exit DFT, and the total time for DFT Entry and Exit is typically no more than 10 tCK, and the writing time is independent of the number of rows and columns in the memory cell array. Therefore, the time to write the background "1" is reduced by (n*Y*X) – (Entry DFT + n + Exit DFT), which significantly shortens the testing time.

[0101] Figure 10 It is based on Figure 8 The diagram illustrates a flow chart of a read operation. For example... Figure 10 As shown, taking the reading of a memory cell connecting X word lines and Y bit lines as an example, the current word line is activated (S1002), and after the word line is activated, "1" is read one bit line at a time (S1004). When reading "1", wait for n DES instructions (S1006) time. Then, after traversing and reading Y bit lines, the current word line is precharged (S1008), and then the activation action of the next word line is entered to traverse X word lines (S1009).

[0102] Can be adopted Figure 1 The method shown writes "1" and uses Figure 10 If the method shown is used to read and test the invalid bit, then use... Figure 5 or Figure 8 The method shown writes "1" and uses Figure 10 The method shown can be used to read and verify whether the failed bits are caused by defects in the wafer itself or by an abnormal Write operation. Therefore Figure 5 and Figure 8 The method provided in the embodiments can also help verify whether the Write operation is abnormal.

[0103] Figure 11 This is a block diagram illustrating a dynamic random access memory (DRAM) testing apparatus according to an exemplary embodiment. Figure 11 The device shown can be applied, for example, to... Figure 3 and Figure 4 The multiple storage units shown.

[0104] refer to Figure 11 The apparatus 110 provided in this embodiment may include a control module 1102 and a test module 1104.

[0105] The control module 1102 can be used to charge the storage capacitor of each storage cell by applying a first voltage on the substrate and a second voltage on the second plate of the storage capacitor of each storage cell, wherein the first voltage is higher than the second voltage.

[0106] The test module 1104 can be used to perform read operations on each memory cell after the storage capacitor of each memory cell has been charged for a predetermined period of time, so as to perform aging tests on the dynamic random access memory.

[0107] Figure 12 This is a block diagram illustrating another dynamic random access memory (DRAM) testing apparatus according to an exemplary embodiment. Figure 12 The device shown can be applied, for example, to... Figure 3 and Figure 4 The multiple storage units shown.

[0108] refer to Figure 12 The apparatus 120 provided in this embodiment may include a control module 1202, a test module 1204, and a determination module 1206.

[0109] The control module 1202 can be used to charge the storage capacitor of each storage cell by applying a first voltage on the substrate and a second voltage on the second plate of the storage capacitor of each storage cell, wherein the first voltage is higher than the second voltage.

[0110] The control module 1202 can also be used to: send a first input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from a third voltage to a first voltage, and switch the voltage applied on the second plate of each storage capacitor from a fourth voltage to a second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

[0111] The control module 1202 can also be used to: send a first input signal to the common input terminal of the first inverter and the second inverter, so as to switch the voltage applied on the substrate from the third voltage to the first voltage through the first inverter, and switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

[0112] The control module 1202 can also be used to: after the storage capacitors of each storage cell have been charged for a predetermined period of time, send a second input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

[0113] The control module 1202 can also be used to: send a second input signal to the common input terminal of the first inverter and the second inverter, so as to switch the voltage applied on the substrate from the first voltage to the third voltage through the first inverter, and switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

[0114] The test module 1204 can be used to perform read operations on each memory cell after the storage capacitor of each memory cell has been charged for a predetermined period of time, so as to perform aging tests on the dynamic random access memory.

[0115] The determining module 1206 can be used to obtain the area size of multiple memory cells; and determine the voltage difference between the first voltage and the second voltage based on the area size of the multiple memory cells to obtain the first voltage and the second voltage.

[0116] The specific implementation of each module in the device provided in this embodiment can be referred to the content of the above method, and will not be repeated here.

[0117] Figure 13 A schematic diagram of the structure of an electronic device according to an embodiment of this disclosure is shown. It should be noted that... Figure 13 The devices shown are merely examples of computer systems and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0118] like Figure 13 As shown, device 1300 includes a central processing unit (CPU) 1301, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1302 or a program loaded from storage portion 1308 into random access memory (RAM) 1303. The RAM 1303 also stores various programs and data required for the operation of device 1300. CPU 1301, ROM 1302, and RAM 1303 are interconnected via bus 1304. Input / output (I / O) interface 1305 is also connected to bus 1304.

[0119] The following components are connected to I / O interface 1305: an input section 1306 including a keyboard, mouse, etc.; an output section 1307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1308 including a hard disk, etc.; and a communication section 1309 including a network interface card such as a LAN card, modem, etc. The communication section 1309 performs communication processing via a network such as the Internet. A drive 1310 is also connected to I / O interface 1305 as needed. Removable media 1311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1310 as needed so that computer programs read from them can be installed into storage section 1308 as needed.

[0120] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1309, and / or installed from removable medium 1311. When the computer program is executed by central processing unit (CPU) 1301, it performs the functions defined above in the system of this disclosure.

[0121] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0122] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0123] The modules described in the embodiments of this disclosure can be implemented in software or hardware. The described modules can also be housed in a processor; for example, a processor may be described as including a data control module and a test module. The names of these modules do not necessarily limit the module itself; for example, a control module may also be described as "a module that sends control signals to a connected circuit."

[0124] In another aspect, this disclosure also provides a computer-readable medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more programs, which, when executed by the device, cause the device to include:

[0125] By applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each storage cell, the storage capacitor of each storage cell is charged, wherein the first voltage is higher than the second voltage; after the storage capacitor of each storage cell has been charged for a predetermined period of time, a read operation is performed on each storage cell to perform an aging test on the dynamic random access memory.

[0126] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A method for testing dynamic random access memory, characterized in that, The dynamic random access memory includes a substrate and multiple memory cells. Each memory cell includes a storage capacitor and a first transistor, wherein the first transistor is an NMOS transistor. The first plate of the storage capacitor of each memory cell is electrically connected to the drain of the corresponding first transistor. The P-type silicon substrate of the first transistor of each memory cell is electrically connected to the substrate. The method includes: By applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each storage cell, the storage capacitor of each storage cell is charged, wherein the first voltage is higher than the second voltage. After the storage capacitors of each storage cell have been charged for a predetermined period of time, a read operation is performed on each storage cell to perform an aging test on the dynamic random access memory. By applying a first voltage to the substrate and a second voltage to the second plates of each storage capacitor, the following steps are included: A first input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage; Wherein, the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

2. The method according to claim 1, characterized in that, The voltage switching circuit includes a first inverter and a second inverter, with the input terminal of the first inverter connected to the input terminal of the second inverter; Sending a first input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from a third voltage to the first voltage, and to switch the voltage applied on the second plates of each storage capacitor from a fourth voltage to the second voltage, includes: The first input signal is sent to the common input terminal of the first inverter and the second inverter to switch the voltage applied on the substrate from the third voltage to the first voltage through the first inverter, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

3. The method according to claim 1, characterized in that, After the storage capacitors of each storage cell have been charged for a predetermined period of time, a read operation is performed on each storage cell, including: After the storage capacitors of each storage cell have been charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and to switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

4. The method according to claim 3, characterized in that, The voltage switching circuit includes a first inverter and a second inverter, and the first inverter and the second inverter share an input terminal. Sending a second input signal to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the first voltage to the third voltage, and to switch the voltage applied on the second plates of each storage capacitor from the second voltage to the fourth voltage, includes: The second input signal is sent to the common input terminal of the first inverter and the second inverter to switch the voltage applied on the substrate from the first voltage to the third voltage through the first inverter, and to switch the voltage applied on the second plate of each storage capacitor from the second voltage to the fourth voltage.

5. The method according to claim 1, characterized in that, Also includes: Obtain the region size of the plurality of storage units; The voltage difference between the first voltage and the second voltage is determined based on the region size of the plurality of memory cells to obtain the first voltage and the second voltage.

6. A dynamic random access memory (DRAM) testing device, characterized in that, The dynamic random access memory (DRAM) includes a substrate and multiple memory cells. Each memory cell includes a storage capacitor and a first transistor, wherein the first transistor is an NMOS transistor. The first plate of the storage capacitor in each memory cell is electrically connected to the drain of the corresponding first transistor. The P-type silicon substrate of the first transistor in each memory cell is electrically connected to the substrate. The device includes: A control module is used to charge the storage capacitor of each memory cell by applying a first voltage on the substrate and a second voltage on the second plate of the storage capacitor of each memory cell, wherein the first voltage is higher than the second voltage. The test module is used to perform read operations on each memory cell after the storage capacitor of each memory cell has been charged for a predetermined period of time, so as to perform aging test on the dynamic random access memory. By applying a first voltage to the substrate and a second voltage to the second plates of each storage capacitor, the following steps are included: A first input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied on the substrate from the third voltage to the first voltage, and to switch the voltage applied on the second plate of each storage capacitor from the fourth voltage to the second voltage; Wherein, the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

7. A dynamic random access memory (DRAM) testing device, characterized in that, This includes the dynamic random access memory under test and the voltage switching circuit, wherein: The dynamic random access memory under test includes a substrate and multiple memory cells. Each memory cell includes a storage capacitor and a first transistor. The first transistor is an NMOS transistor. The first plate of the storage capacitor of each memory cell is electrically connected to the drain of the corresponding first transistor. The P-type silicon substrate of the first transistor of each memory cell is electrically connected to the substrate. The voltage switching circuit includes a first output terminal and a second output terminal. The first output terminal of the voltage switching circuit is electrically connected to the substrate and is used to apply a first voltage to the substrate. The second output terminal of the voltage switching circuit is electrically connected to the second plate of each storage capacitor and is used to apply a second voltage to the second plate of each storage capacitor. The first voltage is higher than the second voltage to charge the storage capacitor of each storage cell. The drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal. The input voltage of the source of the PMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the NMOS transistor of the first inverter is the third voltage. The drains of the NMOS transistor and the PMOS transistor of the second inverter are connected to the second output terminal. The input voltage of the source of the PMOS transistor of the second inverter is the second voltage, and the input voltage of the source of the NMOS transistor of the second inverter is the fourth voltage, which is higher than the third voltage. The input terminals of the first inverter and the second inverter are used to receive a first input signal, so as to turn on the PMOS transistors of the first inverter and the second inverter, and turn off the NMOS transistors of the first inverter and the second inverter.

8. The apparatus according to claim 7, characterized in that, The voltage switching circuit includes a first inverter and a second inverter. The input terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the first inverter is the first output terminal, and the output terminal of the second inverter is the second output terminal.

9. The apparatus according to claim 8, characterized in that, Both the first inverter and the second inverter are CMOS transistors.

10. The apparatus according to claim 7, characterized in that, The input terminals of the first inverter and the second inverter are also used to receive a second input signal, so as to turn off the PMOS transistors of the first inverter and the second inverter, and turn on the NMOS transistors of the first inverter and the second inverter.

11. The apparatus according to claim 9, characterized in that, The drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal. The input voltage of the source of the NMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the PMOS transistor of the first inverter is the third voltage. The drains of the NMOS transistor and the PMOS transistor of the second inverter are connected to the second output terminal. The input voltage of the source of the NMOS transistor of the second inverter is the second voltage, and the input voltage of the source of the PMOS transistor of the second inverter is the fourth voltage, which is higher than the third voltage. The input terminals of the first inverter and the second inverter are used to receive a first input signal, so as to turn on the NMOS transistors of the first inverter and the second inverter, and turn off the PMOS transistors of the first inverter and the second inverter.

12. The apparatus according to claim 11, characterized in that, The input terminals of the first inverter and the second inverter are also used to receive a second input signal, so as to turn off the NMOS transistors of the first inverter and the second inverter, and turn on the PMOS transistors of the first inverter and the second inverter.

13. The apparatus according to claim 7, characterized in that, The first output terminal of the voltage switching circuit is electrically connected to the substrate via a connector plug.

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