A method for fabricating a wide SOA SGT device

Abstract

The application discloses a manufacturing method of a wide SOA SGT device, which can effectively increase the channel length of the SGT device by adjusting the groove width when forming a gate oxide layer and a gate material, and adding an additional doping area formed by diffusion of PSG or BSG material or ion implantation. The SGT device and process disclosed by the application are compatible with the conventional SGT manufacturing process without adding an additional photoetching plate, can effectively increase the channel length of the device without increasing the process difficulty and cost, enhance the thermal instability resistance of the device, obtain a larger safe working area (SOA), and additionally, the additional implantation area can also optimize and adjust the electric field distribution of the device and improve the voltage resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically to a method for manufacturing a wide SOA SGT device. Background Technology

[0002] Insulated-gate field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance, and good frequency response. In various high-stress systems, power MOSFETs are required to have lower conduction losses and the ability to operate for longer periods under high voltage and high current, i.e., high reliability and a large safe operating area (SOA). Shielded-gate MOSFETs (SGT MOSFETs) are widely used in low- and medium-voltage ionization systems due to their excellent specific on-resistance and switching performance. However, the thermal instability of SGTs becomes increasingly prominent due to the increase in channel density and transconductance.

[0003] Studies on the thermal instability of MOSFETs show that the optimization of the thermal instability and SOA (Safe Operating Area) of the device can be considered from two aspects: (1) One direction is to reduce the temperature sensitivity of the threshold voltage, which is mainly achieved by adjusting the bulk concentration and oxide layer thickness; (2) The other direction is to reduce the drain current corresponding to the zero temperature point and reduce the width of the interval where thermal instability occurs, which can be achieved by increasing the channel length and decreasing the channel width.

[0004] To address similar issues, Chinese invention patent (CN116682859B) discloses a multi-channel silicon carbide MOSFET device and its manufacturing method. This silicon carbide MOSFET device includes first and second trenches, a first conductivity type substrate, an epitaxial layer, and a source region, and a second conductivity type well region. The first and second trenches are formed by etching along a direction perpendicular to the xz plane, and the first and second trenches penetrate the active region of the device along the x-direction. A gate dielectric and a gate electrode are formed in the first and second trenches. Under forward conduction conditions, the gate electrode, gate dielectric, and the second conductivity type well region form five channels at different locations, effectively increasing the channel width. This structure increases the channel width by introducing a trench structure, while avoiding the inherent gate dielectric breakdown problem of trench structures. A similar technical solution is also disclosed in Chinese invention patent (CN116525681B). Summary of the Invention

[0005] The purpose of this invention is to provide a manufacturing method for SGT devices suitable for wide SOA, addressing the shortcomings of existing technologies.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for manufacturing a wide SOA SGT device includes forming a substrate, forming an epitaxial layer on the substrate, forming trenches in the epitaxial layer, forming a shielding gate structure, a gate oxide layer, and a gate material in the trenches, forming a moderately doped body region and a heavily doped source region, performing oxidation and passivation on the chip surface, forming a heavily doped body ohmic contact region, and metallizing. The method is characterized by including the following steps during the trench formation and the formation of the gate oxide layer and gate material in the trenches: Step 1: Form several trenches for active and terminal regions on the epitaxial layer, then perform oxidation growth, and then deposit polycrystalline material; Step 2: Etch away excess polycrystalline material from the outside and inside of the trenches in the active region; Step 3: Etch away excess oxide material to form a polycrystalline shielding gate and thick oxide layer structure after the re-etching process; Step 4: Widen the trench width above the shielding gate area to form an additional doped region on the sidewall of the widened trench; Step 5: Form an oxide layer in the trench after the formation of the additional doped region; Step 6: Etch the oxide layer to form an isolation oxide layer between the shielding gate and the control gate; Step 7: Perform sacrificial oxide layer growth and etching on the trench sidewalls to eliminate trench sidewall stress, and then perform gate oxide layer growth. Step 8: Deposit the polycrystalline material of the control gate, etch back the polycrystalline material, and form the gate structure.

[0007] The preferred technical solution of the present invention is as follows: In step 4, impurities in the PSG or BSG can be deposited and filled using PSG or BSG materials, and then diffused into the single crystal material of the trench sidewall through high-temperature annealing to form an additional doped region. Then, the PSG or BSG material is removed to form the additional doped region. Alternatively, the implantation angle can be adjusted to perform tilted implantation of ions of the same conductivity type as the bulk region to form an additional doped region on the trench sidewall.

[0008] Preferably, the substrate is a heavily doped single-crystal material substrate having a second conductivity type.

[0009] Preferably, step 1 includes performing mask material deposition, photoresist exposure, and trench etching over the epitaxial layer to form a plurality of trenches for the active region and the terminal region.

[0010] Preferably, the top mask material is retained, and PSG or BSG material is selected for deposition and filling according to the difference between P-type and N-type conductivity. Then, the impurities in PSG or BSG are diffused into the single crystal material of the trench sidewall through high-temperature annealing to form an additional doped region. After the additional doped region is formed, the mask material is removed.

[0011] Preferably, ion implantation and push-junction of the body and source regions can be performed using masking or self-alignment processes to form a moderately doped body region and a heavily doped source region.

[0012] Preferably, after oxidation and passivation of the chip surface, photolithographic contact holes are formed thereon, followed by ohmic doping and annealing to form a heavily doped bulk ohmic contact region.

[0013] Preferably, the metallization includes depositing a metal layer on the surface oxide layer, performing photolithography to form a top layer metal, including source PAD metal and gate PAD metal; and performing substrate thinning and back metal deposition on the back side to form a drain metal.

[0014] Preferably, the process sequence for fabricating the body region can be selectively changed, with the body region being implanted and pushed together before the trench is formed in the epitaxial layer, and the moderately doped body region being formed before the trench is etched.

[0015] As a preferred embodiment, the thickness of the insulating dielectric layer 5 surrounding the shielding gate region 4 can be adjusted according to the withstand voltage level of the device to ensure that the insulating dielectric layer 5 will not break down.

[0016] As a preferred embodiment, the width of the control gate trench is greater than the width of the shielding gate trench, and the width difference between the two can be adjusted according to the device size and process capability.

[0017] As a preferred embodiment, the impurity concentration of the BSG or PSG material can be adjusted according to the threshold voltage requirement.

[0018] As a preferred embodiment, the control gate structure includes a bottom depth of the control gate region 6 that reaches or exceeds the depth of the additional doped region 7 of the moderately doped first type of conductivity semiconductor, ensuring that the device can conduct normally.

[0019] As a preferred embodiment, the SGT device is made of silicon, silicon carbide, gallium arsenide, indium phosphide, gallium oxide, or germanium-silicon semiconductor material.

[0020] As a preferred embodiment, the first type of conductivity semiconductor is doped with a P-type semiconductor and the second type of conductivity semiconductor is doped with an N-type semiconductor; or the first type of conductivity semiconductor is doped with an N-type semiconductor and the second type of conductivity semiconductor is doped with a P-type semiconductor.

[0021] As a preferred embodiment, the light doping is on the order of 1e. 16 cm -3 Medium doping refers to impurity concentrations on the order of 1e. 16 cm -3 To 1e 18 cm -3 The heavy doping refers to the impurity concentration on the order of 1e. 18 cm -3 Doping.

[0022] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows: SGT devices manufactured using this method can form additional doped regions without increasing process difficulty and cost, requiring only additional single-crystal etching, impurity deposition and diffusion, or impurity ion implantation. These regions can form an inversion layer when the device is forward-conducting, effectively increasing the channel length of the device, enhancing the device's resistance to thermal instability and SOA. In addition, the additional implanted regions can also optimize and adjust the electric field distribution of the device, improving the device's breakdown voltage. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a semiconductor element structure according to an embodiment of the present invention.

[0024] Figures 2 to 16 for Figure 1 The diagram shows the structure of the component in different processing steps.

[0025] Figure 17 This is a schematic diagram of the semiconductor in the implantation state in Embodiment 3 of the present invention.

[0026] Figure 18 This is a schematic diagram of the semiconductor in the implantation state in another embodiment of the present invention.

[0027] Figure 19 yes Figure 18 A schematic diagram of the semiconductor structure in the illustrated embodiment.

[0028] In the diagram, the markings are as follows: 1 is the drain metal layer, 2 is the drain region of the heavily doped Type II conductivity semiconductor, 3 is the drift region of the lightly doped Type II conductivity semiconductor, 4 is the shielding gate region, 5 is the insulating dielectric layer, 6 is the control gate region, 7 is the tilted injection region of the moderately doped Type I conductivity semiconductor, 8 is the body region of the moderately doped Type I conductivity semiconductor, 9 is the source region of the heavily doped Type II conductivity semiconductor, 10 is the ohmic contact region of the doped Type I conductivity semiconductor, 11 is the top insulating dielectric layer, and 12 is the source metal layer. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings.

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] Example 1 A wide SOA SGT device, such as Figure 1As shown, the structure includes a source structure, a control gate structure, a shielding gate structure, a drift region structure, and a drain structure: the source structure includes a source metal layer 12, a heavily doped first-type conductivity type semiconductor ohmic contact region 10, a heavily doped second-type conductivity type semiconductor source region 9, a moderately doped first-type conductivity type semiconductor body region 8, and a moderately doped first-type conductivity type semiconductor additional doped region 7; the control gate structure includes a control gate region 6 and a thin insulating dielectric layer 5 on its sides; the shielding gate structure includes a shielding gate region 4 and a thick insulating dielectric layer 5 surrounding the region 4; the drift region structure includes a lightly doped second-type conductivity type semiconductor drift region 3; and the drain structure includes a heavily doped second-type conductivity type semiconductor drain region 2 and a drain metal layer 1. One side of the heavily doped second-type conductivity type semiconductor source region 9 of the source structure is a heavily doped first-type conductivity type semiconductor ohmic contact region 10, and the other side is a control gate structure. The upper side is a source metal layer 12, and the lower side is a moderately doped first-type conductivity type semiconductor body region 8. A moderately doped first-type conductivity type semiconductor additional doped region 7 is located on the side of the body region 8 closest to and below the control gate region 6. The control gate region 6 of the control gate structure is located below the source metal layer 12 and on the side of the moderately doped first-type conductivity type semiconductor body region 8. The control gate region 6 and the source metal layer 12 are separated by a thick insulating dielectric layer 11. The type semiconductor body region 8 is separated by a thin insulating dielectric layer 5; the shielding gate region 4 of the shielding gate structure is located below the control gate region 6 and extends into the range of the lightly doped second type conductivity type semiconductor drift region 3, and the shielding gate region 4 is isolated from the control gate region 6 and the lightly doped second type conductivity type semiconductor drift region 3 by the thick insulating dielectric layer 5; the lightly doped second type conductivity type semiconductor drift region 3 of the drift region structure is located below the medium-doped first type conductivity type semiconductor body region 8; the heavily doped second type conductivity type semiconductor drain region 2 of the drain structure is located below the drift region 3, and the lower surface of the heavily doped second type conductivity type semiconductor drain region 2 is in direct contact with the drain metal layer 1. This SGT device creates a difference in the lateral dimension of the control gate by widening the control gate on both sides. The channel is formed between the control gate and the medium-doped Type I conductivity semiconductor body region. Further doping in the additional doped region can also provide conditions for channel formation, thereby effectively increasing the channel length of the device, reducing the width of the thermal instability range, reducing the drain current corresponding to the zero temperature point, improving thermal stability, and achieving a larger safe operating area (SOA).

[0032] The specific manufacturing method of the SGT device with this structure is as follows: Step 1: Select a heavily doped single-crystal material substrate with a second conductivity type, and grow a single-crystal material epitaxial layer on the substrate, such as... Figure 2 As shown; Step 2: Mask material deposition, photoresist exposure, and trench etching are performed above the epitaxial layer to form several trenches in the active and terminal regions. Then, oxide layer growth is performed, followed by polycrystalline material deposition, such as... Figure 3 As shown; Step 3: Etch to remove excess polycrystalline material from the outside and inside of the trenches in the active region, such as... Figure 4 As shown; Step 4: Etch away excess oxide material to form the polycrystalline shielding gate and thick oxide layer structure after the etch-back process, such as... Figure 5 As shown; Step 5: Retain the top mask material and directly etch the single crystal material to widen the trench width above the shielding gate area, such as... Figure 6 As shown; Step 6: Retain the top mask material. Based on the difference between P-type and N-type conductivity, select PSG or BSG material for deposition and filling. Then, use high-temperature annealing to diffuse impurities within the PSG or BSG into the single-crystal material of the trench sidewalls, forming additional doped regions. Figure 7 As shown; Step 7: Remove the masking material and PSG or BSG material, such as Figure 8 As shown; Step 8: Thermal oxidation growth and deposition of oxide layer, such as Figure 9 As shown; Step 9: Etch the oxide layer to form an isolation oxide layer between the shielding gate and the control gate, such as... Figure 10 As shown; Step 10: Perform sacrificial oxide layer growth and etching on the trench sidewalls to eliminate trench sidewall stress, and then perform gate oxide layer growth, such as... Figure 11 As shown; Step 11: Deposit the polycrystalline material for the control gate, etch back the polycrystalline material to form the gate structure, such as... Figure 12 As shown; Step 12: Ion implantation and push-bonding are performed on the body and source regions using masking or self-aligned processes to form moderately doped body regions and heavily doped source regions, such as... Figure 13 As shown; Step 13: Perform oxidation and passivation on the chip surface, such as... Figure 14 As shown; Step 14: Photolithographically etch contact holes, perform ohmic doping and annealing to form heavily doped bulk ohmic contact regions, such as... Figure 15 As shown; Step 15: Perform metallization by depositing a metal layer on the surface oxide layer and performing photolithography to form the top layer metal, including the source PAD metal and the gate PAD metal; perform substrate thinning and back metal deposition on the back side to form the drain metal, such as... Figure 16 As shown.

[0033] In this embodiment, the thickness of the insulating dielectric layer 5 surrounding the shielding gate region 4 can be adjusted according to the withstand voltage level of the device to ensure that the insulating dielectric layer 5 will not break down; the width of the control gate trench is greater than the width of the shielding gate trench, and the width difference between the two can be adjusted according to the device size and process capability; the impurity concentration of the BSG or PSG material can be adjusted according to the threshold voltage requirement; the control gate structure includes a bottom depth of the control gate region 6 that reaches or exceeds the depth of the moderately doped first type of conductivity semiconductor tilted injection region 7 to ensure that the device can conduct normally; the material of the VDMOS device is silicon, silicon carbide, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon semiconductor material; the first type of conductivity semiconductor is doped with a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor; or the first type of conductivity semiconductor is doped with an N-type semiconductor and the second type of conductivity semiconductor is a P-type semiconductor; the light doping is an impurity concentration on the order of 1e 16 cm -3 Medium doping refers to impurity concentrations on the order of 1e. 16 cm -3 to 1e 18 cm -3 The heavy doping refers to the impurity concentration being on the order of 1e. 18 cm -3 Doping.

[0034] The working principle of the present invention will be explained in detail below with reference to Embodiment 1 (taking an N-type SGT as an example): In the forward conduction state, the electrode connection method in Example 1 is as follows: the source metal layer 12 and the shielding gate region are connected to a low potential, the control gate region 6 is connected to a high potential, and the drain metal layer 1 is connected to a high potential. At this time, the moderately doped type I conductivity semiconductor tilted injection region 7 can effectively increase the channel length of the device, thereby enhancing the device's resistance to thermal instability and increasing the device's SOA.

[0035] In the reverse blocking state, the electrode connection method in Example 1 is as follows: the source metal layer 12 and the shielding gate region are connected to a low potential, the control gate region 6 is connected to a low potential, and the drain metal layer 1 is connected to a high potential. At this time, the moderately doped type I conductivity semiconductor tilted injection region 7 can introduce a new electric field peak at the midpoint between the original Body / EPI electric field peak and the electric field peak at the bottom of the shielding gate trench, enhancing the two-dimensional electric field adjustment effect of the device and increasing the breakdown voltage of the device.

[0036] Example 2 This method is similar to that of Example 1, except that the order of the body region and trench etching processes is adjusted, as follows: Step 1: Select a heavily doped single-crystal silicon substrate with a second conductivity type, and grow a single-crystal silicon epitaxial layer on the substrate; Step 2: Perform body region implantation and push-in to form a moderately doped body region before trench etching; Step 3: Perform mask material deposition, photoresist exposure, and trench etching on the epitaxial layer to form several trenches in the active and terminal regions. Then, perform oxide layer growth and polycrystalline material deposition. Step 4: Etch away excess polycrystalline material from the outside and inside of the trenches in the active region; Step 5: Etch away excess oxide material to form a polycrystalline shielding gate and thick oxide layer structure after the re-etching process; Step 6: Retain the top mask material and directly etch the single crystal material to widen the trench width above the shielding gate area; Step 7: Retain the top mask material. Based on the difference between P-type and N-type conductivity, select PSG or BSG material for deposition and filling. Then, use high-temperature annealing to diffuse the impurities in the PSG or BSG into the single-crystal material of the trench sidewalls, forming additional doped regions. Step 8: Remove the masking material and PSG or BSG material; Step 9: Thermal oxidation growth and deposition of oxide layer; Step 10: Etch the oxide layer to form an isolation oxide layer between the shielding gate and the control gate; Step 11: Perform sacrificial oxide layer growth and etching on the trench sidewalls to eliminate trench sidewall stress, and then perform gate oxide layer growth; Step 12: Deposit the polycrystalline material of the control gate, etch back the polycrystalline material, and form the gate structure; Step 13: Ion implantation and push-bonding of the body and source regions are performed using masking or self-aligned processes to form heavily doped source regions; Step 14: Perform oxidation and passivation on the chip surface; Step 15: Photolithographically create contact holes, perform ohmic doping and annealing to form heavily doped bulk ohmic contact regions; Step 16: Perform metallization by depositing a metal layer on the surface oxide layer and performing photolithography to form the top layer metal, including the source PAD metal and the gate PAD metal; perform substrate thinning and back metal deposition on the back side to form the drain metal.

[0037] Example 3 Step 1: Select a heavily doped single-crystal material substrate with a second conductivity type, and grow a single-crystal material epitaxial layer on the substrate; Step 2: Mask material deposition, photoresist exposure, and trench etching are performed on the epitaxial layer to form several trenches in the active and terminal regions. Then, oxide layer growth is performed, followed by polycrystalline material deposition. Step 3: Etch away excess polycrystalline material from the outside and inside of the trenches in the active region; Step 4: Etch away excess oxide material to form a polycrystalline shielding gate and thick oxide layer structure after the re-etching process; Step 5: Retain the top mask material and directly etch the single crystal material to widen the trench width above the shielding gate area; Step 6: Adjust the implantation angle and perform tilted implantation of impurities with the same conductivity type as the body to form an additional doped region on the trench sidewall, such as... Figure 17 As shown; Step 7: Thermal oxidation growth and deposition of oxide layer; Step 8: Etch the oxide layer to form an isolation oxide layer between the shielding gate and the control gate; Step 9: Perform sacrificial oxide layer growth and etching on the trench sidewalls to eliminate trench sidewall stress, and then perform gate oxide layer growth; Step 10: Deposit the polycrystalline material of the control gate, etch back the polycrystalline material, and form the gate structure; Step 11: Ion implantation and push-junction of the body and source regions are performed using masking or self-aligned processes to form a moderately doped body region and a heavily doped source region. Step 12: Perform oxidation and passivation on the chip surface; Step 13: Photolithographically etch contact holes, perform ohmic doping and annealing to form heavily doped bulk ohmic contact regions; Step 14: Perform metallization by depositing a metal layer on the surface oxide layer and performing photolithography to form the top layer metal, including the source PAD metal and the gate PAD metal; perform substrate thinning and back metal deposition on the back side to form the drain metal.

[0038] Example 4 The structure of this embodiment 2 is as follows: Figure 18 and Figure 19 As shown, after etching back the thick oxide layer on the shielding gate and its sides and etching Si, the tilting injection angles on the left and right sides are adjusted to be different, as follows: Figure 18 As shown, the additional doped region 7 of the moderately doped first-type conductivity type semiconductor on one side is connected to the mediumly doped first-type conductivity type semiconductor body region 8, while the additional doped region 7 of the moderately doped first-type conductivity type semiconductor on the other side is disconnected from the mediumly doped first-type conductivity type semiconductor body region 8. The final structure is as follows. Figure 19 As shown, it can make trade-offs between on-resistance and thermal instability resistance based on the actual application environment while ensuring optimized withstand voltage.

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a wide SOA SGT device, comprising forming a substrate, forming an epitaxial layer on the substrate, forming trenches in the epitaxial layer, forming a shielding gate structure, a gate oxide layer, and a gate material in the trenches, forming a moderately doped body region and a heavily doped source region, performing oxidation and passivation on the chip surface, forming a heavily doped body ohmic contact region, and metallizing, characterized in that, The process of forming the trench and forming the gate oxide layer and gate material in the trench includes the following steps: Step 1: Form several trenches for active and terminal regions on the epitaxial layer, then perform oxidation growth, and then deposit polycrystalline material; Step 2: Etch away excess polycrystalline material from the outside and inside of the trenches in the active region; Step 3: Etch away excess oxide material to form a polycrystalline shielding gate and thick oxide layer structure after the re-etching process; Step 4: Widen the trench width above the shielding gate area to form an additional doped region on the sidewall of the widened trench; Step 5: Form an oxide layer in the trench after the formation of the additional doped region; Step 6: Etch the oxide layer to form an isolation oxide layer between the shielding gate and the control gate; Step 7: Perform sacrificial oxide layer growth and etching on the trench sidewalls to eliminate trench sidewall stress, and then perform gate oxide layer growth; Step 8: Deposit the polycrystalline material of the control gate, etch back the polycrystalline material, and form the gate structure.

2. The method for manufacturing a wide SOA SGT device according to claim 1, characterized in that, The substrate is a heavily doped single-crystal material substrate with a second conductivity type. Step 1 includes performing mask material deposition, photoresist exposure, and trench etching over the epitaxial layer to form a number of trenches for the active region and the terminal region.

3. The method for manufacturing a wide SOA SGT device according to claim 2, characterized in that, The top mask material is retained. Based on the difference between P-type and N-type conductivity, PSG or BSG material is selected for deposition and filling. Then, impurities in PSG or BSG are diffused into the single crystal material of the trench sidewall through high-temperature annealing to form an additional doped region. After the additional doped region is formed, the mask material is removed.

4. The method for manufacturing a wide SOA SGT device according to claim 3, characterized in that, Ion implantation and push-junction of the body and source regions can be performed using masking or self-aligned processes to form moderately doped body regions and heavily doped source regions.

5. The method for manufacturing a wide SOA SGT device according to claim 4, characterized in that, After oxidation and passivation of the chip surface, photolithographic contact holes are formed on it, followed by ohmic doping and annealing to form a heavily doped bulk ohmic contact region.

6. The method for manufacturing a wide SOA SGT device according to claim 5, characterized in that, The control gate structure includes a bottom depth of the control gate region that reaches or exceeds the depth of the additional doped region 7 of the moderately doped Type I conductivity semiconductor.

7. The method for manufacturing a wide SOA SGT device according to claim 1, characterized in that, In step 4, the implantation angle is adjusted to perform tilted implantation of impurities with the same conductivity type as the body region, forming an additional doped region on the trench sidewall.

8. The method for manufacturing a wide SOA SGT device according to claim 5, characterized in that, Light doping refers to impurity concentrations on the order of 1e. 16 cm -3 Medium doping refers to impurity concentrations on the order of 1e. 16 cm -3 to 1e 18 cm -3 The heavy doping refers to the impurity concentration being on the order of 1e. 18 cm -3 Doping.

9. The method for manufacturing a wide SOA SGT device according to claim 1, characterized in that, In step 4, PSG or BSG material is used for deposition and filling. Then, high-temperature annealing diffusion is used to diffuse the impurities in PSG or BSG into the single crystal material of the trench sidewall to form the additional doped region. Then, the PSG or BSG material is removed.

10. The method for manufacturing a wide SOA SGT device according to claim 1, characterized in that, Before forming trenches in the epitaxial layer, body region implantation and push-bonding are performed to form the moderately doped body region before trench etching.

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