A high-speed electroabsorption modulator laser chip and a preparation method thereof

Abstract

This invention relates to a high-speed electroabsorption modulated laser chip and its fabrication method, comprising a DFB laser and an EA modulator. A groove is etched at one end of the DFB laser, and the EA modulator is epitaxially grown within the groove. The EA modulator includes a buffer layer, an EA active region, an InP layer, a primary buried structure, and a secondary buried structure. The EA active region corresponds to the DFB active region. The primary buried structure includes a current blocking layer and first trenches on both sides of the EA active region, forming a ridge waveguide structure between the two first trenches. The current blocking layer is disposed within the first trenches, and the EA active region is buried between two semi-insulating InP current blocking layers. The secondary buried structure includes a low-dielectric-constant filling film and second trenches respectively constructed outside the current blocking layers. The bottom of the second trenches is lower than the first trenches, and a deep ridge waveguide structure is formed between the two second trenches. The filling film is disposed within the first trenches and buries the current blocking layer. This invention can effectively improve the response frequency and reliability of the EML laser chip.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, specifically to a high-speed electroabsorption modulation laser chip and its fabrication method. Background Technology

[0002] With the widespread application and popularization of 5G communication, people's demand for high-speed network transmission is becoming increasingly urgent. Currently, low-speed chips such as 2.5G / 10G / 25G generally use direct modulation (DML) structures. This structure has high optical output characteristics, relatively good single-mode output characteristics, and relatively stable side-mode suppression ratio. Moreover, its epitaxial design and fabrication process are relatively simple, making it easier to achieve mass production. However, under different temperature and current conditions, the refractive index of the active region of this structure will change, resulting in wavelength drift (chirp) and dispersion under different conditions, which is a more serious problem, especially in long-distance propagation. In addition, under high current modulation, DML lasers are more likely to reach saturation, making it difficult for DML devices to achieve high extinction ratios and high bandwidths.

[0003] Electro-absorption modulated lasers (EML lasers) consist of a distributed feedback laser (DFB laser) and an electro-absorption modulator (EA modulator, EA device), and are the preferred structure for high-speed chips above 53 GHz. The DFB laser operates under constant pump current conditions, which avoids lasing wavelength drift (chirping) caused by current variations. The EA device operates under low reverse bias conditions, and its main function is to modulate the continuous optical signal of the DFB laser, further reducing lasing wavelength drift (chirping) and significantly increasing the transmission distance of the EML laser.

[0004] The modulation rate of EML lasers is primarily limited by parasitic capacitance, which includes the junction capacitance of the EA device and the plate capacitance of the electrodes. This parasitic capacitance can be optimized using the EA device. However, in existing EML laser chips, the active region is typically exposed to air. The Al-containing material in the active region is highly susceptible to oxidation. Under normal operating conditions, this oxidation can trap charge carriers and cause nonradiative recombination, significantly impacting device performance and posing a high risk of reliability failure over long-term operation. For example, Chinese patent CN 116111452 A discloses an EML laser fabrication method using a ridge waveguide. While this avoids secondary epitaxial processes, the direct contact between the aluminum (Al) material and SiO2 in this method poses a risk of oxidation of the Al-containing elements in the active region, affecting device reliability and creating potential reliability issues. Furthermore, the response frequency of existing EML laser chips still needs improvement, which is not conducive to realizing high-speed EML laser chips. For example, in an EML laser fabrication method provided by Chinese patent CN 106785916 A, the far-field divergence angle characteristics of the EML laser chip are improved, and the coupling efficiency of the emitted light is increased. However, this results in a large parasitic planar capacitance in the device itself, which is not conducive to improving the response frequency of the EML laser chip. Therefore, how to improve the response frequency of EML devices while solving the device reliability problem is an urgent issue for the industry. Summary of the Invention

[0005] The first aspect of this invention addresses the problem of improving the response frequency and reliability of EML laser chips by providing a high-speed electro-absorption modulation laser chip. This chip reduces the device's junction capacitance, further increasing the response frequency, and effectively avoids the risk of oxidation, thus improving device reliability. The main concept is as follows:

[0006] A high-speed electro-absorption modulated laser chip includes a DFB laser and an EA modulator, wherein the DFB laser and the EA modulator are grown on the same substrate via an epitaxial bonding process.

[0007] A DFB laser includes a DFB active region, and one end of the DFB laser has a groove. An EA modulator is grown in the groove and is connected to the DFB laser.

[0008] The EA modulator includes a primary buried structure, a secondary buried structure, and a buffer layer, an EA active region, and an InP layer arranged from bottom to top. The EA active region corresponds to the DFB active region. The primary buried structure includes a current blocking layer and first trenches respectively constructed on both sides of the EA active region. A ridge waveguide structure is formed between the two first trenches. The current blocking layer is respectively disposed in the first trenches. The EA active region is buried between the two current blocking layers. The secondary buried structure includes a filling film layer and second trenches respectively constructed on the outside of the current blocking layer. The filling film layer is made of a low dielectric constant material. The bottom of the second trench is lower than the first trench. A deep ridge waveguide structure is formed between the two second trenches. The filling film layer is respectively disposed in the first trenches and buries the current blocking layer. In this scheme, by configuring a primary burial structure to bury the active region (EA), the EA active region can be effectively prevented from being exposed to air, providing better protection, avoiding the risk of oxidation, and improving device reliability. By configuring a secondary burial structure and incorporating a second trench within it, with the bottom of the second trench lower than the first trench, a deep ridge waveguide structure can be formed between the two second trenches. This effectively reduces the photon lifetime of the EA active region, improving the response characteristics of the EA device. Simultaneously, by using a low-dielectric-constant filling layer, the parasitic capacitance of the EA device can be effectively reduced using the secondary burial structure, further improving the device's response frequency. In this scheme, the synergistic structure of the EA active region, the primary burial structure, and the secondary burial structure not only reduces the device's parasitic capacitance and further improves the device's response frequency, but also effectively avoids the risk of oxidation, improving device reliability. This better meets the high-performance and high-reliability requirements of 53GHz and above high-speed electro-absorption modulation laser chips.

[0009] To further improve chip reliability, in the primary buried structure, the current blocking layer is made of semi-insulating InP material. The width of the current blocking layer along the direction away from the EA active region is 2μm to 5μm, thus forming a semi-insulating buried structure. In this solution, by using semi-insulating InP material to form the current blocking layer and reasonably controlling the width of the current blocking layer, the primary buried structure can achieve a semi-insulating buried structure. In practice, this not only effectively buries the EA active region, preventing it from being exposed to air and oxidized, thus providing better protection, but also forms a high-resistivity current blocking layer to effectively limit the current and optical field of the EA modulator, thereby providing interface passivation protection for the EA modulator and further improving chip reliability. Furthermore, setting the width of the current blocking layer to 2μm to 5μm achieves even better results.

[0010] Preferably, the semi-insulating InP material includes iron-doped InP material or rubidium-doped InP material. In particular, the use of rubidium-doped InP material can achieve better results and further improve reliability.

[0011] Preferably, the width of the current blocking layer along the direction away from the EA active region is 2μm to 3μm. This helps to further improve reliability.

[0012] Preferably, the width of the current blocking layer along the direction away from the EA active region is 2μm, 2.2μm, 2.5μm, 2.7μm, 2.8μm, or 3μm.

[0013] Preferably, the bottom of the first trench is lower than the bottom of the EA active region, and the thickness of the current blocking layer is greater than the thickness of the EA active region. This allows the current blocking layer to effectively shield the sides of the EA active region, providing better protection.

[0014] Preferably, the bottom end of the EA active region is flush with or lower than the bottom end of the DFB active region, and the top end of the EA active region is higher than the top end of the DFB active region. This can effectively reduce light loss at the docking position and help achieve better results.

[0015] Preferably, the width of the ridge waveguide structure is 0.3μm to 2.5μm.

[0016] Furthermore, the top of the current blocking layer is lower than the top of the ridge waveguide structure. This allows the filling film layer to not only fill the outer surface of the current blocking layer but also the top of the current blocking layer, thereby achieving a more comprehensive burial of the current blocking layer and resulting in better performance.

[0017] To further improve stability, the active region of the DFB is made of indium gallium arsenide phosphide (IGaAs). In existing technologies, the active region of the DFB uses AlQ material. Al in AlQ is highly reactive and readily reacts with water and oxygen in the air to form an aluminum oxide film, which is difficult to remove. However, during the fabrication of this laser chip, after the groove etching is completed, the DFB active region is directly exposed to the air. Using IGaAs avoids the introduction of Al, resulting in a more stable interface and thus further improving the chip's stability.

[0018] Furthermore, the active region EA is made of indium gallium aluminum arsenide (AlQ) material. In this scheme, by using AlQ material in the quantum well structure of the active region EA, compared with using PQ material, the distribution ratio of ΔEg on ΔEc / ΔEv is larger. The lower ΔEv has the advantage of improving hole mobility, which can effectively improve the extinction ratio output performance and response frequency of the device.

[0019] Furthermore, the filling film layer is made of polyimide or benzocyclobutene. On the one hand, polyimide and benzocyclobutene have lower dielectric constants, which can effectively reduce the parasitic capacitance of the EA device. On the other hand, they can achieve smaller electrode planar capacitance, thereby further improving the device response frequency.

[0020] Preferably, the DFB laser further includes, from bottom to top: an InP buffer layer, a PQ etch stop layer, an InP space layer, a PQ grating layer, a grating buried layer, an InP cladding layer, a PQ material transition layer, and an InGaAs ohmic contact layer grown on the substrate, wherein the DFB active region is located between the PQ etch stop layer and the PQ grating layer.

[0021] Preferably, the EA modulator further includes, from bottom to top: an InP buffer layer, an InP capping layer, an InP cladding layer, a PQ material transition layer, and an InGaAs ohmic contact layer, wherein the EA active region is located between the InP buffer layer and the InP capping layer.

[0022] Preferably, the lower end of the groove is located in the InP buffer layer of the DFB laser, and the lower ends of the first groove and the second groove are respectively located in the InP buffer layer of the EA modulator.

[0023] Furthermore, the top of the DFB laser has two parallel third trenches, forming a DFB ridge waveguide structure between them. The bottom of the third trenches is higher than the DFB active region, and the mesa width of the DFB ridge waveguide structure is the same as the mesa width of the ridge waveguide structure in the EA modulator. This can effectively reduce the subsequent SiO / SiN film and P-type electrode processing steps.

[0024] Furthermore, a fourth groove is constructed on the top of the DFB laser. The fourth groove is located between the DFB laser and the EA modulator. The fourth groove is perpendicular to the third groove, and the bottom of the fourth groove is higher than the bottom of the third groove. The fourth groove is used to form an isolation area between the DFB laser and the EA modulator, which can effectively avoid the problem of current crosstalk when the two devices are working.

[0025] The second aspect of this invention addresses the problem of fabricating the aforementioned high-speed electroabsorption modulated laser chip by providing a method for fabricating such a chip, comprising the following steps:

[0026] Step S1: A primary epitaxial structure is grown on the substrate to obtain the substrate wafer of the DFB laser. The primary epitaxial structure includes, from bottom to top: an InP buffer layer, a PQ etch stop layer, a DFB active region, an InP space layer, and a PQ grating layer grown on the substrate.

[0027] Step S2: Prepare the PQ grating layer.

[0028] Step S3: Deposit and grow a grating fill layer on the grating layer to fill the grating in the grating layer.

[0029] Step S4: Etch a groove for selective growth of the EA modulator, the groove being etched down to the InP buffer layer, and use one sidewall of the groove as a docking growth surface adapted to the DFB laser.

[0030] Preferably, in step 4, the groove is a cuboid structure.

[0031] Preferably, in step 4, the width of the groove is 120μm to 160μm. That is, the width of the mating growth surface is 120μm to 160μm.

[0032] Step S5: Clean the surface of the substrate wafer to remove residual organic matter and oxide film.

[0033] Step S6, growing a secondary epitaxial structure in the groove, includes growing an InP buffer layer at the bottom of the groove, depositing an EA active region on the InP buffer layer, and growing an InP capping layer above the EA active region, wherein the EA active region is connected to the DFB active region through a mating growth surface.

[0034] Preferably, in step S6, the thickness of the EA active region is greater than the thickness of the DFB active region, the bottom of the EA active region is lower than or flush with the bottom of the DFB active region, and the top of the EA active region is higher than the top of the DFB active region. This can effectively reduce light loss on the docking growth surface.

[0035] Preferably, in step S6, the upper end of the InP capping layer is flush with the upper end of the grating filling layer to facilitate subsequent fabrication processes.

[0036] Step S7 involves growing a three-stage epitaxial structure, including growing an InP cladding layer on the DFB substrate wafer, growing a PQ material transition layer on the InP cladding layer, and growing an InGaAs ohmic contact layer on the PQ material transition layer.

[0037] Step S8, forming the first trench of the primary buried structure, includes etching two parallel first trenches in the groove using an etching process, etching the first trenches to the InP buffer layer of the secondary epitaxial structure, the two first trenches being connected to the docking growth surface respectively, and the two first trenches being perpendicular to the docking growth surface respectively, and forming a straight ridge waveguide structure between the two first trenches.

[0038] Preferably, in step S8, the sum of the mesa width of the ridge waveguide structure and the widths of the two first trenches is equal to the width of the groove. This improves wafer utilization and facilitates subsequent fabrication processes. Furthermore, with a fixed mesa width, a wider first trench can be obtained, allowing for the subsequent fabrication of a wider current blocking layer. This not only meets the configuration requirements of current blocking layers with different widths but also allows for precise control of the final width of the current blocking layer in subsequent processes.

[0039] Preferably, in step S8, the two first grooves have the same width, and the two first grooves in the groove are arranged symmetrically.

[0040] Preferably, in step S8, the mesa width of the ridge waveguide structure is configured to be 0.3 μm to 2.5 μm, and the etching depth of the first trench is 3 μm to 3.5 μm. Controlling the mesa width of the ridge waveguide structure can effectively control the width of the EA active region, thereby effectively reducing the junction capacitance of the EA active region and further improving the device response frequency.

[0041] Step S9, forming a primary buried structure of the current blocking layer, includes depositing and growing a current blocking layer in two first trenches using an MOCVD process. The upper end of the current blocking layer is higher than the upper end of the EA active region. The EA active region is buried by the current blocking layer to form a primary buried structure of the EA active region. The current blocking layer is made of semi-insulating InP material.

[0042] Preferably, the thickness of the current blocking layer is 0.5 μm to 2 μm, in order to better isolate and bury the active region EA.

[0043] Preferably, the semi-insulating InP material includes iron-doped InP material or rubidium-doped InP material.

[0044] Step S10: Within the groove area, an etching process is used to etch downwards along the outer ends of the two current blocking layers respectively, forming two parallel second trenches. The etching also reduces the width of the current blocking layers to meet the design requirements.

[0045] The lower end of the second trench is lower than the lower end of the first trench. The two second trenches are perpendicular to the mating growth surface, forming a deep ridge waveguide structure with a secondary buried structure between them. In this scheme, since the width of the current blocking layer generated in step S9 is greater than the designed width of the current blocking layer, this step can not only precisely adjust and change the width of the current blocking layer to achieve the designed width, so that it can play a better role in the primary buried structure and further improve the response frequency of the device, but also prepare current blocking layers of different widths according to actual needs to meet the requirements of different occasions. On the other hand, a deep ridge waveguide structure can be formed between the two second trenches to effectively reduce the photon lifetime of the EA active region and improve the response characteristics of the EA device. In addition, when preparing the deep ridge waveguide structure, by etching the current blocking layer, the thickness of the current blocking layer on both sides of the ridge waveguide structure mesa can be reduced as much as possible while ensuring the resistance of the current blocking layer is on the order of GΩ, so as to further reduce the parasitic capacitance of the EA modulator itself, thereby improving the overall response frequency of the EML device.

[0046] Preferably, in step S10, the maximum width between the two second trenches is equal to the width of the groove. This not only improves wafer utilization but also facilitates subsequent fabrication processes.

[0047] Preferably, in step S10, after etching, the width of the current blocking layer on both sides of the ridge waveguide along the direction away from the EA active region is 2μm~5μm, more preferably 2μm~3μm.

[0048] Preferably, in step S10, the etching depth is 3.5 μm to 10 μm.

[0049] Step S11: Fill the first trench and the second trench with a low dielectric constant material to form a filling film layer of a secondary buried structure, thereby completing the fabrication of the EA modulator. This secondary buried structure is used to further reduce the parasitic capacitance of the EA device and improve the response frequency of the EML device.

[0050] Step S12 involves fabricating the DFB ridge waveguide structure in the DFB laser, including etching two parallel third trenches on the top of the DFB laser using an etching process. The two third trenches are connected to the docking growth surface and are perpendicular to the docking growth surface. A DFB ridge waveguide structure is formed between the two third trenches. The bottom of the third trench is higher than the DFB active region. The mesa width of the DFB ridge waveguide structure is the same as the mesa width of the ridge waveguide structure in the EA modulator, and the DFB ridge waveguide structure is directly opposite the ridge waveguide structure in the EA modulator.

[0051] Preferably, the mesa width of the DFB ridge waveguide structure is 1.5μm to 2.0μm.

[0052] Preferably, the length of the third groove is 280μm to 320μm.

[0053] Preferably, the third trench is etched into the PQ grating layer.

[0054] Step S13 involves physically isolating the DFB laser and the EA modulator, including etching a fourth trench on the top of the DFB laser using an etching process. The fourth trench is located between the DFB laser and the EA modulator, and is perpendicular to the third trench. The etching depth of the fourth trench is lower than that of the third trench, forming an isolation region between the DFB laser and the EA modulator.

[0055] Preferably, the etching depth of the fourth trench is 0.5 μm to 0.7 μm.

[0056] Compared with existing technologies, the high-speed electro-absorption modulated laser chip and its fabrication method provided by this invention utilize the synergistic structure of the EA active region, the primary buried structure, and the secondary buried structure. This not only reduces the parasitic capacitance and junction capacitance of the device itself, further improving the response frequency, but also effectively avoids the risk of oxidation, further improving the reliability of the device. This better meets the high performance and high reliability requirements of 53G and above high-speed electro-absorption modulated laser chips. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 The side view of the DFB substrate wafer in steps 1-3 of the fabrication method of a high-speed electroabsorption modulated laser chip provided in an embodiment of the present invention.

[0059] Figure 2 This is a schematic diagram of a partial structure at the groove on the DFB substrate wafer in step 4 of a method for fabricating a high-speed electroabsorption modulated laser chip provided in an embodiment of the present invention.

[0060] Figure 3 for Figure 2 Sectional view at point AA.

[0061] Figure 4In a method for fabricating a high-speed electroabsorption modulated laser chip provided in an embodiment of the present invention, step 6, a cross-sectional view after forming the secondary epitaxial structure, is shown, with the cutting position being... Figure 3 same.

[0062] Figure 5 In a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention, step 7 shows a cross-sectional view after forming a three-stage epitaxial structure, with the cutting position being... Figure 3 same.

[0063] Figure 6 This is a schematic diagram of the partial structure after the first trench is generated in step 8 of a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention.

[0064] Figure 7 for Figure 6 Sectional view at point BB.

[0065] Figure 8 In a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention, step 9, a cross-sectional view after the current blocking layer is generated, the cutting position is... Figure 7 same.

[0066] Figure 9 This is a partial structural diagram of a high-speed electro-absorption modulated laser chip fabrication method provided in an embodiment of the present invention, specifically in step 10, after etching the second trench.

[0067] Figure 10 for Figure 9 Sectional view at point CC.

[0068] Figure 11 In a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention, step 11 involves generating a cross-sectional view after the filling film layer is formed, with the cutting position being... Figure 10 same.

[0069] Figure 12 This is a schematic diagram of the partial structure after the third trench is generated in step 12 of a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention.

[0070] Figure 13 This is a schematic diagram of the partial structure after the fourth trench is generated in step 13 of a method for fabricating a high-speed electro-absorption modulated laser chip provided in an embodiment of the present invention.

[0071] Figure 14 for Figure 13 Top view.

[0072] Figure 15This is a three-dimensional structural schematic diagram of the high-speed electroabsorption modulation laser chip prepared according to the present invention.

[0073] Figure 16 A comparative diagram showing the electrical properties, deep-level defect concentration, and compensation of several semi-insulating InP single-crystal materials.

[0074] The markings in the figure are as follows: DFB substrate wafer 1, groove 11, and docking growth surface 12.

[0075] 21. InP substrate, 22. InP buffer layer, 23. PQ etch stop layer, 24. DFB active region, 25. InP space layer, 26. PQ grating layer, 27. Grating buried layer.

[0076] EA active region 31, InP capping layer 32, InP cladding layer 33, PQ material transition layer 34, InGaAs ohmic contact layer 35.

[0077] First trench 41, current blocking layer 42, ridge waveguide structure 43.

[0078] Second groove 51, filling membrane layer 52.

[0079] Third trench 61, DFB ridge waveguide structure 62.

[0080] Fourth trench 71.

[0081] DFB laser 8.

[0082] EA modulator 9. Detailed Implementation

[0083] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0084] Example 1

[0085] This embodiment provides a method for fabricating a high-speed electroabsorption modulated laser chip, including the following steps:

[0086] Step S1: Grow DFB substrate wafer 1 to obtain a primary epitaxial structure, such as... Figure 1As shown. The specific process can be as follows: First, select an S-doped indium phosphide substrate (InP substrate 21) with the corresponding crystal phase, and perform epitaxy on the InP substrate 21. In practice, the number of crystal phases can be determined according to actual needs. As an example, in this embodiment, S-doped indium phosphide substrate 21 is selected. <100> A crystalline InP substrate 21 is used, preferably an S-doped indium phosphide substrate. Then, an indium phosphide buffer layer (InP buffer layer 22) of approximately 1 μm to 1.5 μm is grown on the InP substrate 21. Next, an etch stop layer of appropriate thickness is deposited on the InP buffer layer 22. In this embodiment, an indium gallium arsenide phosphide etch stop layer (PQ etch stop layer 23) is preferably used. The thickness of the PQ etch stop layer 23 can be determined according to actual needs. In this embodiment, the thickness of the PQ etch stop layer 23 is preferably configured to be less than 0.01 μm; for example, in this embodiment, the thickness of the PQ etch stop layer 23 is 0.01 μm. Then, a DFB active region 24 is grown on the PQ etch stop layer 23. The DFB active region 24 can be implemented using existing technology. For example, in this embodiment, the DFB active region 24 may include a SCH confined waveguide layer and 5-8 pairs of quantum well (MQW) layers. The thickness of the DFB active region 24 can preferably be 0.2μm to 0.22μm. Next, an InP space layer 25 is grown on the DFB active region 24. The thickness of the InP space layer 25 can preferably be 0.05-0.08μm. Finally, a PQ grating layer 26 (i.e., an indium gallium arsenide phosphorus grating layer) is grown on the InP space layer 25. The thickness of the PQ grating layer 26 can preferably be controlled to be 0.02μm to 0.05μm, thereby obtaining a primary epitaxial structure and completing the growth of the DFB substrate wafer 1. Figure 1 As shown. In this embodiment, the DFB active region is made of indium gallium arsenide phosphide material, that is, the DFB active region uses an indium gallium arsenide phosphide layer (PQ layer), which can effectively avoid the introduction of Al elements, eliminate the problem of oxidation, and make it easier to obtain a more stable interface, thereby helping to further improve the stability of the chip.

[0087] Step S2 involves fabricating the PQ grating layer 26. Specifically, an EBL electron beam lithography machine can be used to write the grating region, and an ideal grating morphology can be formed using an ICP dry etching process. The depth of the ICP etching can be 0.045 μm to 0.075 μm.

[0088] Step S3: An InP layer, a PQ layer, and an InP layer are sequentially deposited and grown on the grating layer using MOCVD (Metal-Organic Chemical Vapor Deposition). The InP, PQ, and InP layers are used as grating fill layers 27 to fill the grating within the grating layer. Figure 1 As shown.

[0089] Step S4, etch the grooves 11 for selective growth of the EA modulator 9, such as Figure 2 and Figure 3 As shown. Specifically, a 0.3μm~0.5μm thick SiO2 layer can be deposited as a hard mask using PECVD deposition (i.e., plasma-enhanced chemical vapor deposition). After photolithography, the SiO2 is patterned, and then patterned and transferred using RIE dry and wet etching processes (first using solution 1: H2O: H2O2: H2SO4 = 10: 1: 1, then using solution 2: H3PO4: HCl = 3: 1), etching down to the InP buffer layer 22, so as to etch grooves 11 on the DFB substrate wafer 1 for selective growth of the EA modulator 9, as shown. Figure 2 and Figure 3 As shown. In implementation, the groove 11 can preferably adopt a cuboid structure, which is more convenient for the subsequent growth of the EA modulator. It can be understood that in implementation, SiO2 is deposited on the top layer. For example, when the top layer is the grating buried layer 27, SiO2 is deposited on the grating buried layer 27. In this embodiment, the width of the groove 11 can be equal to or greater than the width of the designed laser chip. The required width can be obtained by subsequent cutting. In this embodiment, the width of the groove 11 can preferably be 120μm to 160μm. For example, in implementation, the width of the groove 11 can preferably be 120μm, 130μm, 140μm, 150μm, and 160μm, etc. Figure 2 and Figure 3 As shown. For ease of description, in this embodiment, one sidewall of the groove 11 serves as the docking growth surface 12 for the DFB laser 8, as shown. Figure 2 and Figure 3 As shown, the DFB laser 8 and EA modulator 9 are respectively constructed on both sides of the mating growth surface 12 and are connected to each other through the mating growth surface 12. It is understood that, in practice, the size of the groove 11 is determined according to actual process and production requirements; this embodiment does not impose any special limitations, and... Figure 2 This is just one possible shape of the groove 11. In practice, there are many other possible implementations of the groove 11. For example, the groove 11 can also be constructed as a long strip groove, etc., which will not be described in detail here.

[0090] Step S5: Clean the surface of the DFB substrate wafer 1 to remove residual organic matter and oxide film. Specifically, in this embodiment, the sample of the DFB substrate wafer 1 to be grown can be cleaned sequentially with ACE solution, IPA solution, and DI solution, and then immersed in BOE solution. The immersion time can be determined according to actual needs. In this embodiment, immersion in BOE solution for 30 seconds can effectively remove the oxide film on the sample surface.

[0091] Step S6: A secondary epitaxial structure is formed within the groove 11 of the DFB substrate wafer 1, that is, the EA modulator 9 is grown within the groove 11 of the DFB substrate wafer 1. Specifically, this process includes first growing an InP buffer layer 22 at the bottom of the groove 11, such as... Figure 4 As shown, the thickness of the InP buffer layer 22 can be preferentially controlled to be 0.22 μm ~ 0.25 μm. Then, an EA active region 31 is deposited on the InP buffer layer 22, where the EA active region mainly consists of 11~15 pairs of quantum well (MQW) layers. The EA active region 31 is adjacent to the DFB active region 24, as shown... Figure 4 As shown, the thickness of the EA active region 31 is greater than the thickness of the DFB active region 24, which helps to reduce light loss at the docking position. Simultaneously, in implementation, the bottom end of the EA active region 31 can be flush with the bottom end of the DFB active region 24, while the top end of the EA active region 31 is higher than the top end of the DFB active region 24, as shown. Figure 4 As shown, this can effectively reduce light loss at the docking position. At this time, the top of the InP buffer layer 22 is flush with the top of the PQ etch stop layer 23. Of course, in practice, the top of the InP buffer layer 22 can also be lower than the PQ etch stop layer 23, so that the bottom of the EA active region 31 can also be lower than the bottom of the DFB active region 24, while the top of the EA active region 31 is still higher than the top of the DFB active region 24. Finally, an InP capping layer 32 of a certain thickness is grown above the EA active region 31, such as... Figure 4 As shown, the thickness of the InP capping layer 32 can be determined according to actual needs. For example, in this embodiment, the thickness of the InP capping layer 32 is 0.02 μm. Furthermore, in implementation, the upper end of the InP capping layer 32 can be flush with the upper end of the grating buried layer 27. Of course, in some embodiments, the upper end of the InP capping layer 32 can also be slightly lower or slightly higher than the upper end of the grating buried layer 27. In this embodiment, the EA active region uses indium gallium aluminum arsenide material, that is, the EA active region uses an AlQ layer. Compared with indium gallium arsenide phosphide material (PQ layer), its ΔEg distribution ratio on ΔEc / ΔEv is larger. The lower ΔEv has the advantage of improving hole mobility, which can effectively improve the extinction ratio output performance and response frequency of the device.

[0092] Step S7 involves growing a three-stage epitaxial structure, specifically including first growing an InP cladding layer 33 on the DFB substrate wafer 1, such as... Figure 5 As shown, the thickness of the InP cladding layer 33 can preferably be controlled to be 2.1~2.5 μm. Then, a PQ material transition layer 34 of a certain thickness is grown on the InP cladding layer 33, as shown. Figure 5 As shown, for example, in implementation, the thickness of the PQ material transition layer 34 can preferably be controlled to be 0.01 μm ~ 0.05 μm. Finally, an InGaAs ohmic contact layer 35 is grown on the PQ material transition layer 34, as shown. Figure 5 As shown, the thickness of the InGaAs ohmic contact layer 35 can preferably be 0.02μm to 0.025μm, such as 0.020μm, 0.021μm, 0.022μm and 0.023μm, to form a three-dimensional epitaxial structure.

[0093] Step S8, forming the first groove 11 in the primary buried structure, specifically may include growing a 0.3μm~0.5μm SiO2 layer as a hard mask on the InP capping layer 32 of the EA modulator using PEVCD technology, then patterning the SiO2 of the EA modulator using photolithography, and then dry etching two first trenches 41 within the groove 11 using an inductively coupled plasma etching (ICP) machine. Figure 6 and Figure 7 As shown, the two first grooves 41 are parallel to each other and arranged opposite to each other. The two first grooves 41 are perpendicular to the docking growth surface 12 of the EA modulator, as shown. Figure 6 and Figure 7 As shown, a straight ridge waveguide structure 43 is formed between the two first trenches 41. In implementation, the mesa width of the ridge waveguide structure 43 can be determined according to actual needs. Preferably, the mesa width of the ridge waveguide structure 43 can be 1.5μm to 2μm. For example, in implementation, the mesa width of the ridge waveguide structure 43 can be preferably controlled as 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2.0μm, etc. In implementation, the bottom of the first trench 41 can be preferentially etched into the InP buffer layer 22 of the secondary epitaxial structure, such as... Figure 6 and Figure 7 As shown, the etching depth can be preferentially controlled to be 3μm to 3.5μm, that is, the depth of the first trench 41 can preferably be 3μm to 3.5μm. For example, in implementation, the etching depth can preferably be 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, etc. In implementation, the widths of the two first trenches 41 can be the same or different, and the sum of the width of the mesa of the ridge waveguide structure 43 and the width of the two first trenches 41 can be greater than or equal to the width of the groove 11. For example, in this embodiment, such as Figure 6 and Figure 7 As shown, the two first grooves 41 have the same width, and the sum of the width of the platform of the ridge waveguide structure 43 and the width of the two first grooves 41 is exactly equal to the width of the groove 11, which is more conducive to the implementation of subsequent processes.

[0094] Step S9 involves forming the current-blocking layer 42 in the primary burial structure. Specifically, this may include depositing and growing semi-insulating InP in the two first trenches 41 using MOCVD (Metal-Organic Chemical Vapor Deposition) to form the current-blocking layer 42. The deposition temperature can be preferentially controlled at 620°C for better results. In practice, the thickness of the current-blocking layer 42 can be less than the depth of the first trenches 41, and the upper end of the current-blocking layer 42 needs to be higher than the upper end of the EA active region 31 to form a primary burial structure for the EA active region 31. Figure 8 As shown. In implementation, the thickness of the current blocking layer 42 can preferably be controlled to be 0.5μm to 2μm. In implementation, the semi-insulating InP can be made of materials such as iron (Fe)-doped InP or rubidium (Rb)-doped InP, so that the generated current blocking layer 42 has semi-insulating characteristics. That is, when the laser chip is operating at the design current, the semi-insulating InP remains in an insulating state, and when the operating current of the laser chip is greater than the set threshold, the semi-insulating InP can conduct electricity. By setting the current blocking layer 42 made of semi-insulating InP material on both sides of the mesa of the ridge waveguide structure 43, not only can a high-resistance current blocking layer 42 be formed, but also a primary burial structure for the EA active region 31 can be formed. This can effectively limit the current and optical field of the EA modulator, form interface passivation protection for the EA modulator, and prevent the EA active region 31 from being exposed to air, thus achieving a better protection effect.

[0095] Step S10: Adjust the width of the current blocking layer 42 to meet the design requirements. Specifically, a PECVD deposition method can be used to deposit a certain thickness of SiO2 as a hard mask on the current blocking layer 42. The thickness of the SiO2 can be determined according to actual needs; for example, in this embodiment, the SiO2 thickness is 1.6 μm. Then, the SiO2 of the EA modulator portion is patterned using a photolithography process. Finally, dry etching and wet etching processes are used to etch away part of the outer end of the current blocking layer 42, ensuring that the width of the current blocking layer 42 accurately meets the design requirements. Through etching, the width of the current blocking layer 42 can be preferentially set to be greater than or equal to 2 μm. Specifically, high concentrations of deep-level defects are often detected in primary iron doping, and these defects inevitably affect the electrical compensation of the material. (Refer to...) Figure 16According to the formula R=ρL / S①, and considering the reserved design dimensions of the current blocking layer 42 in this embodiment, where ρ is the resistivity of the material used to make the resistor, ρ=2×10 7 Ω*cm, L: Length of the wire wound into a resistor ≥ 2μm (width of the mesa of the ridge waveguide structure 43), S: Cross-sectional area of ​​the wire wound into a resistor, taken as 160μm × 2μm (length and thickness), R: Resistance value. Substituting into ①, we get Rs ≥ 1GΩ; when Rs is within the GΩ range, it is considered that a relatively ideal current blocking effect can be achieved. Therefore, in this embodiment, the width of the current blocking layer 42 is set to be greater than or equal to 2μm.

[0096] Therefore, in practice, the width of the current blocking layer 42 is preferably 2μm to 5μm, which is beneficial for achieving better results. In a further embodiment, the width of the current blocking layer 42 can also preferably be 2μm to 3μm, so that the current blocking layer 42 can be made thinner while meeting the design requirements. For example, in implementation, the width of the current blocking layer 42 can preferably be 2μm, 2.2μm, 2.5μm, 2.7μm, 2.8μm, or 3μm, etc. By effectively controlling the width of the current blocking layer 42, the current blocking layer 42 can better exert its semi-insulating characteristics. In addition, in the production process, by forming current blocking layers 42 of different widths, the needs of different applications can be met. In implementation, the etching depth is greater than the thickness of the current blocking layer 42 so that second trenches 51 are formed on both sides of the EA modulator, such as... Figure 9 and Figure 10 As shown, the lower end of the second groove 51 is lower than the lower end of the first groove 41. The two second grooves 51 are parallel to each other and arranged opposite each other, and the two second grooves 51 are perpendicular to the docking growth surface 12 of the EA modulator, as shown. Figure 9 and Figure 10 As shown, a deep ridge waveguide structure with a secondary buried structure can be formed between the two second trenches 51, so as to effectively reduce the photon lifetime of the EA active region 31 and improve the response characteristics of the EA device. During etching, it is preferable to etch into the InP buffer layer 22, such as... Figure 9 and Figure 10 As shown, the etching depth can be preferentially controlled to be 3.5μm ~ 10μm.

[0097] Step S11 involves filling the second trench 51 with a low dielectric constant material to form a filling film layer 52 of a secondary buried structure, thereby completing the fabrication of the EA modulator. In this embodiment, low dielectric constant materials such as polyimide or benzocyclobutene can be preferentially used to fill the second trench 51. The upper end of the filling film layer 52 can be flush with the InGaAs ohmic contact layer 35. Figure 11 and Figure 12As shown. In this step, a low dielectric constant material is used to fill the second trench 51 under the electrode so that it, together with the second trench 51 and the current blocking layer 42, forms a secondary buried structure, which can effectively reduce the parasitic capacitance of the EA device and improve the response frequency of the EML device.

[0098] Step S12 involves fabricating the DFB ridge waveguide structure 62 in the DFB laser 8. Specifically, this may include: first, growing 0.15 μm SiO2 using PECVD as a hard mask; then, patterning the SiO2 using photolithography to obtain the ridge waveguide pattern; and finally, transferring the pattern using RIE dry and wet etching (solution H3PO4:HCl = 3:1) to etch downwards from the top of the DFB laser 8, resulting in two parallel third trenches 61. Figure 12 As shown, the width of the third groove 61 can preferably be 1.5μm to 2.0μm, and the length of the third groove 61 can preferably be 280μm to 320μm. The third groove 61 is perpendicular to the docking growth surface 12, as shown. Figure 12 As shown, the maximum distance between the two third grooves 61 can be greater than or equal to the width of the groove 11, for example, as... Figure 12 As shown, in this embodiment, the two third trenches 61 have the same width, and the maximum distance between the two third trenches 61 is exactly equal to the width of the groove 11. A DFB ridge waveguide structure 62 is formed between the two third trenches 61. The mesa width of the DFB ridge waveguide structure 62 can be determined according to actual needs. In implementation, the mesa width of the DFB ridge waveguide structure 62 can preferably be 1.5μm to 2.0μm. For example, Figure 12 As shown, the platform width of the DFB ridge waveguide structure 62 is the same as the platform width of the ridge waveguide structure 43 in the EA modulator 9, and the DFB ridge waveguide structure 62 is directly opposite the ridge waveguide structure 43 in the EA modulator 9 to achieve better fit.

[0099] This step does not etch the DFB active region 24. Therefore, in practice, etching is only required to a position higher than the DFB active region 24. That is, the bottom of the third trench 61 is higher than the DFB active region 24. For example, in this embodiment, the third trench 61 is etched to the PQ grating layer 26.

[0100] A more refined solution also includes step S13, which physically isolates the DFB laser 8 from the EA modulator 9. Specifically, this may involve first growing 0.45μm SiO2 as a hard mask using PECVD, then patterning the SiO2 using photolithography to obtain the pattern of the fourth trench 71, and then transferring the pattern using RIE dry and wet etching (solution H3PO4:HCl = 3:1) to etch the fourth trench 71 onto the top of the DFB laser 8. The fourth trench 71 is located between the DFB laser 8 and the EA modulator 9. Figure 13 and Figure 14 As shown, this is to form an isolation region between the DFB laser and the EA modulator 9, avoiding current crosstalk between the two devices during operation. The fourth trench 71 is perpendicular to the third trench 61, and the width of the fourth trench 71 can be equal to the width of the groove 11, as shown. Figure 13 and Figure 14 As shown. The etching depth of the fourth trench 71 is lower than that of the third trench 61, as... Figure 13 and Figure 14 As shown, the bottom of the fourth trench 71 is higher than the bottom of the third trench 61. In practice, the fourth trench 71 can be preferentially etched to the InP cladding 33, and the etching depth of the fourth trench 71 can preferably be 0.5μm to 0.7μm, thereby completing the fabrication of the isolation region.

[0101] In step S14, SiO2 (e.g., with a thickness of 1 μm) and SiNx (e.g., with a thickness of 0.3 μm) are sequentially grown on the DFB substrate wafer 1 using PECVD process as device passivation films. The windowing process of the DFB ridge waveguide structure 62 in the DFB laser 8 and the ridge waveguide structure 43 in the EA modulator 9 is completed using conventional photolithography. Then, P-type electrodes (Ti / Pt / Au=50 / 100 / 300nm) are prepared by magnetron sputtering. Finally, the electrodes are annealed at 450°C for 45 seconds using an RTA rapid annealing furnace to form good ohmic contacts.

[0102] Step S15: The DFB substrate wafer 1 is thinned to 100-150 μm using a grinding and polishing machine, and then cut and split to prepare bar strips. During implementation, the bar strips can be cut along... Figure 14 The outline shown by the dashed line is cut to obtain... Figure 15 The bar shown has a long, strip-shaped structure. In this case, the width of the chip is equal to the width of the groove 11, and the length of the chip is equal to the sum of the length of the groove 11, the length of the fourth groove 71, and the length of the third groove 61. Figure 14 and Figure 15As shown, optical thin films are finally deposited on the AR and HR surfaces at both ends of the bar (existing technology, not described in detail here) to complete the fabrication of the high-speed electroabsorption modulation laser chip, as follows. Figure 15 As shown.

[0103] In the high-speed electro-absorption modulated laser chip prepared in this embodiment, the DFB laser 8 operates under constant current, mainly providing constant light output. Its constant current operation solves the problem of DFB lasing wavelength drift (chirping) caused by changes in operating current. The EA modulator 9 primarily modulates the continuous optical signal from the DFB laser 8.

[0104] The EML chip prepared by the above method has advantages such as low series resistance, low parasitic capacitance, high injection efficiency, and low chirp, making the EML chip more stable and reliable. It also makes it easier to achieve high modulation rate and response frequency, and is especially suitable for high-speed electroabsorption modulation laser chips with a speed of 53G and above.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-speed electroabsorption modulated laser chip, characterized in that, Includes the following steps: Step S1: A primary epitaxial structure is grown on the substrate to obtain the substrate wafer of the DFB laser. The primary epitaxial structure includes, from bottom to top: an InP buffer layer, a PQ etch stop layer, a DFB active region, an InP space layer, and a PQ grating layer grown on the substrate. Step S2: Fabrication of the PQ grating layer; Step S3: Deposit and grow a grating fill layer on the grating layer; Step S4: Etch a groove for selective growth of the EA modulator, the groove being etched down to the InP buffer layer, and use one of the sidewalls of the groove as the docking growth surface for the DFB laser. Step S5: Clean the surface of the substrate wafer to remove residual organic matter and oxide film. Step S6, growing a secondary epitaxial structure in the groove, includes growing an InP buffer layer at the bottom of the groove, depositing an EA active region on the InP buffer layer, and growing an InP capping layer above the EA active region, wherein the EA active region is connected to the DFB active region through a mating growth surface. Step S7, growing a three-stage epitaxial structure, including: growing an InP cladding layer on the DFB substrate wafer, growing a PQ material transition layer on the InP cladding layer, and growing an InGaAs ohmic contact layer on the PQ material transition layer. Step S8, forming the first trench of the primary buried structure, includes etching two parallel first trenches in the groove using an etching process, etching the first trenches to the InP buffer layer of the secondary epitaxial structure, the two first trenches being connected to the docking growth surface respectively, and the two first trenches being perpendicular to the docking growth surface respectively, and forming a straight ridge waveguide structure between the two first trenches. Step S9, forming a current blocking layer for a primary burial structure, includes depositing and growing current blocking layers in two first trenches using MOCVD process. The upper end of the current blocking layer is higher than the upper end of the EA active region, and the top end of the current blocking layer is lower than the top end of the ridge waveguide structure. The EA active region is buried using the current blocking layer to form a primary burial structure for the EA active region. The current blocking layer is made of semi-insulating InP material. Step S10: Within the groove area, an etching process is used to etch downwards along the outer ends of the two current blocking layers respectively, forming two parallel second trenches. The etching also reduces the width of the current blocking layers to meet the design requirements. The lower end of the second trench is lower than the lower end of the first trench, and the two second trenches are perpendicular to the docking growth surface, forming a deep ridge waveguide structure with a secondary burial structure between the two second trenches. Step S11: Fill the first trench and the second trench with a low dielectric constant material to form a filling film layer of a secondary buried structure. The filling film layer buries the current blocking layer to complete the fabrication of the EA modulator.

2. The method for fabricating a high-speed electro-absorption modulated laser chip according to claim 1, characterized in that, The process also includes step S12, which involves fabricating the DFB ridge waveguide structure in the DFB laser. This includes etching two parallel third trenches on the top of the DFB laser using an etching process. The two third trenches are connected to the docking growth surface and are perpendicular to the docking growth surface. A DFB ridge waveguide structure is formed between the two third trenches. The bottom of the third trench is higher than the DFB active region. The mesa width of the DFB ridge waveguide structure is the same as the mesa width of the ridge waveguide structure in the EA modulator, and the DFB ridge waveguide structure is directly opposite the ridge waveguide structure in the EA modulator. Step S13 involves physically isolating the DFB laser and the EA modulator, including etching a fourth trench on the top of the DFB laser using an etching process. The fourth trench is located between the DFB laser and the EA modulator, and is perpendicular to the third trench. The etching depth of the fourth trench is lower than that of the third trench, forming an isolation region between the DFB laser and the EA modulator.

3. The method for fabricating a high-speed electro-absorption modulated laser chip according to claim 1, characterized in that, The width of the current blocking layer along the direction away from the EA active region is 2μm~5μm, so that the primary burial structure forms a semi-insulated burial structure.

4. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 3, characterized in that, The width of the current blocking layer along the direction away from the EA active region is 2μm~3μm.

5. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 1, characterized in that, The semi-insulating InP material includes iron-doped InP material or rubidium-doped InP material.

6. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 1, characterized in that, The bottom of the first trench is lower than the bottom of the EA active region, and the thickness of the current blocking layer is greater than the thickness of the EA active region.

7. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 1, characterized in that, The bottom of the EA active region is flush with or lower than the bottom of the DFB active region, and the top of the EA active region is higher than the top of the DFB active region. And / or, the mesa width of the ridge waveguide structure is 0.3μm to 2.5μm.

8. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 1, characterized in that, The active region of the DFB is made of indium gallium arsenide phosphide material; And / or, the active region of the EA is made of indium gallium aluminum arsenide.

9. The method for fabricating a high-speed electro-absorption modulated laser chip according to claim 1, characterized in that, The filling film layer is made of polyimide or benzocyclobutene.

10. The method for fabricating a high-speed electroabsorption modulated laser chip according to claim 1, characterized in that, The lower end of the groove is located in the InP buffer layer of the DFB laser, and the lower ends of the first groove and the second groove are located in the InP buffer layer of the EA modulator, respectively.

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