System and method for automatic identification and address assignment of vehicle controller expansion submodules

Abstract

The application discloses a kind of automatic identification and address allocation system and method of vehicle-mounted controller extension submodule, main module is connected with extension submodule unit using module signal line and CAN bus respectively, based on the level signal of module signal line detected by main module, and the acquisition instruction issued by the main module is transmitted to extension submodule through CAN bus, and the extension submodule parameter information obtained by extension submodule according to acquisition instruction is fed back to main module;At the same time, the address allocation instruction of extension submodule issued by main module according to the feedback extension submodule parameter information is transmitted through CAN bus, the automatic identification and address allocation of vehicle-mounted controller extension submodule are realized.Solve the method that traditional vehicle-mounted module installation position is fixed and one-to-one configuration address, so that the address of distribution vehicle-mounted module is more convenient and save time and increase the flexibility of allocation address, effectively reduce the number of connection line between modules, reduce the complexity of hardware connection.

Description

Technical Field

[0001] This invention relates to the field of vehicle controller platform expansion submodule identification technology, and in particular to an automatic identification and address allocation system and method for vehicle controller expansion submodules. Background Technology

[0002] As a modular design platform, the on-board controller platform connects multiple different modules to form a complex on-board controller system. It can be applied to different occasions, scales, and interfaces. However, different on-board controllers use different numbers and types of modules. Traditional on-board controllers require custom backplanes to be designed according to the number and type of modules needed. Since each on-board module in existing rail locomotives requires different functions, the on-board module addresses need to be manufactured using functional backplanes, and the external address lines of the on-board modules need to be set. This is not only time-consuming and costly but also cumbersome, increasing the number of connection lines between modules and adding to the complexity of hardware connections. Summary of the Invention

[0003] This invention provides an automatic identification and address allocation system and method for an on-board controller extension submodule to overcome the above-mentioned technical problems.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows:

[0005] An automatic identification and address allocation system for an onboard controller expansion submodule includes a main module, expansion submodule units, multiple module signal lines, and a CAN bus.

[0006] The main module is hardwired to the expansion submodule unit via module signal lines. The expansion submodule unit has multiple expansion submodules, and the expansion submodules are hardwired to each other via module signal lines. The main module communicates with each expansion submodule via a CAN bus.

[0007] Each module signal line includes an LE signal line and an LC signal line. The main module identifies the current extended submodule by detecting the level signal of the LE signal line of the current extended submodule directly connected to the main module; and identifies the next-level extended submodule by detecting the level signal of the LE signal line of the next-level extended submodule connected to the current extended submodule. The main module detects and obtains the level signal of the LE signal line of the current extended submodule and sends a trigger level signal to the current extended submodule through the LC signal line; the trigger level signal is used to trigger the current extended submodule and feed back the parameter information of the current extended submodule to the main module through the CAN bus.

[0008] Alternatively, the current expansion submodule can send a trigger level signal to the next-level expansion submodule via the LC signal line. The next-level expansion submodule, based on the received trigger level signal, feeds back its parameter information to the main module via the CAN bus.

[0009] The parameter information includes interface data set according to the I / O interface type and quantity of the extended submodule;

[0010] The main module issues address allocation instructions to each extended submodule based on the CAN bus feedback parameter information, and allocates addresses to each extended submodule according to the address allocation instructions to obtain the address allocation list of the extended submodules.

[0011] Furthermore, the main module includes a main controller MCU, a first pull-up resistor R1, a second pull-up resistor R2, and a first tri-state gate driver G;

[0012] The main controller MCU's input pin InLE, one end of the second pull-up resistor R2, and one end of the LE signal line are connected, and the other end of the LE signal line is connected to the ground line set by the expansion submodule unit; the other end of the second pull-up resistor R2, one end of the first pull-up resistor R1, and the VCC terminal are connected.

[0013] The output pin OE of the main controller MCU, the other end of the first pull-up resistor R1, and the control terminal of the first tri-state gate driver G are connected; the input terminal of the first tri-state gate driver G is grounded, and the output terminal of the first tri-state gate driver G is connected to the expansion submodule unit through an LC signal line.

[0014] Furthermore, the specific implementation method for the main module to detect and identify the current extended sub-module is as follows:

[0015] Define the extended submodule that is directly connected to the main module through the module signal line as the current extended submodule; the main module is initialized upon power-up, and the input pin InLE of the main controller MCU is defined as a floating input, the output pin OE of the main controller MCU is defined as a high level output, and the first tri-state gate driver G is in the off state;

[0016] The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended sub-module is identified based on the first module identification strategy.

[0017] The specific identification strategy of the first module is as follows:

[0018] If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light.

[0019] If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended submodule is confirmed to be identified.

[0020] The method by which the main module allocates addresses to the current extended submodule is as follows:

[0021] When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module through the first tri-state gate driver G and the LC signal line in sequence.

[0022] The sub-controller MCU1 detects a low-level signal corresponding to the first input pin InLC1, acquires the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus.

[0023] The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule;

[0024] The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule via the CAN bus.

[0025] After the current extended submodule receives the CAN bus sign-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU.

[0026] Furthermore, the extended submodule unit includes multiple extended submodules connected sequentially via module signal lines;

[0027] The extended submodule includes a sub-controller MCU1, a third pull-up resistor R11, a fourth pull-up resistor R12, a fifth pull-up resistor R13, and a second tri-state gate driver G1;

[0028] The output of the first tri-state gate driver G is connected to the first input pin InLC1 of the sub-controller MCU1, one end of the third pull-up resistor R11, and the input of the second tri-state gate driver G1 via an LC signal line. The control terminal of the second tri-state gate driver G1 is connected to the output pin OE1 of the sub-controller MCU1 and one end of the fourth pull-up resistor R12. The second input pin InLE1 of the sub-controller MCU1 and one end of the fifth pull-up resistor R13 are connected to the grounding wire of the multi-level expansion sub-module via an LE signal line. The other ends of the third pull-up resistor R11, the fourth pull-up resistor R12, and the fifth pull-up resistor R13 are connected to the VCC terminal. The output of the second tri-state gate driver G1 is connected to the next-level expansion sub-module via an LC signal line.

[0029] Furthermore, the specific implementation method for the current extended submodule to detect and identify the next-level extended submodule is as follows:

[0030] The sub-controller MCU1 of the current extended sub-module continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, the next level extended sub-module of the current extended sub-module is identified based on the second module identification strategy.

[0031] The second module's identification strategy is as follows:

[0032] If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light.

[0033] If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended submodule is confirmed to be identified.

[0034] The method for the main module to allocate addresses to the next-level extended sub-modules is as follows:

[0035] If the sub-controller MCU1 of the current expansion sub-module detects that the second input pin InLE1 is low, then the output pin OE of the sub-controller MCU1 of the current expansion sub-module is low, and the second tri-state gate driver G1 is in the conducting state. Then, the low-level signal at the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module through the second tri-state gate driver G1 and the LC signal line in sequence.

[0036] The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus.

[0037] The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule;

[0038] The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level extended submodule based on the parameter information of the next-level current extended submodule, and transmits it to the next-level extended submodule through the CAN bus;

[0039] After receiving the CAN bus sign-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU.

[0040] An automatic identification and address allocation method for an onboard controller expansion submodule includes the following steps:

[0041] S1: The main module is powered on and initialized; the input pin InLE of the main controller MCU is defined as a floating input, the output pin OE of the main controller MCU is defined as a high level output, and the first tri-state gate driver G is in the off state;

[0042] S2: The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended submodule of the extended submodule unit is identified based on the first module identification strategy;

[0043] The specific identification strategy of the first module is as follows:

[0044] If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light.

[0045] If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended sub-module is identified and step S3 is executed.

[0046] S3: When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, through the first tri-state gate driver G and the LC signal line in sequence, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module.

[0047] S4: The sub-controller MCU1 detects the low-level signal corresponding to the first input pin InLC1, obtains the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus;

[0048] The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule;

[0049] The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule via the CAN bus.

[0050] After the current extended submodule receives the CAN bus check-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU.

[0051] S5: The sub-controller MCU1 continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, it confirms and identifies the next level expansion sub-module of the current expansion sub-module based on the second module identification strategy;

[0052] The second module's identification strategy is as follows:

[0053] If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light.

[0054] If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended sub-module is identified and step S6 is executed.

[0055] S6: When the next-level sub-controller MCU1 detects that the second input pin InLE1 is a low-level signal, it outputs a low level through the output pin OE of the sub-controller MCU1, and the second tri-state gate driver G1 is in the conducting state. Then, through the second tri-state gate driver G1 and the LC signal line, the low-level signal output from the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module.

[0056] S7: The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus;

[0057] The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule;

[0058] The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level extended submodule based on the parameter information of the next-level current extended submodule, and transmits it to the next-level extended submodule through the CAN bus;

[0059] After receiving the CAN bus check-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU.

[0060] S8: Repeat S5 to S7 until the automatic identification and address allocation of all extended submodules in the extended submodule unit are completed.

[0061] Furthermore, the CAN bus is a differential communication line used to transmit CAN bus response messages for address allocation commands;

[0062] With CAN bus check-in messages used to transmit parameter information of each extended submodule in the extended submodule unit.

[0063] Beneficial Effects: This invention provides an automatic identification and address allocation system and method for vehicle controller expansion submodules. The main module is connected to the expansion submodule units via module signal lines and a CAN bus. The main module detects the level signals of the module signal lines and transmits acquisition commands issued by the main module to the expansion submodules via the CAN bus. It also feeds back the expansion submodule parameter information obtained by the expansion submodules according to the acquisition commands to the main module. Simultaneously, the main module transmits address allocation commands for the expansion submodules based on the feedback parameter information via the CAN bus, thus achieving automatic identification and address allocation of the vehicle controller expansion submodules. This solves the problem of traditional methods that require fixed installation positions and one-by-one address configuration for vehicle modules, making address allocation more convenient, time-saving, and flexible. It also effectively reduces the number of connecting lines between modules and decreases the complexity of hardware connections. Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] Figure 1 This is a block diagram of the automatic identification and address allocation system for the vehicle controller extension submodule of the present invention;

[0066] Figure 2 This is a schematic diagram of the automatic identification and address allocation system for the vehicle controller extension submodule of the present invention;

[0067] Figure 3 This is a flowchart of the main module for automatic identification and address allocation of the vehicle controller extension submodule in this embodiment;

[0068] Figure 4 This is a flowchart of the automatic identification and address allocation submodule of the vehicle controller extension submodule in this embodiment. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] This embodiment provides an automatic identification and address allocation system for an onboard controller expansion submodule, such as... Figures 1 to 2 As shown, it includes a main module, expansion sub-module units, multiple module signal lines, and a CAN bus;

[0071] The main module is hardwired to the expansion submodule unit via module signal lines. The expansion submodule unit has multiple expansion submodules, and the expansion submodules are hardwired to each other via module signal lines. The main module communicates with each expansion submodule via a CAN bus.

[0072] Each module signal line includes an LE signal line and an LC signal line. The main module identifies the current extended submodule by detecting the level signal of the LE signal line of the current extended submodule directly connected to the main module; and identifies the next-level extended submodule by detecting the level signal of the LE signal line of the next-level extended submodule connected to the current extended submodule. The main module detects and obtains the level signal of the LE signal line of the current extended submodule and sends a trigger level signal to the current extended submodule through the LC signal line; the trigger level signal is used to trigger the current extended submodule and feed back the parameter information of the current extended submodule to the main module through the CAN bus.

[0073] Alternatively, the current expansion submodule can send a trigger level signal to the next-level expansion submodule via the LC signal line. The next-level expansion submodule, based on the received trigger level signal, feeds back its parameter information to the main module via the CAN bus.

[0074] The parameter information includes interface data set according to the I / O interface type and quantity of the extended submodule;

[0075] The main module issues address allocation instructions to each extended submodule based on the CAN bus feedback parameter information, and allocates addresses to each extended submodule according to the address allocation instructions to obtain the address allocation list of the extended submodules.

[0076] In this embodiment, the main module is connected to the expansion sub-module units via module signal lines and a CAN bus. The main module detects the level signals on the module signal lines and transmits acquisition commands issued by the main module to the expansion sub-modules via the CAN bus. It also feeds back the expansion sub-module parameter information obtained by the expansion sub-modules according to the acquisition commands to the main module. Simultaneously, the main module transmits address allocation commands for the expansion sub-modules based on the feedback parameter information via the CAN bus, enabling automatic identification and address allocation of the vehicle controller's expansion sub-modules. This solves the problem of traditional methods involving unlocking vehicle modules and configuring addresses one by one, making address allocation for vehicle modules more convenient, time-saving, and increasing the success rate of address allocation. It also effectively reduces the number of connection lines between modules and decreases the complexity of hardware connections.

[0077] In a specific embodiment, the main module includes a main controller MCU, a first pull-up resistor R1, a second pull-up resistor R2, and a first tri-state gate driver G;

[0078] The main controller MCU's input pin InLE, one end of the second pull-up resistor R2, and one end of the LE signal line are connected, and the other end of the LE signal line is connected to the ground line set by the expansion submodule unit; the other end of the second pull-up resistor R2, one end of the first pull-up resistor R1, and the VCC terminal are connected.

[0079] The output pin OE of the main controller MCU, the other end of the first pull-up resistor R1, and the control terminal of the first tri-state gate driver G are connected; the input terminal of the first tri-state gate driver G is grounded, and the output terminal of the first tri-state gate driver G is connected to the expansion submodule unit through an LC signal line.

[0080] In a specific embodiment, the method for the main module to detect and identify the current extended sub-module is as follows:

[0081] Define the extended submodule that is directly connected to the main module through the module signal line as the current extended submodule, and send a power-on signal through the controller LAN to control the main module to power on and initialize; and define the input pin InLE of the main controller MCU as floating input, define the output pin OE of the main controller MCU as output high level, and the first tri-state gate driver G is in the off state;

[0082] The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended sub-module is identified according to the first module identification strategy.

[0083] The specific identification strategy of the first module is as follows:

[0084] If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light.

[0085] If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended submodule is confirmed to be identified.

[0086] The method by which the main module allocates addresses to the current extended submodule is as follows:

[0087] When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module through the first tri-state gate driver G and the LC signal line in sequence.

[0088] The sub-controller MCU1 detects a low-level signal corresponding to the first input pin InLC1, acquires the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus.

[0089] The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule;

[0090] The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule via the CAN bus.

[0091] After the current extended submodule receives the CAN bus sign-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU.

[0092] In a specific embodiment, the expansion submodule unit includes multiple expansion submodules connected sequentially via module signal lines;

[0093] Each of the aforementioned extended sub-modules includes a sub-controller MCU1, a third pull-up resistor R11, a fourth pull-up resistor R12, a fifth pull-up resistor R13, and a second tri-state gate driver G1;

[0094] The output of the first tri-state gate driver G is connected to the first input pin InLC1 of the sub-controller MCU1, one end of the third pull-up resistor R11, and the input of the second tri-state gate driver G1 via an LC signal line. The control terminal of the second tri-state gate driver G1 is connected to the output pin OE1 of the sub-controller MCU1 and one end of the fourth pull-up resistor R12. The second input pin InLE1 of the sub-controller MCU1 and one end of the fifth pull-up resistor R13 are connected to the grounding wire of the multi-level expansion sub-module via an LE signal line. The other ends of the third pull-up resistor R11, the fourth pull-up resistor R12, and the fifth pull-up resistor R13 are connected to the VCC terminal. The output of the second tri-state gate driver G1 is connected to the next-level expansion sub-module via an LC signal line.

[0095] In a specific embodiment, the method for the current extended submodule to detect and identify the next-level extended submodule is as follows:

[0096] The sub-controller MCU1 of the current extended sub-module continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of the continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, the next level extended sub-module of the current extended sub-module is identified based on the second module identification strategy.

[0097] The second module's identification strategy is as follows:

[0098] If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light.

[0099] If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended submodule is confirmed to be identified.

[0100] The method for allocating Jining addresses for the next-level extended sub-modules by the main module is as follows:

[0101] If the sub-controller MCU1 of the current expansion sub-module detects that the second input pin InLE1 is low, then the output pin OE of the sub-controller MCU1 of the current expansion sub-module is low, and the second tri-state gate driver G1 is in the conducting state. Then, the low-level signal at the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module through the second tri-state gate driver G1 and the LC signal line in sequence.

[0102] The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus.

[0103] The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule;

[0104] The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level extended submodule based on the parameter information of the next-level current extended submodule, and transmits it to the next-level extended submodule through the CAN bus;

[0105] After receiving the CAN bus sign-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU.

[0106] A method for an automatic identification and address allocation system for an onboard controller extension submodule, such as... Figures 3 to 4 As shown, it includes the following steps:

[0107] S1: The main module is powered on and initialized by sending a power-on signal through the controller LAN; the input pin InLE of the main controller MCU is defined as a floating input, the output pin OE of the main controller MCU is defined as a high level output, and the first tri-state gate driver G is in the off state;

[0108] S2: The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended submodule of the extended submodule unit is identified and confirmed according to the first module identification strategy;

[0109] The specific identification strategy of the first module is as follows:

[0110] If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light.

[0111] If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended sub-module is identified and step S3 is executed.

[0112] S3: When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, through the first tri-state gate driver G and the LC signal line in sequence, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module.

[0113] S4: The sub-controller MCU1 detects the low-level signal corresponding to the first input pin InLC1, obtains the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus;

[0114] The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule;

[0115] The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule via the CAN bus.

[0116] After the current extended submodule receives the CAN bus sign-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU.

[0117] Specifically, the main controller MCU of the main module is used for logic control of automatic identification and address allocation of the extended submodules of the extended submodule unit, and to realize data communication on the CAN bus and automatic identification / address allocation of the extended submodules. The input pin InLE of the main controller MCU is used to detect whether the extended submodule is identified; a high level indicates no identification, and a low level indicates identification. The output pin OE of the main controller MCU controls the output enable of the tri-state gate driver G to transmit commands to the extended submodules; a low-level signal indicates that the extended submodule is ready to start address allocation. The first pull-up resistor R1 and the second pull-up resistor R2 are used to keep the pin high before the main controller MCU is powered on and during power-on initialization, and the first tri-state gate driver G is used to drive the level signal transmission to the extended submodule of the extended submodule unit.

[0118] S5: The sub-controller MCU1 of the current extended sub-module continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, the next level extended sub-module of the current extended sub-module is identified based on the second module identification strategy.

[0119] The second module's identification strategy is as follows:

[0120] If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light.

[0121] If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended sub-module is identified and step S6 is executed.

[0122] S6: When the sub-controller MCU1 detects that the second input pin InLE1 is a low-level signal, it outputs a low level through the output pin OE of the sub-controller MCU1, and the second tri-state gate driver G1 is in the conducting state. Then, through the second tri-state gate driver G1 and the LC signal line, the low-level signal of the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module.

[0123] S7: The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus;

[0124] The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule;

[0125] The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level extended submodule based on the parameter information of the next-level current extended submodule, and transmits it to the next-level extended submodule through the CAN bus;

[0126] After receiving the CAN bus sign-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU.

[0127] Specifically, each expansion submodule of the expansion submodule unit includes a sub-controller MCUn (n is a positive integer), input pins InLCn and InLEn, an output pin OEn, pull-up resistors Rn1, Rn2, and Rn2 for the three pins, and a tri-state gate driver Gn. The sub-controller MCUn of the expansion submodule is used for address allocation logic control, implementing CAN bus data communication, and acquiring expansion submodule information. The input pin InLCn of the expansion submodule is used to receive address allocation commands from the previous master module or expansion submodule; a low-level signal indicates the start of address allocation. The input pin InLEn of the expansion submodule is used to detect whether the next-level expansion submodule is recognized; a high level indicates no recognition, and a low level indicates recognition. The output pin OEn of the expansion submodule controls the output enable of the tri-state gate driver Gn, which is used to transmit commands to the next-level expansion submodule. A low-level signal indicates that the next-level expansion submodule is ready to start address allocation. Pull-up resistors Rn1, Rn2, and Rn2 are used to keep the pin high before power-on and during power-on initialization of the sub-controller MCUn. The tri-state gate driver Gn is used to drive the level signal to the next-level expansion submodule. The module signal lines include two lines: LEn and LCn. Signal line LEn is the valid identification signal for the next-level expansion submodule; a high level indicates no identification, and a low level indicates identification. Signal line LCn is the address allocation command for the expansion submodule; a low-level signal indicates the start of address allocation.

[0128] The CAN bus is a differential communication line used to transmit CAN bus response messages for address allocation commands and CAN bus check-in messages for transmitting parameter information of each extended submodule in the extended submodule unit.

[0129] S8: Repeat S5 to S7 until the automatic identification and address allocation of the extended submodule in the extended submodule unit are completed.

[0130] In this embodiment, the automatic address allocation method for the vehicle controller's extended submodule is divided into a main module process and an extended submodule process based on the module carrier. The main module process mainly consists of initialization, detection and identification of extended submodules, identification and storage of extended submodule information, and address allocation. The extended submodule process mainly consists of initialization, detection and identification of preceding and following extended submodules, sending extended submodule information, and obtaining addresses.

[0131] Specifically, the main module process is as follows: After the main module powers on and initializes, it defines the InLE pin of the main controller MCU as a floating input and the OE pin as an output, outputting a high level. It continuously monitors the InLE state (i.e., the LE0 state of the module signal line). If the InLE state remains high for more than 1 second, the extended submodule is not recognized, and the process exits after handling an error. When the InLE state is low, the extended submodule is recognized, and the OE outputs a low level (i.e., the LC0 state is set low). After the OE outputs a low level, it waits to receive the CAN bus check-in message from the extended submodule. Upon receiving the check-in message, the extended submodule is recognized and its parameter information is stored. If no check-in message is received for more than 1 second, the process exits after handling an error. After the main controller MCU identifies the extended submodule, it replies with a CAN bus check-in response message. The check-in response message includes the communication address assigned to the extended submodule by the main module. The main controller MCU continues to wait to receive check-in messages from the extended submodule and confirms whether the current extended submodule is the last one based on the check-in message status. If the current extended submodule is the last module, the process of identifying the extended submodule and allocating the address ends. If the current extended submodule is not the last module, the main controller MCU switches to the state of waiting to receive check-in messages from the extended submodule. If the total time for the main controller MCU to receive CAN check-in messages from the extended submodule exceeds a preset time threshold, the extended submodule replies with a CAN check-in message to the main controller MCU again via the CAN bus. If the main controller MCU still fails to receive the message (the maximum number of failed receptions is 3), it performs extended submodule error handling and exits the process.

[0132] Extended Submodule Process: After the extended submodule powers on and initializes, it defines the InLEn and InLCn pins of the subcontroller MCUn as floating inputs and OEn as an output, outputting a high level. It continuously monitors the InLCn state (i.e., the LCn state of the module signal line). When InLCn is high, it indicates that the preceding extended submodule is not recognized or has not completed initialization; monitoring continues. When InLCn is low, it indicates that the main module or the preceding extended submodule recognizes it and can obtain an address. Simultaneously, after monitoring the InLEn state, it sends the extended submodule information and the monitored InLEn state (i.e., the LEn state of the module signal line) as an extended submodule check-in message to the main module via the CAN bus. After sending the check-in message, it waits for a reply from the main module. The main module's reply includes the address information allocated to the extended submodule. If the extended submodule times out (exceeding 1 second) upon receiving the main module's reply check-in message, it resends the check-in message. After the extended submodule completes the storage address information, it determines whether the current extended submodule is the last one based on the InLEn state. If the InLEn state is high, it means that the extended submodule is the last one and the extended submodule completes the address allocation process. If the InLEn state is low, it means that the extended submodule is not the last module and OEn needs to be output low before the address allocation process is completed.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An automatic identification and address allocation system for an on-board controller expansion submodule, characterized in that, It includes a main module, expansion sub-module units, multiple module signal lines, and a CAN bus; The main module is hardwired to the expansion submodule unit via module signal lines. The expansion submodule unit has multiple expansion submodules, and the expansion submodules are hardwired to each other via module signal lines. The main module communicates with each expansion submodule via a CAN bus. The main module includes a main controller MCU, a first pull-up resistor R1, a second pull-up resistor R2, and a first tri-state gate driver G; The main controller MCU's input pin InLE, one end of the second pull-up resistor R2, and one end of the LE signal line are connected, and the other end of the LE signal line is connected to the ground line set by the expansion submodule unit; the other end of the second pull-up resistor R2, one end of the first pull-up resistor R1, and the VCC terminal are connected. The output pin OE of the main controller MCU, the other end of the first pull-up resistor R1, and the control terminal of the first tri-state gate driver G are connected; the input terminal of the first tri-state gate driver G is grounded, and the output terminal of the first tri-state gate driver G is connected to the expansion sub-module unit through an LC signal line; Each module signal line includes an LE signal line and an LC signal line. The main module identifies the current extended submodule by detecting the level signal of the LE signal line of the current extended submodule directly connected to the main module; and identifies the next-level extended submodule by detecting the level signal of the LE signal line of the next-level extended submodule connected to the current extended submodule. The main module detects and obtains the level signal of the LE signal line of the current extended submodule, and sends a trigger level signal to the current extended submodule through the LC signal line. The trigger level signal is used to trigger the current extended submodule and feed back the parameter information of the current extended submodule to the main module via the CAN bus; Alternatively, the current expansion submodule can send a trigger level signal to the next-level expansion submodule via the LC signal line. The next-level expansion submodule, based on the received trigger level signal, feeds back its parameter information to the main module via the CAN bus. The parameter information includes interface data set according to the I / O interface type and quantity of the extended submodule; The main module issues address allocation instructions to each extended submodule based on the CAN bus feedback parameter information, and allocates addresses to each extended submodule according to the address allocation instructions to obtain the address allocation list of the extended submodules.

2. The automatic identification and address allocation system for an on-board controller expansion submodule according to claim 1, characterized in that, The specific implementation method for the main module to detect and identify the current extended sub-module is as follows: Define the extended submodule that is directly connected to the main module through the module signal line as the current extended submodule; the main module is initialized upon power-up, and the input pin InLE of the main controller MCU is defined as a floating input, the output pin OE of the main controller MCU is defined as a high level output, and the first tri-state gate driver G is in the off state; The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended sub-module is identified based on the first module identification strategy. The specific identification strategy of the first module is as follows: If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light. If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended submodule is confirmed to be identified. The method by which the main module allocates addresses to the current extended submodule is as follows: When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module through the first tri-state gate driver G and the LC signal line in sequence. The sub-controller MCU1 detects a low-level signal corresponding to the first input pin InLC1, acquires the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus. The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule; The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule through the CAN bus; After the current extended submodule receives the CAN bus sign-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU.

3. The automatic identification and address allocation system for an on-board controller expansion submodule according to claim 2, characterized in that, The expansion submodule unit includes multiple expansion submodules connected sequentially via module signal lines; The extended submodule includes a sub-controller MCU1, a third pull-up resistor R11, a fourth pull-up resistor R12, a fifth pull-up resistor R13, and a second tri-state gate driver G1; The output of the first tri-state gate driver G is connected to the first input pin InLC1 of the sub-controller MCU1, one end of the third pull-up resistor R11, and the input of the second tri-state gate driver G1 via an LC signal line. The control terminal of the second tri-state gate driver G1 is connected to the output pin OE1 of the sub-controller MCU1 and one end of the fourth pull-up resistor R12. The second input pin InLE1 of the sub-controller MCU1 and one end of the fifth pull-up resistor R13 are connected to the grounding wire of the multi-level expansion sub-module via an LE signal line. The other ends of the third pull-up resistor R11, the fourth pull-up resistor R12, and the fifth pull-up resistor R13 are connected to the VCC terminal. The output of the second tri-state gate driver G1 is connected to the next-level expansion sub-module via an LC signal line.

4. The automatic identification and address allocation system for an on-board controller expansion submodule according to claim 3, characterized in that, The specific implementation method for the current extended submodule to detect and identify the next-level extended submodule is as follows: The sub-controller MCU1 of the current extended sub-module continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of the continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, the next level extended sub-module of the current extended sub-module is identified based on the second module identification strategy. The second module's identification strategy is as follows: If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light. If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended submodule is confirmed to be identified. The method for the main module to allocate addresses to the next-level extended sub-modules is as follows: If the sub-controller MCU1 of the current expansion sub-module detects that the second input pin InLE1 is low, then the output pin OE of the sub-controller MCU1 of the current expansion sub-module is low, and the second tri-state gate driver G1 is in the conducting state. Then, the low-level signal at the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module through the second tri-state gate driver G1 and the LC signal line in sequence. The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus. The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule; The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level expansion submodule based on the parameter information of the next-level expansion submodule, and transmits it to the next-level expansion submodule through the CAN bus. After receiving the CAN bus sign-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU.

5. A method for automatically identifying and allocating addresses to an on-board controller extension submodule based on an automatic identification and address allocation system for an on-board controller extension submodule according to any one of claims 1-4, characterized in that, Includes the following steps: S1: The main module is powered on and initialized; the input pin InLE of the main controller MCU is defined as a floating input, the output pin OE of the main controller MCU is defined as a high level output, and the first tri-state gate driver G is in the off state; S2: The main controller MCU continuously detects the current level signal of the LE signal line connected to the main controller MCU and records the first cumulative duration of continuous detection; based on the first cumulative duration and the current level signal, the current extended submodule of the extended submodule unit is identified based on the first module identification strategy; The specific identification strategy of the first module is as follows: If the first cumulative duration exceeds the preset time threshold and the current level signal of the LE signal line is a high level signal, it is confirmed that the current extended sub-module has not been identified, and an error warning is issued by the main controller MCU through the module panel indicator light. If the first cumulative duration does not exceed the preset time threshold and the current level signal of the LE signal line is low, then the current extended sub-module is identified and step S3 is executed. S3: When the main controller MCU detects that the current level signal of the LE signal line is a low level signal, it outputs a low level through the output pin OE of the main controller MCU, and the first tri-state gate driver G is in the on state. Then, through the first tri-state gate driver G and the LC signal line in sequence, the low level signal at the input terminal of the first tri-state gate driver G of the main module is transmitted to the first input pin InLC1 of the sub-controller MCU1 of the current extended sub-module. S4: The sub-controller MCU1 detects the low-level signal corresponding to the first input pin InLC1, obtains the CAN bus check-in message, and transmits the CAN bus check-in message of the current extended sub-module to the main controller MCU through the CAN bus; The main controller MCU obtains and stores the parameter information of the current extended submodule based on the CAN bus check-in message of the current extended submodule; The main controller MCU generates a CAN bus check-in response message containing the communication address assigned to the current extended submodule based on the parameter information of the current extended submodule, and transmits it to the current extended submodule through the CAN bus; After the current extended submodule receives the CAN bus check-in response message, it obtains the latest response message. After the main controller MCU obtains the latest response message of the current extended submodule, it stores the communication address of the current extended submodule in the memory of the main controller MCU. S5: The sub-controller MCU1 continuously detects the current level signal of the corresponding second input pin InLE1 and records the second cumulative duration of continuous detection; based on the second cumulative duration and the current level signal of the second input pin InLE1, it confirms and identifies the next level expansion sub-module of the current expansion sub-module based on the second module identification strategy; The second module's identification strategy is as follows: If the second cumulative duration exceeds the preset time threshold, and the current level signal of the second input pin InLE1 is detected to be a high level signal, it is confirmed that the next-level expansion sub-module has not been identified, and alarm information is obtained based on the sub-controller MCU1 of the current expansion sub-module and transmitted to the main controller MCU. The main controller MCU issues an error warning through the module panel indicator light. If the second cumulative duration does not exceed the preset time threshold and the current level signal of the second input pin InLE1 is low, then the next-level extended sub-module is identified and step S6 is executed. S6: When the sub-controller MCU1 detects that the second input pin InLE1 is a low-level signal, it outputs a low level through the output pin OE of the sub-controller MCU1, and the second tri-state gate driver G1 is in the conducting state. Then, through the second tri-state gate driver G1 and the LC signal line, the low-level signal output from the input terminal of the second tri-state gate driver G of the current expansion sub-module is transmitted to the next-level first input pin InLC2 of the next-level expansion sub-module. S7: The sub-controller MCU2 of the next-level expansion sub-module detects the low-level signal of the corresponding next-level first input pin InLC2, obtains the CAN bus check-in message of the next-level expansion sub-module, and transmits the CAN bus check-in message of the next-level expansion sub-module to the main controller MCU through the CAN bus. The main controller MCU obtains and stores the parameter information of the next-level expansion submodule based on the CAN bus check-in message of the next-level expansion submodule; The main controller MCU generates a CAN bus check-in response message containing the communication address of the next-level expansion submodule based on the parameter information of the next-level expansion submodule, and transmits it to the next-level expansion submodule through the CAN bus. After receiving the CAN bus check-in response message, the next-level extension submodule obtains the latest response message. After obtaining the latest response message from the next-level extension submodule, the main controller MCU stores the communication address of the next-level extension submodule in the memory of the main controller MCU. S8: Repeat S5 to S7 until the automatic identification and address allocation of all extended submodules in the extended submodule unit are completed.

6. The method for automatic identification and address allocation system of vehicle controller expansion submodule according to claim 5, characterized in that, The CAN bus is a differential communication line used to transmit CAN bus response messages for address allocation commands; With CAN bus check-in messages used to transmit parameter information of each extended submodule in the extended submodule unit.

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