Over-temperature detection circuit and layout structure thereof

Abstract

An over-temperature detection circuit and a layout structure thereof, the over-temperature detection circuit comprising N BJT sets, N-1 resistors and an inverter, wherein N is an integer greater than 1; the BJT set comprises N BJTs; the collector of each BJT is connected to an external current bias; when n is any integer from 1 to N-1, the emitter of the nth BJT in each set is connected to ground via the (n-1)th resistor; the base of the first BJT in each set is connected to a reference voltage; when n is any integer from 2 to N, the base of the nth BJT in each set is connected to the emitter of the (n-1)th BJT; the voltage signal output by the collector of the Nth BJT in each set is inverted by the inverter to obtain a temperature indication signal; when n is any integer from 1 to N, the emitter, base and collector of the nth BJT in each set are connected together. The connection lines between the BJTs in the layout structure adopt 45° routing. The present application can flexibly set the size of the over-temperature threshold voltage, reduce the routing distance and reduce the parasitic effect.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more specifically to an over-temperature detection circuit and its layout structure. Background Technology

[0002] In IC chips, high temperatures can cause chip instability, reduced chip performance, and even chip damage. To prevent overheating, an over-temperature detection circuit needs to be designed inside the chip.

[0003] Existing over-temperature detection circuits typically consist of a temperature sensor and a comparator. The temperature sensor is usually a thermistor, such as a BJT (Bipolar Junction Transistor). The BJT's emitter junction forward voltage Vbe has a negative temperature characteristic, meaning that Vbe decreases as the temperature increases. The comparator compares the sensor's output voltage signal with a preset over-temperature threshold voltage signal. When the sensor's output voltage signal exceeds the over-temperature threshold voltage signal, the comparator outputs a high-level signal, triggering a protection circuit to cut off the power supply and protect the device.

[0004] The over-temperature threshold voltage signal in an over-temperature detection circuit typically needs to be set appropriately based on the chip's operating temperature range. However, the Vbe of the BJT and the series resistor, which affect the setting of the over-temperature threshold voltage signal, usually have limited adjustment ranges. Therefore, existing over-temperature detection circuits need to be improved to meet the requirement of more flexible over-temperature threshold voltage signal settings. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an over-temperature detection circuit and its layout structure, which allows for more flexible adjustment of the over-temperature threshold voltage, better ensures the operating state of the BJT used as a thermistor, and minimizes circuit parasitics through reasonable layout design, thereby improving the performance of the over-temperature detection circuit.

[0006] The present invention adopts the following technical solution.

[0007] According to a first aspect of the present invention, an over-temperature detection circuit is provided. The over-temperature detection circuit includes N BJT sets, N-1 resistors, and an inverter, where N is an integer greater than 1.

[0008] The BJT set includes N BJTs; the collector of each of the N BJTs is connected to an external current bias; when n is any integer from 1 to N-1, the emitter of the nth BJT in the N BJTs is grounded through the nth resistor of the N-1 resistors; the base of the 1st BJT in the N BJTs is connected to the over-temperature threshold voltage; when n is any integer from 2 to N, the base of the nth BJT in the N BJTs is connected to the emitter of the (n-1)th BJT; the voltage signal output from the collector of the Nth BJT in the N BJTs is inverted by the inverter to obtain the temperature detection signal; when n is any integer from 1 to N, the emitter, base, and collector of the nth BJT in each BJT set of the N BJTs are connected together.

[0009] Furthermore, N is 2 or 3.

[0010] Furthermore, the over-temperature detection circuit also includes a first switching transistor; wherein, the controlled terminal of the first switching transistor is connected to an enable signal, and the other two ports of the first switching transistor, excluding the controlled terminal, are respectively connected to the over-temperature threshold voltage and the base of the first BJT among the N BJTs.

[0011] Furthermore, the over-temperature detection circuit also includes a hysteresis regulation branch connected in parallel with one of the N-1 resistors; the hysteresis regulation branch includes a second switch and an additional resistor connected in series; the controlled terminal of the second switch is connected to the over-temperature indication signal.

[0012] Furthermore, the first switch and the second switch are MOSFETs.

[0013] According to a second aspect of the present invention, a layout structure for an over-temperature detection circuit according to a first aspect of the present invention is provided. The layout structure includes:

[0014] In an N×N array, when n is any integer from 1 to N, the nth BJT in each of the N BJT sets is distributed in different rows and columns of the N×N array.

[0015] Furthermore, the N×N array is represented as:

[0016]

[0017] Among them, A n This represents the nth BJT in each BJT set.

[0018] Furthermore, the connection lines between each BJT in the N×N array are routed at 45°.

[0019] Furthermore, the layout structure also includes a first type of connecting line extending along a first direction and a second type of connecting line extending along a second direction perpendicular to the first direction; wherein the angle between the first direction and the second direction and the row direction of the N×N array is 45°; when n is any integer from 1 to N, the first type of connecting line is used to connect the emitter, base, or collector of the nth BJT in each BJT set together; when n is any integer from 2 to N, the second type of connecting line is used to connect the base of the nth BJT in the N BJTs to the emitter of the (n-1)th BJT.

[0020] Furthermore, the layout structure also includes multiple dummy BJTs; the multiple dummy BJTs are evenly distributed on opposite sides or at each edge of the BJT array.

[0021] The beneficial effects of this invention are compared with those of the prior art:

[0022] 1. A configuration is established consisting of N BJT sets, N-1 resistors, and inverters, where N is an integer greater than 1 and each BJT set contains N BJTs. The collector of each BJT is connected to an external current bias. The emitters of the first N-1 BJTs are grounded via corresponding resistors in the N-1 resistors. The emitter of the Nth BJT is grounded. The base of the first BJT is connected to the over-temperature threshold voltage, and the base of the nth BJT is connected to the emitter of the (n-1)th BJT. The voltage signal output from the collector of the Nth BJT is inverted by the inverters to obtain the temperature indication signal. The emitter, base, and collector of the nth BJT in each BJT set are connected together. This allows for flexible matching of the over-temperature threshold voltage by appropriately setting the Vbe of each BJT and the resistance values ​​of the N-1 resistors. For example, when a higher over-temperature threshold voltage is required, the size of N can be increased, and the Vbe of multiple BJTs can be superimposed to match the higher over-temperature threshold voltage. Furthermore, by matching appropriate over-temperature threshold voltages and bias currents, the operating state of the three BJTs can be better ensured.

[0023] 2. The hysteresis magnitude can be adjusted by selecting the additional resistor in the hysteresis adjustment branch based on the over-temperature indication signal, thus avoiding frequent switching of the over-temperature indication signal.

[0024] 3. By designing the layout structure of the over-temperature detection circuit as an N×N array, and distributing the nth BJT in each of the N BJT sets in different rows and columns of the N×N array, and using 45° routing for the metal interconnects between the BJTs, the distribution of the metal interconnects can be more uniform while the routing distance is shorter. Shorter routing distance means less parasitic interference. This allows the over-temperature detection circuit using the layout structure of the present invention to achieve better performance compared to circuits with layout structures that typically use horizontal and vertical routing. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the over-temperature detection circuit of the present invention;

[0026] Figure 2 It is the technology used in the prior art Figure 1 Layout diagram of the over-temperature detection circuit;

[0027] Figure 3 This invention is used for Figure 1 Schematic diagram of the layout structure of the over-temperature detection circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0029] According to a first aspect of the present invention, an over-temperature detection circuit is provided. The over-temperature detection circuit includes N BJT sets, N-1 resistors, and an inverter, where N is an integer greater than 1.

[0030] The BJT set includes N BJTs; the collector of each of the N BJTs is connected to an external current bias; when n is any integer from 1 to N-1, the emitter of the nth BJT in the N BJTs is grounded through the nth resistor of the N-1 resistors; the base of the 1st BJT in the N BJTs is connected to the over-temperature threshold voltage; when n is any integer from 2 to N, the base of the nth BJT in the N BJTs is connected to the emitter of the (n-1)th BJT; the voltage signal output from the collector of the Nth BJT in the N BJTs is inverted by the inverter to obtain the temperature detection signal; when n is any integer from 1 to N, the emitter, base, and collector of the nth BJT in each BJT set of the N BJTs are connected together.

[0031] The emitter of the Nth BJT can be directly grounded or grounded via a resistor.

[0032] Preferably, N is 2 or 3, that is, each BJT set preferably includes 2 or 3 BJTs.

[0033] In a more preferred embodiment, the over-temperature detection circuit further includes a first switching transistor; wherein, the controlled terminal of the first switching transistor is connected to an enable signal, and the other two ports of the first switching transistor, excluding the controlled terminal, are respectively connected to the over-temperature threshold voltage and the base of the first BJT among the N BJTs.

[0034] In a more preferred embodiment, the over-temperature detection circuit further includes a hysteresis regulation branch connected in parallel with one of the N-1 resistors; the hysteresis regulation branch includes a second switch and an additional resistor connected in series; the controlled terminal of the second switch is connected to the over-temperature indication signal.

[0035] Preferably, the first and second switching transistors are MOSFETs. Accordingly, the controlled terminal of the MOSFET is the gate of the MOSFET.

[0036] Figure 1 A schematic diagram of the above-described over-temperature detection circuit is shown in one embodiment when N=3.

[0037] like Figure 1 As shown, the circuit includes three BJT sets, two resistors R1-R2, a first switch MN1, a second switch MN2, an additional resistor R1', and an inverter D.

[0038] Each BJT set includes three NPN type BJTs, designated A1, A2, and A3. The collector of each BJT in each set is connected to an external current bias Id. In this embodiment, Id is set to 5μA. In each BJT set, the emitter of the first BJT is grounded via resistor R1, the emitter of the second BJT is grounded via resistor R2, and the emitter of the third BJT is directly grounded. Resistors R1 and R2 have a resistance of 4MΩ, R2 has a resistance of 1MΩ, and an additional resistor R1' has a resistance of 1MΩ. Simultaneously, in each BJT set, the base of the first BJT is connected to the drain of the switching transistor S, the base of the second BJT is connected to the emitter of the first BJT, the base of the third BJT is connected to the emitter of the second BJT, and the collector of the third BJT (corresponding to...) Figure 1The voltage signal output from point Otp is inverted by inverter D to obtain the over-temperature indication signal OTP_OUT. The gate of the first switch MN1 is connected to the enable signal EN, and the source of the first switch MN1 is connected to the over-temperature threshold voltage VR. The gate of the second switch MN2 is connected to the over-temperature indication signal OTP_OUT, the source of the second switch MN2 is grounded, and the drain of the second switch MN2 is connected to one end of the additional resistor R1', the other end of R1' is connected to the emitter of the BJT corresponding to A1. The second switch MN2 and the additional resistor R1' connected in series form a hysteresis regulation branch. In this embodiment, VR is set to 1.125V. In addition, in the three BJT sets, the emitters, bases, and collectors of the three BJTs corresponding to A1 are connected together, the emitters, bases, and collectors of the three BJTs corresponding to A2 are connected together, and the emitters, bases, and collectors of the three BJTs corresponding to A3 are connected together.

[0039] It should be noted that although in this embodiment the external current bias Id is set to 5μA, the over-temperature threshold voltage is set to 1.125V, the reference voltage VR is set to 1.125V, R1 is set to 4MΩ, R2 is set to 1MΩ, and R1' is set to 1MΩ, this is not limiting. In fact, the present invention achieves a more flexible setting of the over-temperature threshold voltage signal VR by reasonably setting these component parameters.

[0040] The working principle of the above over-temperature detection circuit is as follows: When an over-temperature occurs, the temperature rises, and the emitter junction forward voltage Vbe of each BJT decreases. Because the base of the BJT corresponding to A1 is connected to the over-temperature threshold voltage VR, therefore... Figure 1 The potential at point a (i.e., the base of the BJT corresponding to A1) remains unchanged. Since the potential at point a remains constant, the potential at point b (i.e., the base of the BJT corresponding to A2) rises, and the potential at point c (i.e., the base of the BJT corresponding to A3) also rises. Finally, when the potential at point c rises to a level that causes the BJT corresponding to A3 to conduct, the voltage at its collector Otp drops, causing the over-temperature indication signal OTP_OUT to rise, indicating an over-temperature phenomenon in the area. This over-temperature indication signal can be used to trigger a protection circuit to cut off the power supply to protect the equipment.

[0041] In this embodiment, by providing N BJT sets and N-1 resistors, each BJT set includes N cascaded BJTs, and the n-th BJT in each BJT set is connected in parallel, so the magnitude of the over-temperature threshold voltage can be flexibly adjusted by properly setting the Vbe of each BJT and the resistance value of the N-1 resistors. For example, when a higher over-temperature threshold voltage is required, the value of N can be increased, and the superposition of Vbe of multiple BJTs is used to match the higher over-temperature threshold voltage. Furthermore, matching an appropriate over-temperature threshold voltage with a bias current can better ensure the working states of the three BJTs. In addition, the additional resistor R1' in the hysteresis adjustment branch can be selected through the second switching transistor MN2 according to the over-temperature indication signal to adjust the hysteresis magnitude, thereby avoiding frequent flipping of the over-temperature indication signal.

[0042] According to a second aspect of the present invention, there is provided a layout structure for an over-temperature detection circuit according to the first aspect of the present invention.

[0043] Figure 2 is a layout structure schematic diagram of an over-temperature detection circuit in the Figure 1 prior art. As Figure 2 shown, the layout structure includes a 3×3 array, and each array element corresponds to one BJT. The 3×3 array can be expressed as:

[0044]

[0045] In this layout structure, the layout of the region where each BJT is located includes three regions, that is, a rectangular emitter region 1 at the center, a C-shaped base region 2 in the middle, and a square-shaped collector region 3 at the outermost side. It can be seen from Figure 2 that the emitters of the three BJTs corresponding to A1 are connected together, the bases are connected together, and the collectors are also connected together. The three BJTs corresponding to A2 and the three BJTs corresponding to A3 also adopt the same connection mode as the three BJTs corresponding to A1. In addition, from Figure 2 it can also be seen that the bases of the three BJTs corresponding to A2 are connected to the emitters of the three BJTs corresponding to A1, and the bases of the three BJTs corresponding to A3 are connected to the emitters of the three BJTs corresponding to A2.

[0046] Furthermore, in the 3×3 array, the connecting lines between the three BJTs respectively corresponding to A1, A2 and A3 are parallel to the row direction of the array, and the connecting lines between A1 and A2 and between A2 and A3 are parallel to the column direction of the array.

[0047] However, this wiring mode that is parallel and perpendicular to the row direction may not minimize the length of the required metal connecting lines. As a result, additional parasitics will be introduced.

[0048] To overcome the aforementioned problems in the prior art, the present invention also improves the conventional layout structure of the over-temperature detection circuit. The improved layout structure includes an N×N array. Wherein, when n is any integer from 1 to N, the nth BJT in different BJT sets of the over-temperature detection circuit of the present invention is uniformly arranged at different rows and columns of the array.

[0049] Preferably, the N×N array can be represented as:

[0050]

[0051] Among them, A n This represents the nth BJT in each BJT set.

[0052] Furthermore, the connection lines between each BJT in the N×N array are routed at 45°.

[0053] More specifically, the layout structure of the over-temperature detection circuit of the present invention further includes a first type of connection line extending along a first direction and a second type of connection line extending along a second direction perpendicular to the first direction. The angle between the first direction and the second direction and the row direction of the N×N array is 45°. When n is any integer from 1 to N, the first type of connection line is used to connect the emitter, base, or collector of the nth BJT in all N BJT sets together. When n is any integer from 2 to N, the second type of connection line is used to connect the base of the nth BJT in the N BJTs to the emitter of the (n-1)th BJT.

[0054] Preferably, the layout structure also includes multiple dummy BJTs; these dummy BJTs are evenly distributed on opposite sides or edges of the BJT array. The dummy BJTs have the same structure as normal BJTs, except that they are not connected to perform the functions of normal BJTs. Dummy BJTs ensure manufacturability and prevent etching failures during chip manufacturing due to overexposure or underexposure.

[0055] Figure 3 This invention is used for Figure 1 Schematic diagram of the layout structure of the over-temperature detection circuit.

[0056] like Figure 3 This layout structure corresponds to the case where N=3, and includes the following 3×3 array:

[0057]

[0058] Where A1 represents the first BJT in the first to third BJT sets, A2 represents the second BJT in the first to third BJT sets, and A3 represents the third BJT in the first to third BJT sets.

[0059] and Figure 2 similar, Figure 3 Each BJT also includes an innermost emitter region, a middle base region, and an outermost collector region. However, compared to... Figure 2 The difference is that, in Figure 3 In the diagram, the connecting lines between the three BJTs corresponding to A1, A2, and A3 are parallel to direction L1, and the connecting lines between A1 and A2, and between A2 and A3, are parallel to direction L2. The angles between directions L1 and L2 and the row direction of the array are both 45°.

[0060] In addition, the layout structure also includes six dummy BJTs distributed on both sides of the aforementioned 3×3 array. The connecting lines between the dummy BJTs and between the dummy BJTs and the normal BJTs can be horizontal or vertical.

[0061] By comparison Figure 2 and Figure 3 It is understood that by distributing the nth BJT in each of the N BJT sets across different rows and columns of the N×N array, and simultaneously using 45° routing for the metal interconnects between the BJTs, a more uniform distribution of the metal interconnects can be ensured while reducing the routing distance. A shorter routing distance implies less parasitic capacitance. Furthermore, using 45° routing increases the spacing between adjacent interconnects, which reduces coupling between lines, thereby reducing parasitic capacitance between lines. As a result, the over-temperature detection circuit using the layout structure of this invention exhibits better performance compared to circuits with layout structures that typically use horizontal and vertical routing.

[0062] It should be noted that, Figure 2 and Figure 3 Only the BJT-related portion of the layout is shown; other components (such as resistors, switching transistors, etc.) included in the over-temperature detection circuit are not shown. The wiring for these other components can be horizontal, vertical, or, depending on the situation, at a 45° angle.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. An over-temperature detection circuit, characterized in that, It includes N sets of BJTs, N-1 resistors and inverters, where N is an integer greater than 1; Each of the N BJT sets comprises N BJTs; the collector of each of the N BJTs is connected to an external current bias; when n is any integer from 1 to N-1, the emitter of the nth BJT in the N BJTs is grounded via the nth resistor of the N-1 resistors; the base of the 1st BJT in the N BJTs is connected to the over-temperature threshold voltage; when n is any integer from 2 to N, the base of the nth BJT in the N BJTs is connected to the emitter of the (n-1)th BJT; the voltage signal output from the collector of the Nth BJT in the N BJTs is inverted by the inverter to obtain an over-temperature indication signal; when n is any integer from 1 to N, the emitter, base, and collector of the nth BJT in each of the N BJT sets are connected together.

2. The over-temperature detection circuit according to claim 1, characterized in that, N is 2 or 3.

3. The over-temperature detection circuit according to claim 1, characterized in that, It also includes a first switching transistor; wherein, the controlled terminal of the first switching transistor is connected to an enable signal, and the other two ports of the first switching transistor, excluding the controlled terminal, are respectively connected to the over-temperature threshold voltage and the base of the first BJT among the N BJTs.

4. The over-temperature detection circuit according to claim 3, characterized in that, It also includes a hysteresis regulation branch connected in parallel with one of the N-1 resistors; the hysteresis regulation branch includes a second switch and an additional resistor connected in series; the controlled terminal of the second switch is connected to the over-temperature indication signal.

5. The over-temperature detection circuit according to claim 4, characterized in that, The first and second switching transistors are MOSFETs.

6. A layout structure for an over-temperature detection circuit according to any one of claims 1-5, characterized in that, include: In an N×N array, when n is any integer from 1 to N, the nth BJT in each of the N BJT sets is distributed in different rows and columns of the N×N array.

7. The layout structure according to claim 6, characterized in that, The N×N array is represented as follows: in, Represents the first in each BJT set i One BJT.

8. The layout structure according to claim 7, characterized in that, The connection lines between each BJT in the N×N array are routed at 45°.

9. The layout structure according to claim 8, characterized in that, It also includes a first type of connecting line extending along a first direction and a second type of connecting line extending along a second direction perpendicular to the first direction; wherein the angle between the first direction and the second direction and the row direction of the N×N array is 45°; when n is any integer from 1 to N, the first type of connecting line is used to connect the emitter, base or collector of the nth BJT in each BJT set together; when n is any integer from 2 to N, the second type of connecting line is used to connect the base of the nth BJT in the N BJTs to the emitter of the (n-1)th BJT.

10. The layout structure according to claim 6, characterized in that, It also includes multiple dummy BJTs; the multiple dummy BJTs are evenly distributed on opposite sides or at each edge of the BJT array.

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