Time window adjustment circuit and driving method thereof, and laser radar

Abstract

The present disclosure provides a time window adjusting circuit, a driving method thereof and a laser radar. The time window adjusting circuit comprises a time window sub-circuit and an adaptive adjusting sub-circuit. The time window sub-circuit is configured to output a first time signal upon receiving a trigger signal, and is further configured to output a second time signal under the action of a control signal. The first time signal and the second time signal jointly constitute a time window signal. The adaptive adjusting sub-circuit is coupled to a control terminal of the time window sub-circuit. The adaptive adjusting sub-circuit is configured to adjust the control signal under different working conditions, and provide the control signal to the time window sub-circuit, so that a plurality of time window signals output by the time window sub-circuit have consistent time window lengths. The time window adjusting circuit provided by the present disclosure can make the plurality of time window signals output have consistent time window lengths, thereby improving the detection accuracy of the laser radar.

Description

Technical Field

[0001] This disclosure relates to the field of lidar technology, and in particular to a time window adjustment circuit and its driving method, and lidar. Background Technology

[0002] LiDAR is a system for detecting distance. The principle of LiDAR is to first emit a light signal towards the target object, then receive the reflected light signal. By detecting and processing the emitted and reflected light signals, information such as the detection distance can be obtained.

[0003] Currently, errors occur in the signal processing of LiDAR, such as filtering and noise reduction, when the received reflected light signals are processed, resulting in errors in the final detection distance. Summary of the Invention

[0004] The purpose of some embodiments of this disclosure is to provide a time window adjustment circuit and its driving method, and a lidar, which enables multiple time window signals output by the time window adjustment circuit based on the adaptive adjustment control signal to have a consistent time window length, reduce or even eliminate the jitter of the time window length, thereby improving the detection accuracy of the lidar.

[0005] To achieve the above objectives, some embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a time window adjustment circuit is provided. The time window adjustment circuit includes a time window sub-circuit and an adaptive adjustment sub-circuit. The time window sub-circuit is configured to output a first time signal upon receiving a trigger signal; and is further configured to output a second time signal under the action of a control signal. The first time signal and the second time signal together constitute a time window signal. The time difference between the first time signal and the second time signal is the time window length. The adaptive adjustment sub-circuit is coupled to the control terminal of the time window sub-circuit. The adaptive adjustment sub-circuit is configured to adjust the control signal under different operating conditions and provide the control signal to the time window sub-circuit so that the multiple time window signals output by the time window sub-circuit have a consistent time window length.

[0007] In some embodiments, the adaptive adjustment subcircuit includes a delay subcircuit and a phase adjustment subcircuit. The delay subcircuit is configured to receive a reference signal, perform delay processing on the reference signal, and output a last-position delayed signal. The phase adjustment subcircuit is coupled to the delay subcircuit. The phase adjustment subcircuit is configured to provide the control signal to the delay subcircuit based on the reference signal and the last-position delayed signal to adjust the delay amount of the delay processing, such that the phase of the last-position delayed signal and the phase of the reference signal remain consistent under different operating conditions. The phase adjustment subcircuit is also coupled to the control terminal of the time window subcircuit. The phase adjustment subcircuit is further configured to provide the control signal to the time window subcircuit to ensure that the multiple time window signals output by the time window subcircuit under different operating conditions have a consistent time window length.

[0008] In some embodiments, the phase adjustment subcircuit includes a phase detection module and a charge pump module. The input terminal of the phase detection module is coupled to a reference signal terminal and the output terminal of the delay subcircuit, respectively. The phase detection module is configured to receive the reference signal and the last-position delay signal, and output a comparison result between the phase of the reference signal and the phase of the last-position delay signal. The input terminal of the charge pump module is coupled to the output terminal of the phase detection module, and the output terminal of the charge pump module is coupled to the control terminal of the delay subcircuit. The charge pump module is configured to provide a control signal to the control terminal of the delay subcircuit based on the comparison result between the phase of the reference signal and the phase of the last-position delay signal to adjust the delay amount of the delay processing, so that the phase of the last-position delay signal and the phase of the reference signal remain consistent under different operating conditions. The output terminal of the charge pump module is also coupled to the control terminal of the time window subcircuit. The charge pump module is further configured to provide the control signal to the time window subcircuit so that the multiple time window signals output by the time window subcircuit under different operating conditions have a consistent time window length.

[0009] In some embodiments, the time window sub-circuit includes at least two delay units connected in series. Each delay unit delays a first signal received at its input and outputs a second signal, which is the result of delaying the first signal, at its output. The control terminal of each delay unit is coupled to the output of the phase adjustment sub-circuit.

[0010] In some embodiments, the delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor's first terminal is coupled to a power supply signal terminal, its control terminal is coupled to the input terminal of the delay unit, and its second terminal is coupled to a first node. The second transistor's first terminal is coupled to a power supply signal terminal, its control terminal is coupled to the first node, and its second terminal is coupled to the output terminal of the delay unit. The third transistor's first terminal is coupled to the first node, and its control terminal is coupled to the input terminal of the delay unit. The fourth transistor's first terminal is coupled to the second terminal of the second transistor, and its control terminal is coupled to the first node. The fifth transistor's first terminal is coupled to the second terminal of the third transistor, its control terminal is coupled to the output terminal of the phase adjustment sub-circuit, and its second terminal is coupled to ground. The sixth transistor's first terminal is coupled to the second terminal of the fourth transistor, its control terminal is coupled to the output terminal of the phase adjustment sub-circuit, and its second terminal is coupled to ground.

[0011] In some embodiments, the first transistor and the second transistor have the same channel type. The third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same channel type. The first transistor has an opposite channel type to the third transistor.

[0012] In some embodiments, the delay sub-circuit includes at least two delay sub-units connected in series. Each delay sub-unit delays the signal received at its input by a phase delay of one time and outputs a delayed signal. The control terminal of each delay sub-unit is coupled to the output terminal of the phase adjustment sub-circuit.

[0013] On another front, a driving method for a time window adjustment circuit is provided, applied to the time window adjustment circuit described above. The driving method includes: upon receiving a trigger signal, outputting a first time signal through the time window sub-circuit; providing a control signal to the time window sub-circuit through the adaptive adjustment sub-circuit under different operating conditions; and utilizing the time window sub-circuit to output a second time signal in response to the control signal, so that the multiple time window signals output by the time window sub-circuit have a consistent time window length. Wherein, the first time signal and the second time signal together constitute a time window signal, and the time difference between the first time signal and the second time signal is the time window length.

[0014] In some embodiments, providing control signals to the time window subcircuit through the adaptive adjustment subcircuit under different operating conditions includes: receiving a reference signal using the delay subcircuit, performing delay processing on the reference signal, and outputting a last-position delay signal. The phase adjustment subcircuit provides the control signal to the delay subcircuit based on the reference signal and the last-position delay signal to adjust the delay amount of the delay processing, so that the phase of the last-position delay signal and the phase of the reference signal remain consistent under different operating conditions. The phase adjustment subcircuit provides the control signal to the time window subcircuit so that the multiple time window signals output by the time window subcircuit under different operating conditions have a consistent time window length.

[0015] In another aspect, a lidar system is provided, comprising a transmitter, a receiver, and a processor. The transmitter is configured to transmit an optical signal toward a target object. The receiver is configured to receive a reflected optical signal. The processor is coupled to both the transmitter and the receiver. The processor includes the time window adjustment circuit described above. The processor is configured to perform noise reduction processing on the reflected optical signal to obtain the optical signal reflected back by the target object, and to determine the detection range based on the transmitted optical signal and the optical signal reflected back by the target object. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0017] Figure 1 This is a timing diagram of optical signal processing based on time window signals provided by a lidar according to some embodiments;

[0018] Figure 2 Here is a structural diagram of a lidar provided according to some embodiments;

[0019] Figure 3 This is a structural diagram of a time window adjustment circuit provided according to some embodiments;

[0020] Figure 4 This is a structural diagram of a time window adjustment circuit provided according to some embodiments;

[0021] Figure 5 This is a structural diagram of a phase detection module provided according to some embodiments;

[0022] Figure 6 This is a timing diagram of a phase detection module performing phase detection on a signal according to some embodiments;

[0023] Figure 7 This is a structural diagram of a charge pump module provided according to some embodiments;

[0024] Figure 8 This is a structural diagram of a delay unit provided according to some embodiments;

[0025] Figure 9 A flowchart of a driving method for a time window adjustment circuit according to some embodiments;

[0026] Figure 10 This is a flowchart of a driving method for a time window adjustment circuit according to some embodiments. Detailed Implementation

[0027] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0030] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0031] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0032] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0033] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0034] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0035] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0036] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0037] It should be noted that the transistors used in the circuit structures provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The transistors in the embodiments of this disclosure can be enhancement-mode transistors or depletion-mode transistors, and this disclosure does not set any limitations on them.

[0038] In the circuit structure, the control terminal of each transistor is the gate of the transistor, the first terminal is one of the source and drain of the transistor, and the second terminal is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second terminals of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first terminal is the source and the second terminal is the drain; for example, in the case of an N-type transistor, the first terminal is the drain and the second terminal is the source.

[0039] It should also be noted that the high potential signal and low potential signal mentioned in this disclosure are relative terms, that is, they only mean that the potential of the high potential signal is higher than that of the low potential signal, and do not limit the specific potential values ​​of the high potential and low potential.

[0040] Laser Radar (LiDAR) is short for laser detection and ranging system. LiDAR emits a light signal towards a target object and then receives the reflected light signal, measuring the optical path. In practical applications, the reflected light signal received by the LiDAR includes not only the light reflected from the target object but also noise reflected from other objects in the surrounding environment or other sources. Therefore, noise reduction and filtering are necessary to process the reflected light signal to obtain the light signal reflected from the target object. Based on the emitted and reflected light signals, detection data such as the target object's azimuth, height, velocity, attitude, and even shape can be obtained. For example, the optical path difference can be calculated by detecting the time difference between the emission and reflection of the light signal, thus determining the distance of the LiDAR to the target object.

[0041] In lidar, signal processing such as noise reduction and filtering of reflected light signals can be performed, including threshold judgment of the received reflected light signals. A suitable threshold can be adjusted based on lidar system test data. Light signals exceeding the threshold are considered to be reflected light signals from a target object and optical path measurements are performed; otherwise, they are considered optical noise and no optical path measurement is performed.

[0042] For example, a single-photon avalanche diode (SPAD) detector in a lidar system can detect individual photons of the received reflected light signal and output the pulse signal characteristics of each photon. By recording the number of pulses output by the SPAD detector, the number of photons in the received reflected light signal can be counted. Based on the photon count per unit time, the magnitude and intensity of the light signal can be characterized. Furthermore, by applying a threshold to the received reflected light signal, the light signal reflected from the target object can be filtered out.

[0043] It should be noted that threshold determination for optical signals needs to be performed within a stable time window to ensure accuracy. A stable time window can be understood as one where each time window has a consistent length; for example, the time difference between the start and end times of a time window is stable.

[0044] The time window length can be understood as the duration of the valid signal when the threshold signal switches from an invalid level signal (e.g., a low level signal) to a valid level signal (e.g., a high level signal). The time window length can also be understood as the time difference between the start and end times of the time window. Specifically, the start time of the time window can be the moment when the threshold signal switches from an invalid level signal to a valid level signal, and the end time of the time window can be the moment when the threshold signal switches from a valid level signal to an invalid level signal.

[0045] The stability of the start and end times of a time window can include the case where the phase of the start signal of each time window is consistent with the phase of the end signal of each time window.

[0046] However, the length of the time window can vary due to factors such as process angle, power supply voltage, or temperature. If the length of the time window varies significantly with these factors, the number of photons collected will also vary considerably.

[0047] In some embodiments, such as Figure 1 As shown, Spad+Noise represents the received reflected light signal, which includes the light noise indicated by the dashed arrow and the light signal reflected back by the target object, indicated by the solid arrow; Window represents the time window signal pulse for threshold judgment, and Stop_NFC represents the light signal reflected back by the target object after threshold judgment and noise filtering. Specifically, only two photons are counted in the reflected light signal collected within the first time window length t1; however, three photons are counted in the second time window length t2.

[0048] Thus, under different operating conditions, the length of the time window used by the lidar to judge the received light signal through the threshold changes due to factors such as process angle, power supply voltage or temperature. This causes a deviation in the result of whether the detected light signal is the light signal reflected back by the target object, resulting in errors in the final detection data such as the detection distance.

[0049] Figure 2 This is a structural diagram of a lidar provided according to some embodiments.

[0050] In some embodiments, such as Figure 2 As shown, the lidar 1000 includes a transmitter 100, a receiver 200, and a processor 300. The processor 300 is coupled to both the transmitter 100 and the receiver 200.

[0051] For example, the processor 300 can be connected to the transmitter 100 and the receiver 200 via wired or wireless communication, respectively. The wireless communication connection may include, but is not limited to, Bluetooth connection, wireless network connection, etc.

[0052] The transmitter 100 is configured to emit an optical signal toward a target object. The transmitter 100 may include a laser transmitter, such as an infrared laser, a light-emitting diode laser, a carbon dioxide laser, a neodymium-doped yttrium aluminum garnet laser, a semiconductor laser, and a wavelength-tunable solid-state laser.

[0053] Receiver 200 is configured to receive reflected light signals. Receiver 200 may include photodetectors such as laser receivers, or combinations of photomultiplier tubes, semiconductor photodiodes, avalanche photodiodes, infrared and visible light multi-element detectors.

[0054] The processor 300 is configured to obtain the light signal reflected back by the target object by performing noise reduction processing on the reflected light signal, and to determine the detection distance based on the emitted light signal and the light signal reflected back by the target object.

[0055] In some embodiments, such as Figure 2 As shown, the processor 300 may include a time window adjustment circuit 30. For example... Figure 3 As shown, the time window adjustment circuit 30 includes an adaptive adjustment sub-circuit 31 and a time window sub-circuit 33. The control terminals of the adaptive adjustment sub-circuit 31 and the time window sub-circuit 33 are coupled. In practical circuits, the adaptive adjustment sub-circuit 31 can be a delay lock loop (DLL).

[0056] The time window sub-circuit 33 is configured to output a first time signal upon receiving a trigger signal. The trigger signal can be an electrical signal output by the photoelectric device (e.g., a photoelectric sensor) in the lidar in response to an optical signal. The first time signal can be understood as the signal that switches the time window signal from an invalid level signal to an valid level signal.

[0057] The time window sub-circuit 33 is also configured to output a second time signal under the action of a control signal. The second time signal can be understood as the signal that switches the time window signal from an active level signal to an inactive level signal. The first time signal and the second time signal together constitute the time window signal, wherein the time difference between the first time signal and the second time signal is the time window length.

[0058] Understandably, the input terminal of the time window sub-circuit 33 is configured to receive a trigger signal, the control terminal of the time window sub-circuit 33 is configured to receive a control signal, and the output terminal of the time window sub-circuit 33 is configured to output a time window signal corresponding to the control signal.

[0059] The adaptive adjustment sub-circuit 31 is configured to adjust the control signal under different operating conditions and provide a control signal to the time window sub-circuit 33 so that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length.

[0060] Understandably, the output of the adaptive regulation sub-circuit 31 is coupled to the control terminal of the time window sub-circuit 33. The control signal may include, but is not limited to, voltage signals, current signals, etc.

[0061] The adaptive adjustment sub-circuit 31 can adaptively adjust the control signal under different operating conditions. The time window sub-circuit 33 can output multiple time window signals with consistent time window lengths based on the adaptively adjusted control signal. This can reduce or even eliminate the jitter of the time window length, avoid the time window length from changing with process angle, power supply voltage, temperature, etc., reduce or even eliminate the error when the lidar performs noise reduction and other signal processing on the optical signal, thereby improving the detection accuracy of the lidar.

[0062] For example, when the temperature causes the time window length to shorten, the control signal output by the adaptive adjustment sub-circuit 31 can extend the time window length to overcome the influence of temperature on the time window length and maintain the stability of the time window length.

[0063] In some embodiments, such as Figure 4 As shown, the adaptive adjustment sub-circuit 31 includes a delay sub-circuit 310 and a phase adjustment sub-circuit 320.

[0064] The delay sub-circuit 310 is configured to receive a reference signal, delay the reference signal, and output a last-bit delayed signal. Understandably, the input terminal of the delay sub-circuit 310 is coupled to the reference signal terminal. The reference signal terminal can be an external signal terminal, and this is not limited here.

[0065] It should be noted that the reference signal can be a clock reference signal with one cycle, for example, the reference signal can be the clock reference signal of one range detection cycle of the lidar.

[0066] In some examples, such as Figure 4 As shown, the delay sub-circuit 310 includes at least two delay sub-units 311 connected in series. It can be understood that the delay sub-circuit 310 includes two or more delay sub-units 311 connected in series. Each delay sub-unit 311 performs a phase delay of one time on the signal received at its input terminal and outputs a delayed signal.

[0067] Each delay subunit 311 can perform delay processing on the signal received at its input terminal in the same way, which can be understood as the phase delay amount of each delay subunit 311 performing delay processing being equal.

[0068] For example, the delay sub-circuit 310 includes two delay sub-units 311 connected in series, namely, a first delay sub-unit 311 and a last delay sub-unit 311 connected in series. The input terminal of the first delay sub-unit 311 is coupled to a reference signal terminal; the first delay sub-unit 311 is configured to receive a reference signal from the reference signal terminal and output a first delayed signal after performing a delay processing of 1 times the phase delay of the reference signal. The input terminal of the last delay sub-unit 311 is coupled to the output terminal of the first delay sub-unit 311; the last delay sub-unit 311 is configured to receive the first delayed signal and output a last delayed signal after performing a delay processing of 1 times the phase delay of the first delayed signal, that is, output a last delayed signal after performing a delay processing of 2 times the phase delay of the reference signal.

[0069] It should be noted that the first delay subunit 311 and the last delay subunit 311 in the aforementioned delay subunit 311 are determined according to the order in which the signal flows through the delay subcircuit 310. Understandably, the first delay subunit 311 is the first delay subunit 311 in the delay subcircuit 310 to undergo delay processing for the reference signal; the last delay subunit 311 is the last delay subunit 311 in the delay subcircuit 310 to undergo delay processing for the reference signal. The last delayed signal is the delayed signal output by the last delay subunit 311 after delay processing.

[0070] For example, the delay sub-circuit 310 includes N (N is an integer greater than 2) delay sub-units 311 connected in series. That is, the delay sub-circuit 310 includes a first delay sub-unit 311 (i.e., the first delay sub-unit 311), a second delay sub-unit 311, ... and an Nth delay sub-unit 311 (i.e., the last delay sub-unit 311) connected in series. The input terminal of the first delay sub-unit 311 is coupled to a reference signal terminal. The first delay sub-unit 311 is configured to receive a reference signal from the reference signal terminal and output a first delayed signal after delaying the reference signal by one time phase. The input terminal of the second delay sub-unit 311 is coupled to the output terminal of the first delay sub-unit 311. The second delay sub-unit 311 is configured to receive the first delayed signal and output a second delayed signal after delaying the reference signal by two times phase. Similarly, the input terminal of the Nth delay sub-unit 311 is coupled to the output terminal of the (N-1)th delay sub-unit 311. The Nth delay sub-unit 311 is configured to receive the (N-1)th delay signal and output the last delay signal after the reference signal has been delayed by N times the phase delay amount.

[0071] It should be noted that when the adaptive adjustment sub-circuit 31 is a delay chain phase-locked loop, the delay sub-circuit 310 can be understood as the delay chain in the delay chain phase-locked loop.

[0072] In some examples, the delay subunit 311 can be a voltage-controlled delay subunit 311, that is, the phase delay amount of the delay subunit 311 can be changed by adjusting the voltage value of the delay control voltage at the control terminal of the delay subunit 311, so that the phase of the delay signal output by the delay subunit 311 is leading or lagging.

[0073] Phase adjustment sub-circuit 320 is coupled to delay sub-circuit 310. Phase adjustment sub-circuit 320 is configured to provide control signals to delay sub-circuit 310 based on reference signal and last-bit delay signal to adjust the delay amount of delay processing, so that the phase of last-bit delay signal and the phase of reference signal remain consistent under different operating conditions.

[0074] In some examples, the input of the phase adjustment sub-circuit 320 is coupled to the reference signal terminal and the output of the delay sub-circuit 310, respectively, and the output of the phase adjustment sub-circuit 320 is coupled to the control terminal of the delay sub-circuit 310. Understandably, the input of the phase adjustment sub-circuit 320 is coupled to the reference signal terminal and the output of the last delay sub-unit 311, respectively, and the output of the phase adjustment sub-circuit 320 is coupled to the control terminal of each delay sub-unit 311.

[0075] After receiving the reference signal and the last-position delay signal, the phase adjustment sub-circuit 320 compares the phase of the last-position delay signal with the phase of the reference signal to obtain one of three comparison results: the phase of the last-position delay signal lags behind the phase of the reference signal, the phase of the last-position delay signal leads the phase of the reference signal, or the phase of the last-position delay signal is equal to the phase of the reference signal.

[0076] For example, if the comparison result output by the phase adjustment sub-circuit 320 is that the phase of the last delayed signal lags behind the phase of the reference signal, the phase adjustment sub-circuit 320 can adjust the control signal (e.g., voltage control signal) provided to the delay sub-circuit 310 so that the phase of the last delayed signal output by the last delayed sub-unit 311 is shifted forward, thereby making the phase of the last delayed signal equal to the phase of the reference signal.

[0077] For example, the delay sub-circuit 310 includes three delay sub-units 311: a first delay sub-unit 311, a middle delay sub-unit 311, and a last delay sub-unit 311. The output terminal of the phase adjustment sub-circuit 320 is coupled to the control terminals of the first delay sub-unit 311, the middle delay sub-unit 311, and the last delay sub-unit 311, respectively. When the phase of the last delayed signal output by the last delay sub-unit 311 lags behind the phase of the reference signal, the phase adjustment sub-circuit 320 can adjust the control signal provided to the delay sub-circuit 310 to shift the phase of the first delayed signal output by the first delay sub-unit 311 forward by a phase adjustment amount of 1, shift the phase of the middle delayed signal output by the middle delay sub-unit 311 forward by a phase adjustment amount of 2, and shift the phase of the last delayed signal output by the last delay sub-unit 311 forward by a phase adjustment amount of 3. One-times phase adjustment can be one-third of the phase difference between the last-order delay signal and the reference signal.

[0078] For example, if the comparison result output by the phase adjustment sub-circuit 320 is that the phase of the last delayed signal leads the phase of the reference signal, the phase adjustment sub-circuit 320 can adjust the control signal (e.g., voltage control signal) provided to the delay sub-circuit 310 so that the phase of the last delayed signal output by the last delayed sub-unit 311 is shifted backward, thereby making the phase of the last delayed signal equal to the phase of the reference signal.

[0079] For example, if the comparison result output by the phase adjustment sub-circuit 320 is that the phase of the last delayed signal is equal to the phase of the reference signal, the phase adjustment sub-circuit 320 can keep the control signal (e.g., voltage control signal) provided to the delay sub-circuit 310 unchanged, so that the phase of the last delayed signal and the phase of the reference signal remain consistent under different operating conditions.

[0080] The phase adjustment subcircuit 320 is also coupled to the control terminal of the time window subcircuit 33. The phase adjustment subcircuit 320 is also configured to provide a control signal to the time window subcircuit 33 so that the multiple time window signals output by the time window subcircuit 33 under different operating conditions have a consistent time window length.

[0081] Understandably, the input terminal of the phase adjustment sub-circuit 320 is coupled to the reference signal terminal and the output terminal of the delay sub-circuit 310, respectively, and the output terminal of the phase adjustment sub-circuit 320 is coupled to the control terminal of the delay sub-circuit 310 and the control terminal of the time window sub-circuit 33, respectively. Based on the comparison result between the phase of the reference signal and the phase of the last delayed signal, the phase adjustment sub-circuit 320 outputs a control signal that ensures the phase of the last delayed signal and the phase of the reference signal remain consistent under different operating conditions. The phase adjustment sub-circuit 320 also provides this control signal to the control terminals of the delay sub-circuit 310 and the time window sub-circuit 33, respectively, so that the phase of the last delayed signal and the phase of the reference signal remain consistent under different operating conditions, and also that the phase of the input terminal and the phase of the output terminal of the time window sub-circuit 33 remain consistent, thereby ensuring that the multiple time window signals output by the time window sub-circuit 33 under different operating conditions have a consistent time window length.

[0082] Because the delay sub-circuit 310 is also affected by external factors such as process time, power supply voltage, temperature, and humidity, the phase of the last delayed signal is inconsistent with the phase of the reference signal. The phase adjustment sub-circuit 320 adjusts the phase delay of the delay sub-circuit 310 through a control signal, so that the phase of the last delayed signal is consistent with the phase of the reference signal, thus overcoming the influence of external factors on the phase delay of the delay sub-circuit 310 under different operating conditions. Therefore, the control signal can also adjust the unit delay of the time window sub-circuit 33 to overcome the influence of external factors on the unit delay of the time window sub-circuit 33 under different operating conditions, reduce or even eliminate the jitter of the time window length, and thus reduce or even eliminate the error of the lidar 1000 in noise reduction and other signal processing of the received reflected light signal, thereby improving the detection accuracy of the lidar 1000.

[0083] In some embodiments, such as Figure 4 As shown, the phase adjustment sub-circuit 320 includes a phase detection module 321 and a charge pump module 322.

[0084] The input terminals of the phase detection module 321 are coupled to the reference signal terminal and the output terminal of the delay sub-circuit 310, respectively. Understandably, the input terminals of the phase detection module 321 are also coupled to the reference signal terminal and the output terminal of the last-position delay sub-unit 311, respectively. The phase detection module 321 is configured to receive the reference signal and the last-position delay signal, and output a comparison result between the phases of the reference signal and the last-position delay signal.

[0085] After receiving the reference signal and the last-position delay signal, the phase detection module 321 compares the phase of the last-position delay signal with the phase of the reference signal to obtain one of three comparison results: the phase of the last-position delay signal lags behind the phase of the reference signal, the phase of the last-position delay signal leads the phase of the reference signal, or the phase of the last-position delay signal is equal to the phase of the reference signal.

[0086] In some examples, the phase detection module 321 may include a phase-detected (PD) sensor. For example... Figure 5 and Figure 6 As shown, Delay(0) and Delay(2N) are input to the phase detection module 321. Delay(0) is equivalent to the reference signal and Delay(2N) is equivalent to the last bit delay signal. The phase detection module 321 can detect the phase difference between the last bit delay signal and the reference signal, and output the UP signal, DN signal or reset signal according to the phase difference.

[0087] For example, such as Figure 6 As shown, if the phase detection module 321 detects that the phase of the last delayed signal leads the phase of the reference signal, the phase detection module 321 outputs an UP signal corresponding to the phase difference between the last delayed signal and the reference signal.

[0088] For example, if the phase detection module 321 detects that the phase of the last-position delay signal lags behind the phase of the reference signal, the phase detection module 321 outputs a DN signal corresponding to the phase difference between the last-position delay signal and the reference signal.

[0089] For example, if the phase detection module 321 detects that the phase of the last-bit delay signal is equal to the phase of the reference signal, the phase detection module 321 outputs a reset signal rst.

[0090] The input terminal of charge pump module 322 is coupled to the output terminal of phase detection module 321, and the output terminal of charge pump module 322 is coupled to the control terminal of delay sub-circuit 310. Understandably, the output terminal of charge pump module 322 is coupled to the control terminal of each delay sub-unit 311. Charge pump module 322 is configured to provide a control signal to the control terminal of delay sub-circuit 310 based on a comparison between the phase of the reference signal and the phase of the last delayed signal, thereby adjusting the delay amount of the delay processing so that the phase of the last delayed signal and the phase of the reference signal remain consistent under different operating conditions.

[0091] In some examples, such as Figure 7As shown, the charge pump module 322 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is configured to receive an UP signal or a reset signal output by the phase detection module 321. The second input terminal is configured to receive a DN signal or a reset signal output by the phase detection module 321. The output terminal is configured to output a corresponding control signal based on the UP signal, DN signal, or reset signal.

[0092] For example, if the first input terminal receives the UP signal output by the phase detection module 321, the charge pump module 322 adjusts the output control signal to increase the phase delay of the last delay signal so that the phase of the last delay signal is consistent with the phase of the reference signal.

[0093] For example, if the second input terminal receives the DN signal output by the phase detection module 321, the charge pump module 322 adjusts the output control signal to reduce the phase delay of the last delay signal, so that the phase of the last delay signal is consistent with the phase of the reference signal.

[0094] For example, if the first input terminal or the second input terminal receives a reset signal output by the phase detection module 321, the charge pump module 322 maintains the control signal unchanged to ensure that the phase of the last-bit delay signal is consistent with the phase of the reference signal.

[0095] like Figure 4 As shown, the output of the charge pump module 322 is also coupled to the control terminal of the time window sub-circuit 33. The charge pump module 322 is also configured to provide a control signal to the time window sub-circuit 33 so that the multiple time window signals output by the time window sub-circuit 33 under different operating conditions have a consistent time window length.

[0096] Understandably, the phase detection module 321 provides a UP signal, a DN signal, or a reset signal to the charge pump module 322 based on the phase difference between the last-position delay signal and the reference signal. The charge pump module 322 then provides control signals to the delay sub-circuit 310 and the time window sub-circuit 33 based on the UP signal, DN signal, or reset signal.

[0097] In this way, the charge pump module 322 adjusts the control signal in a negative feedback manner based on the phase difference between the last delay signal and the reference signal, so that the phase difference between the last delay signal and the reference signal is zero, and the phase of the trigger signal is consistent with the phase of the time window signal. The control signal can be adaptively adjusted according to different operating conditions, so that the multiple time window signals output by the time window sub-circuit 33 under different operating conditions have a consistent time window length. The time window length does not change with the change of operating conditions, so that the detection results of the lidar 1000 are accurate and stable.

[0098] In some embodiments, such as Figure 4 As shown, the time window sub-circuit 33 includes at least two delay units 330 connected in series. It can be understood that the time window sub-circuit 33 includes two delay units 330 connected in series, or the time window sub-circuit 33 includes two or more delay units 330 connected in series.

[0099] Each delay unit 330 delays the first signal received at its input terminal and outputs a second signal with the first signal delayed through its output terminal. The control terminal of each delay unit 330 is coupled to the output terminal of the phase adjustment sub-circuit 320. Understandably, the control terminal of each delay unit 330 is coupled to the output terminal of the charge pump module 322, and each delay unit 330 delays the first signal in response to the control signal output by the charge pump module 322.

[0100] It should be noted that each delay unit 330 can perform delay processing on the first signal received at its input terminal in the same way, which can be understood as the unit delay amount of each delay unit 330 performing delay processing being equal.

[0101] In some examples, such as Figure 4 As shown, the time window sub-circuit 33 includes two delay units 330 connected in series, namely, a first delay unit 330 and a last delay unit 330 connected in series. The input terminal of the first delay unit 330 is coupled to the trigger signal terminal, and the control terminal of the first delay unit 330 is coupled to the output terminal of the charge pump module 322. The first delay unit 330 is configured to receive a trigger signal (i.e., the first signal corresponding to the first delay unit 330) from the trigger signal terminal, and in response to the control signal output by the charge pump module 322, output a trigger delay signal (i.e., the second signal corresponding to the first delay unit 330) after delaying the trigger signal by one unit delay. The input terminal of the last delay unit 330 is coupled to the output terminal of the first delay unit 330, and the control terminal of the last delay unit 330 is coupled to the output terminal of the charge pump module 322. The last delay unit 330 is configured to receive the trigger delay signal (i.e., the first signal corresponding to the last delay unit 330) and, in response to the control signal output by the charge pump module 322, output a time window signal (i.e., the second signal corresponding to the last delay unit 330) after the trigger delay signal is delayed by 1 unit delay (equivalent to delaying the trigger signal by 2 unit delay).

[0102] It should be noted that the first delay unit 330 and the last delay unit 330 in the aforementioned time window sub-circuit 33 are determined based on the order in which the signal flows through the time window sub-circuit 33. Understandably, the first delay unit 330 is the first delay unit 330 in which the signal undergoes delay processing within the time window sub-circuit 33; the last delay unit 330 is the last delay unit 330 in which the signal undergoes delay processing within the time window sub-circuit 33.

[0103] In other examples, the time window subcircuit 33 includes three delay units 330 connected in series: a first delay unit 330, a middle delay unit 330, and a last delay unit 330. The input of the first delay unit 330 is coupled to a first signal terminal, and its control terminal is coupled to the output of the charge pump module 322. The first delay unit 330 is configured to receive a first signal from the first signal terminal and, in response to a control signal output by the charge pump module 322, output a second signal after delaying the first signal by one unit delay. The input of the middle delay unit 330 is coupled to the output of the first delay unit 330, and its control terminal is coupled to the output of the charge pump module 322. The middle delay unit 330 is configured to receive the second signal and, in response to a control signal output by the charge pump module 322, output a third signal after delaying the second signal by one unit delay (equivalent to delaying the first signal by two unit delays). The input terminal of the last delay unit 330 is coupled to the output terminal of the middle delay unit 330, and the control terminal of the last delay unit 330 is coupled to the output terminal of the charge pump module 322. The last delay unit 330 is configured to receive a third signal and, in response to the control signal output by the charge pump module 322, output a time window signal after delaying the third signal by one unit delay (equivalent to delaying the first signal by three units delay).

[0104] In some examples, the delay unit 330 can be a voltage-controlled delay unit, that is, the unit delay amount of the delay unit 330 can be changed by adjusting the voltage value of the delay control voltage at the control terminal of the delay unit 330, so as to adjust the phase of the delay signal output by the delay unit 330, and make the time window lengths of the multiple time window signals output by the time window sub-circuit 33 consistent.

[0105] In some embodiments, such as Figure 8 As shown, the delay unit 330 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

[0106] The first electrode of the first transistor M1 is coupled to the power supply signal terminal VDD, the control electrode of the first transistor M1 is coupled to the input terminal IN of the delay unit 330, and the second electrode of the first transistor M1 is coupled to the first node A.

[0107] The first electrode of the second transistor M2 is coupled to the power supply signal terminal VDD, the control electrode of the second transistor M2 is coupled to the first node A, and the second electrode of the second transistor M2 is coupled to the output terminal OUT of the delay unit 330.

[0108] The first electrode of the third transistor M3 is coupled to the first node A, and the control electrode of the third transistor M3 is coupled to the input terminal IN of the delay unit 330.

[0109] The first terminal of the fourth transistor M4 is coupled to the second terminal of the second transistor M2, and the control terminal of the fourth transistor M4 is coupled to the first node A. Understandably, the first terminal of the fourth transistor M4 is coupled to the output terminal OUT of the delay unit 330.

[0110] The first terminal of the fifth transistor M5 is coupled to the second terminal of the third transistor M3, the control terminal of the fifth transistor M5 is coupled to the output terminal of the phase adjustment sub-circuit 320, and the second terminal of the fifth transistor M5 is coupled to the ground terminal GND.

[0111] The first terminal of the sixth transistor M6 is coupled to the second terminal of the fourth transistor M4, the control terminal of the sixth transistor M6 is coupled to the output terminal of the phase adjustment sub-circuit 320, and the second terminal of the sixth transistor M6 is coupled to the ground terminal GND.

[0112] Among them, there is a parasitic capacitance C1 at the first node A, and a parasitic capacitance C2 at the output terminal of the delay unit 330, which is coupled to the second terminal of the second transistor M2 and the first terminal of the fourth transistor M4.

[0113] In some examples, the first transistor M1 and the second transistor M2 have the same channel type; the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 have the same channel type; and the first transistor M1 has the opposite channel type to the third transistor M3.

[0114] In this configuration, one of the first transistor M1 and the third transistor M3 can be a PMOS transistor, and the other can be an NMOS transistor, thus expanding the selection range of the first transistor M1 and the third transistor M3. For example, the first transistor M1 and the second transistor M2 are PMOS transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors. Alternatively, the first transistor M1 and the second transistor M2 are NMOS transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are PMOS transistors.

[0115] For ease of explanation, this section combines... Figure 8 The specific embodiments shown will be described in detail.

[0116] For example, in Figure 8 In the example shown, the first transistor M1 and the second transistor M2 are PMOS transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors.

[0117] A low-level trigger signal is input to the input terminal IN of the delay unit 330. The first transistor M1 is turned on, and the third transistor M3 is turned off. The high-level signal provided by the power supply signal terminal VDD flows through the first transistor M1 to the first node A to charge the parasitic capacitance C1. The first node A is equivalent to the output terminal of the inverter including the first transistor M1. At this time, the on-resistance of the first transistor M1 is the charging resistance of the parasitic capacitance C1, and the on-resistance of the first transistor M1 is relatively fixed.

[0118] The operating mechanism of the second transistor M2 is the same as that of the first transistor M1, and will not be elaborated here.

[0119] A high-level trigger signal is input to the input terminal IN of delay unit 330, turning off the first transistor M1 and turning on the third transistor M3. A high-level control signal is also input to the control terminal of the fifth transistor M5, turning it on. The first node A is connected to ground GND, discharging the parasitic capacitance C1. The first node A is equivalent to the output terminal of an inverter including the third transistor M3 and the fifth transistor M5. At this time, the on-resistance of the third transistor M3 and the fifth transistor M5 is the discharge resistance of the parasitic capacitance C1. The on-resistance of the third transistor M3 is fixed, while the on-resistance of the fifth transistor M5 changes with the control signal. The larger the control signal, the smaller the on-resistance of the fifth transistor M5, the faster the fifth transistor M5 turns on, the faster the parasitic capacitances C1 and C2 discharge, and the smaller the unit delay of delay unit 330; conversely, the smaller the control signal, the larger the unit delay of delay unit 330.

[0120] The operating mechanisms of the fourth transistor M4 and the sixth transistor M6 are the same as those of the third transistor M3 and the fifth transistor M5, and will not be elaborated here.

[0121] Therefore, by changing the magnitude of the control signal, the unit delay of the delay unit 330 can be adjusted.

[0122] A high-level trigger signal is input to the input terminal IN of the delay unit 330, turning off the first transistor M1 and turning on the third transistor M3. Simultaneously, a control signal turns on the fifth transistor M5 and the sixth transistor M6. The parasitic capacitance C1 at the first node A discharges until the second transistor M2 turns on. The high-level signal provided by the power supply terminal VDD flows through the second transistor M2 to the output terminal OUT of the delay unit 330, which then outputs the first time signal.

[0123] A low-level trigger signal is input to the IN terminal of delay unit 330, turning on the first transistor M1 and turning off the third transistor M3. A high-level signal provided by the power supply signal terminal VDD flows through the first transistor M1 to the first node A to charge the parasitic capacitor C1 until the level signal at the first node A causes the fourth transistor M4 to turn on. Simultaneously, a control signal turns on the sixth transistor M6, discharging the parasitic capacitor C2, and the OUT terminal of delay unit 330 outputs a second time signal. The parasitic capacitor C2 is connected to the ground terminal GND, and the OUT terminal of delay unit 330 outputs a low-level signal.

[0124] It should be noted that the first time signal can be considered as the moment when the time window signal transitions from a low level signal to a high level signal, i.e., the start time signal of the time window signal. The second time signal can be considered as the moment when the time window signal transitions from a high level signal to a low level signal, i.e., the end time signal of the time window signal.

[0125] When the delay unit 330 changes with operating conditions such as process angle, power supply voltage, and temperature, the control signal can be adjusted by the adaptive adjustment sub-circuit 31 to make the unit delay amount of the delay unit 330 consistent, so that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length.

[0126] Embodiments of this disclosure also provide a driving method for a time window adjustment circuit, applied to the aforementioned time window adjustment circuit 30. For example... Figure 9 As shown, the driving method of the time window adjustment circuit 30 includes steps S210 to S230.

[0127] Step S210: Upon receiving the trigger signal, output the first time signal through the time window sub-circuit 33.

[0128] like Figure 4As shown, in some examples, the time window sub-circuit 33 includes two delay units 330 connected in series, namely, a first delay unit 330 and a last delay unit 330 connected in series. After receiving the trigger signal, the first delay unit 330 outputs a trigger delay signal with a delay of 1 unit. After receiving the trigger delay signal, the last delay unit 330 outputs a first time signal (i.e., the start time signal of the time window) with a delay of 2 unit.

[0129] Step S220: Under different operating conditions, the adaptive adjustment sub-circuit 31 provides control signals to the time window sub-circuit 33.

[0130] It should be noted that when operating conditions such as process, temperature, power supply voltage or humidity change, the adaptive adjustment sub-circuit 31 can dynamically adjust the control signal through adjustment methods such as negative feedback, and provide control signals to the time window sub-circuit 33 to reduce or even eliminate the impact of operating condition changes on the time window sub-circuit 33.

[0131] In some examples, such as Figure 4 As shown, the control signal can be generated based on the phase of the reference signal and the phase of the last-position delay signal output by the delay sub-circuit 310 in the adaptive adjustment sub-circuit 31. For example, the control signal can be a voltage control signal or a current control signal. The control signal can be adjusted based on the reference signal and the last-position delay signal by the phase adjustment sub-circuit 320, so that the phase of the last-position delay signal and the phase of the reference signal remain consistent under different operating conditions.

[0132] Step S230: The time window sub-circuit 33 responds to the control signal and outputs a second time signal, so that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length. The first time signal and the second time signal together constitute the time window signal, and the time difference between the first time signal and the second time signal is the time window length.

[0133] The time window sub-circuit 33 responds to the control signal and outputs a second time signal. This can be understood as the control terminal of the time window sub-circuit 33 being coupled to the output terminal of the adaptive adjustment sub-circuit 31, so that the second time signal output by the time window sub-circuit 33 can change with the adjustment of the control signal.

[0134] In some examples, the power supply voltage makes the time window signal longer. For example, when the power supply voltage increases the delay of the second time signal output by the time window sub-circuit 33, the adaptive adjustment sub-circuit 31 can adjust the control signal to shorten the delay of the second time signal output by the time window sub-circuit 33, so that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length.

[0135] In some examples, the fabrication process of the time window adjustment circuit 30 shortens the time window signal. For example, when the process reduces the delay of the second time signal output by the time window sub-circuit 33, the adaptive adjustment sub-circuit 31 can adjust the control signal to increase the delay of the second time signal output by the time window sub-circuit 33, so that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length.

[0136] In some embodiments, such as Figure 10 As shown, step S220 may specifically include steps S221 to S223.

[0137] Step S221: Receive the reference signal using the delay sub-circuit 310, perform delay processing on the reference signal, and output the last-bit delayed signal.

[0138] It should be noted that the reference signal can be a clock reference signal with one cycle, for example, the reference signal can be the clock reference signal of one range detection cycle of the lidar.

[0139] In some examples, the delay sub-circuit 310 includes two delay sub-units 311 connected in series, namely, a first delay sub-unit 311 and a last delay sub-unit 311 connected in series. The first delay sub-unit 311 receives the reference signal from the reference signal terminal and outputs a first delayed signal after delaying the reference signal by one time its phase. The last delay sub-unit 311 receives the first delayed signal and outputs a last delayed signal after delaying the reference signal by two times its phase.

[0140] For example, the delay subunit 311 can be a voltage-controlled delay subunit 311, that is, the phase delay amount of the delay subunit 311 can be changed by adjusting the voltage value of the delay control voltage at the control terminal of the delay subunit 311, so that the phase of the delay signal output by the delay subunit 311 is leading or lagging.

[0141] Each delay subunit 311 can perform delay processing on the signal received at its input terminal in the same way, which can be understood as the phase delay amount of each delay subunit 311 performing delay processing being equal.

[0142] Step S222: Based on the reference signal and the last delay signal, the phase adjustment sub-circuit 320 provides a control signal to the delay sub-circuit 310 to adjust the delay amount of the delay processing, so that the phase of the last delay signal and the phase of the reference signal remain consistent under different operating conditions.

[0143] After receiving the reference signal and the last-position delay signal, the phase adjustment sub-circuit 320 compares the phase of the last-position delay signal with the phase of the reference signal to obtain one of three comparison results: the phase of the last-position delay signal lags behind the phase of the reference signal, the phase of the last-position delay signal leads the phase of the reference signal, or the phase of the last-position delay signal is equal to the phase of the reference signal.

[0144] like Figures 5 to 7 As shown, in some examples, the phase adjustment subcircuit 320 includes a phase detection module 321 and a charge pump module 322. The phase detection module 321 compares the phase difference between the reference signal and the last-order delay signal and provides the comparison result of the phase difference between the reference signal and the last-order delay signal to the charge pump module 322. Based on the comparison result of the phase difference between the reference signal and the last-order delay signal, the charge pump module 322 provides a control signal to the delay subcircuit 310 to adjust the delay amount of the delay processing, so that the phase of the last-order delay signal and the phase of the reference signal remain consistent under different operating conditions.

[0145] For example, the phase detection module 321 detects that the phase of the last-delay signal leads the phase of the reference signal, and outputs an UP signal corresponding to the phase difference between the last-delay signal and the reference signal. The charge pump module 322 adjusts the output control signal to increase the phase delay of the last-delay signal, so that the phase of the last-delay signal is consistent with the phase of the reference signal.

[0146] For example, the phase detection module 321 detects that the phase of the last-position delayed signal lags behind the phase of the reference signal, and outputs a DN signal corresponding to the phase difference between the last-position delayed signal and the reference signal. The charge pump module 322 adjusts the output control signal to reduce the phase delay of the last-position delayed signal, so that the phase of the last-position delayed signal is consistent with the phase of the reference signal.

[0147] For example, the phase detection module 321 detects that the phase of the last-bit delay signal is equal to the phase of the reference signal and outputs a reset signal rst. The charge pump module 322 maintains the control signal unchanged to ensure that the phase of the last-bit delay signal is consistent with the phase of the reference signal.

[0148] The phase delay of each delay subunit 311 can be adjusted by adjusting the control signal of each delay subunit 311, thereby increasing or decreasing the phase delay of the last delay signal.

[0149] Step S223: Provide a control signal to the time window sub-circuit through the phase adjustment sub-circuit 320 so that the multiple time window signals output by the time window sub-circuit under different operating conditions have a consistent time window length.

[0150] In some examples, the phase detection module 321 detects the phase difference between the last-order delayed signal and the reference signal. The charge pump module 322 provides control signals to the delay sub-circuit 310 and the time window sub-circuit 33 based on the phase difference between the last-order delayed signal and the reference signal.

[0151] like Figure 4 As shown, the delay sub-circuit 310 includes three delay sub-units 311. Each delay sub-unit 311 can perform a 1-times phase delay on the reference signal based on the control signal. That is, the delay sub-circuit 310 can perform a 3-times phase delay on the reference signal based on the last-position delay signal output by the control signal, so that the phase of the reference signal and the phase of the last-position delay signal are consistent. Here, the 3-times phase delay is equivalent to the phase difference between the last-position delay signal and the reference signal.

[0152] The time window sub-circuit 33 includes two delay units 330. Each delay unit 330 can delay the trigger signal by one unit delay based on the control signal. That is, the time window sub-circuit 33 can delay the trigger signal by two unit delays based on the time window signal output by the control signal, so that the phase of the trigger signal is consistent with the phase of the time window signal. This ensures that the multiple time window signals output by the time window sub-circuit 33 have a consistent time window length. Here, two unit delays are equivalent to the phase difference between the trigger signal and the time window signal.

[0153] The phase adjustment sub-circuit 320 adjusts the phase delay of the delay sub-circuit 310 through a control signal, ensuring that the phase of the last delayed signal is consistent with the phase of the reference signal. This overcomes the influence of external factors on the phase delay of the delay sub-circuit 310 under different operating conditions. Similarly, the control signal can adjust the unit delay of the time window sub-circuit 33 to overcome the influence of external factors on the unit delay of the time window sub-circuit 33 under different operating conditions, reducing or even eliminating the jitter in the time window length. This, in turn, reduces or eliminates the error in the LiDAR 1000 when performing noise reduction and other signal processing on the received reflected light signal, thereby improving the detection accuracy of the LiDAR 1000.

[0154] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A time window adjustment circuit, characterized in that, include: The time window sub-circuit is configured to output a first time signal upon receiving a trigger signal; It is also configured to output a second time signal under the action of a control signal; the first time signal and the second time signal together constitute a time window signal, wherein the time difference between the first time signal and the second time signal is the time window length; An adaptive adjustment sub-circuit is coupled to the control terminal of the time window sub-circuit; the adaptive adjustment sub-circuit includes: The delay sub-circuit is configured to receive a reference signal, perform delay processing on the reference signal, and output a last-bit delayed signal; A phase adjustment subcircuit is coupled to the delay subcircuit; the phase adjustment subcircuit is configured to provide the control signal to the delay subcircuit based on the reference signal and the last delay signal to adjust the delay amount of the delay processing, so that the phase of the last delay signal and the phase of the reference signal remain consistent under different operating conditions; The phase adjustment sub-circuit is also coupled to the control terminal of the time window sub-circuit; the phase adjustment sub-circuit is also configured to provide the control signal to the time window sub-circuit so that the multiple time window signals output by the time window sub-circuit under different operating conditions have a consistent time window length.

2. The time window adjustment circuit according to claim 1, characterized in that, The phase adjustment sub-circuit includes: A phase detection module is provided, wherein the input terminal of the phase detection module is coupled to the reference signal terminal and the output terminal of the delay sub-circuit, respectively; the phase detection module is configured to receive the reference signal and the last-bit delay signal, and output a comparison result between the phase of the reference signal and the phase of the last-bit delay signal; A charge pump module is provided, with its input terminal coupled to the output terminal of the phase detection module and its output terminal coupled to the control terminal of the delay sub-circuit. The charge pump module is configured to provide a control signal to the control terminal of the delay sub-circuit based on a comparison between the phase of the reference signal and the phase of the last-position delay signal, so that the phase of the last-position delay signal and the phase of the reference signal remain consistent under different operating conditions. The output terminal of the charge pump module is also coupled to the control terminal of the time window sub-circuit; the charge pump module is also configured to provide the control signal to the time window sub-circuit so that the multiple time window signals output by the time window sub-circuit under different operating conditions have a consistent time window length.

3. The time window adjustment circuit according to claim 1, characterized in that, The time window sub-circuit includes at least two delay units connected in series. Each delay unit delays the first signal received at its input terminal and outputs a second signal after delaying the first signal through its output terminal; the control terminal of each delay unit is coupled to the output terminal of the phase adjustment sub-circuit.

4. The time window adjustment circuit according to claim 3, characterized in that, The delay unit includes: The first transistor has its first terminal coupled to a power supply signal terminal; its control terminal is coupled to the input terminal of a delay unit; and its second terminal is coupled to a first node. The second transistor has its first terminal coupled to the power supply signal terminal, its control terminal coupled to the first node, and its second terminal coupled to the output terminal of the delay unit. A third transistor, the first terminal of which is coupled to the first node; the control terminal of which is coupled to the input of the delay unit and configured to receive the first signal; A fourth transistor, wherein the first terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the first node; The fifth transistor has its first terminal coupled to the second terminal of the third transistor, its control terminal coupled to the output terminal of the phase adjustment sub-circuit, and its second terminal coupled to ground. The sixth transistor has its first terminal coupled to the second terminal of the fourth transistor, its control terminal coupled to the output terminal of the phase adjustment sub-circuit, and its second terminal coupled to ground.

5. The time window adjustment circuit according to claim 4, characterized in that, The first transistor and the second transistor have the same channel type; the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same channel type; the first transistor and the third transistor have opposite channel types.

6. The time window adjustment circuit according to claim 1, characterized in that, The delay sub-circuit includes: At least two delay sub-units connected in series; each delay sub-unit delays the signal received at its input terminal by a phase delay of 1 time and outputs the delayed signal; the control terminal of each delay sub-unit is coupled to the output terminal of the phase adjustment sub-circuit.

7. A driving method for a time window adjustment circuit, characterized in that, The method is applied to the time window adjustment circuit as described in any one of claims 1 to 6; the driving method includes: Upon receiving a trigger signal, a first time signal is output through the time window sub-circuit; Under different operating conditions, the adaptive adjustment sub-circuit provides control signals to the time window sub-circuit; The time window sub-circuit responds to the control signal by outputting a second time signal, so that the multiple time window signals output by the time window sub-circuit have a consistent time window length; wherein, the first time signal and the second time signal together constitute the time window signal, and the time difference between the first time signal and the second time signal is the time window length.

8. The driving method for the time window adjustment circuit according to claim 7, characterized in that, The time window adjustment circuit as described in any one of claims 1 to 6; wherein, under different operating conditions, the adaptive adjustment sub-circuit provides a control signal to the time window sub-circuit, comprising: The delay sub-circuit is used to receive a reference signal, and the reference signal is delayed to output a last-bit delayed signal. The phase adjustment sub-circuit provides the control signal to the delay sub-circuit based on the reference signal and the last delay signal to adjust the delay amount of the delay processing, so that the phase of the last delay signal and the phase of the reference signal remain consistent under different operating conditions. The control signal is provided to the time window subcircuit through the phase adjustment subcircuit so that the multiple time window signals output by the time window subcircuit under different operating conditions have a consistent time window length.

9. A lidar, characterized in that, include: The transmitter is configured to emit light signals toward the target object; The receiver is configured to receive reflected light signals. A processor is coupled to both the transmitter and the receiver; the processor includes a time window adjustment circuit as described in any one of claims 1 to 6; The processor is configured to perform noise reduction processing on the reflected light signal to obtain the light signal reflected back by the target object, and to determine the detection distance based on the emitted light signal and the light signal reflected back by the target object.

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