A method and system for eliminating DDS phase jitter

Abstract

This invention relates to a method and system for eliminating phase jitter in a frequency divider (DDS), belonging to the field of radar technology. The phase jitter caused by multiphase division is solved by optimizing the clock distribution relationship of the frequency synthesizer and utilizing the synchronization function of the DDS. First, the FPGA inside the frequency synthesizer uses a reference clock generated by a crystal oscillator instead of the DDS's SYNC_CLK. Then, upon each power-on, the FPGA sends the reference clock to the DDS's SYNCIN pin as a synchronization signal. The DDS internally uses SYSCLK to sample SYNCIN, and when a rising edge of SYNCIN is detected, its internal frequency divider is reset. This invention avoids the multiphase problem caused by the DDS's internal frequency division, fundamentally solving the problem of DDS phase jitter.

Description

Technical Field

[0001] This invention belongs to the field of radar technology, specifically relating to a method and system for eliminating DDS phase jitter, which is applied in radar systems. Background Technology

[0002] Direct Digital Frequency Synthesis (DDS) is a fully digital frequency synthesis technology with advantages such as extremely high frequency resolution, phase resolution, and frequency switching speed, as well as the ability to flexibly generate a variety of complex waveform signals, thus it is widely used in radar systems.

[0003] In radar systems, when a DDS generates waveform signals, it typically uses the PRF (Pulse Repeat Frequency) sent by the signal processor (hereinafter referred to as "the processor") as a reference. This requires the start time of the DDS output signal to have a fixed delay relative to the rising edge of the PRF, thus ensuring a fixed initial phase relative to the rising edge of the PRF. According to the working principle of the DDS, it samples the control signal on the IO_UPDATE pin using its internal operating clock SYNC_CLK. When the rising edge of the IO_UPDATE signal is detected, the DDS internal register becomes active, and signal output begins. Since SYNC_CLK is generated by dividing the input reference clock SYSCLK, multiple phase states exist. Taking the DDS chip AD9957 as an example, its internal operating clock SYNC_CLK is a four-fold division of the input reference SYSCLK, meaning there are four phase states. For example... Figure 1 As shown, when SYNC_CLK is in a certain phase state, the IO_UPDATE signal may not meet its setup and hold time requirements, resulting in sampling metastability and causing initial phase jitter in the DDS output signal. As the DDS system clock frequency increases, SYNC_CLK is often 16 times or even 24 times the frequency of SYSCLK. Therefore, the probability of phase jitter in the DDS further increases. Summary of the Invention

[0004] The technical problem to be solved by this invention is:

[0005] Existing solutions rely on real-time detection to determine if phase jitter exists in the DDS output. If phase jitter is detected, the sampling metastability is avoided by adjusting the PRF delay. This method cannot fundamentally prevent phase jitter from occurring, and it can only be used as a remedial measure after phase jitter has occurred. For radar systems, even a single instance of phase jitter is unacceptable.

[0006] To fundamentally solve the problem of DDS phase jitter, this invention provides a method and system for eliminating DDS phase jitter.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A method for eliminating DDS phase jitter, characterized in that it includes:

[0009] The FPGA inside the frequency synthesizer uses a reference clock generated by a crystal oscillator as a reference.

[0010] Each time the FPGA is powered on, it sends a reference clock to the SYNCIN pin of the DDS as a synchronization signal. The DDS internally uses SYSCLK to sample SYNCIN. When the rising edge of SYNCIN is detected, its internal frequency divider is reset.

[0011] A system for eliminating DDS phase jitter, characterized in that it comprises: a signal processor, wherein the frequency synthesizer includes a crystal oscillator, a power divider, an FPGA, a frequency multiplier, and a DDS;

[0012] The crystal oscillator generates the reference clock for the entire system, which is then divided by a power divider and output to the signal processing unit.

[0013] The signal processor uses this clock to generate various timing control signals, including the PRF sent to the frequency synthesizer;

[0014] Inside the frequency synthesizer, various clock frequencies are generated through a reference clock, including the system clock SYSCLK generated by the frequency multiplier for the DDS chip; at the same time, the reference clock is input to the FPGA as its reference clock.

[0015] Each time the FPGA powers on, it outputs the reference clock as a synchronization signal to the SYNCIN pin of the DDS. The DDS internally samples the SYNCIN signal through SYSCLK. When the rising edge of SYNCIN is detected, the internal frequency divider is reset and the SYNC_CLK signal is regenerated.

[0016] The FPGA generates the IO_UPDATE signal of the DDS based on the PRF. The IO_UPDATE signal is sampled by SYNC_CLK inside the DDS, and the waveform is output when the rising edge is detected.

[0017] The beneficial effects of this invention are as follows:

[0018] This invention provides a method and system for eliminating phase jitter in a frequency synthesizer (DDS). The method addresses phase jitter caused by multi-phase division by optimizing the clock distribution of the frequency synthesizer and utilizing the synchronization function of the DDS. First, the FPGA inside the frequency synthesizer uses a reference clock generated by a crystal oscillator instead of the DDS's SYNC_CLK. Then, upon each power-on, the FPGA sends the reference clock to the DDS's SYNCIN pin as a synchronization signal. The DDS internally uses SYSCLK to sample SYNCIN; when a rising edge of SYNCIN is detected, its internal frequency divider is reset.

[0019] The method employed in this invention avoids the multiphase problem caused by internal frequency division in the DDS, fundamentally solving the problem of DDS phase jitter. This invention systematically resolves the issue of frequency division multiphase in the DDS, thereby ensuring that the DDS output signal has a fixed initial phase relative to the rising edge of the PRF. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0021] Figure 1 A schematic diagram illustrating phase jitter generation for DDS;

[0022] Figure 2 This is a schematic diagram of the technical method of the present invention;

[0023] Figure 3 This is a block diagram illustrating a specific implementation of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0025] The technical solution of this invention mainly utilizes the concept of multi-chip synchronization of DDS to solve the problem of multi-phase frequency division in the internal SYNC_CLK. Multi-chip synchronization is generally used in applications such as digital array radar that require synchronization of multiple DDS chips to ensure that the output signals of multiple DDS chips have a fixed phase relationship. The key is to simultaneously input a synchronization pulse to the SYNCIN pin of all DDS chips. This pulse can simultaneously reset the frequency dividers inside all DDS chips, aligning the SYNC_CLK of multiple DDS chips. However, multi-chip synchronization technology has limitations. When the DDS system clock frequency is high, it is difficult to achieve synchronization between multiple chips. For single-chip DDS applications, in addition to not needing synchronization itself, a high system clock is often required to generate the signal, so the synchronization function of the DDS is not used.

[0026] In this solution, phase jitter caused by multiphase frequency division is addressed by optimizing the clock distribution of the frequency synthesizer and utilizing the synchronization function of the DDS. First, the FPGA inside the frequency synthesizer uses a crystal oscillator-generated reference clock instead of the DDS's SYNC_CLK. Then, upon each power-up, the FPGA sends the reference clock to the DDS's SYNCIN pin as a synchronization signal. The DDS internally samples SYNCIN using SYSCLK, and when a rising edge of SYNCIN is detected, it resets its internal frequency divider. Since SYSCLK is generated by multiplying the reference clock, there is a fixed phase relationship between them. Resetting the frequency divider using the reference clock ensures that SYNC_CLK has a fixed phase relative to the reference clock upon each power-up. Because the phase state of SYNC_CLK is determined, sampling the DDS control signals using SYNC_CLK avoids sampling metastability, ensuring that phase jitter does not occur upon each power-up.

[0027] When the DDS system clock frequency is high, taking the AD9914 chip as an example, the system clock SYSCLK supports a maximum of 3500MHz, and SYNC_CLK is a 24-fold division of SYSCLK. In this case, sampling the SYNCIN signal through SYSCLK results in a very small sampling window, making it difficult to meet the setup and hold time requirements, leading to a jitter of one SYSCLK cycle in SYNC_CLK. This is unacceptable for multi-chip synchronization. However, for single-chip DDS applications, even with this limitation, the internal operating clock SYNC_CLK will only have two phase states instead of 24, significantly reducing the phase uncertainty of SYNC_CLK. By adjusting the PRF delay, the setup and hold time requirements of SYNC_CLK can be easily met, thus ensuring the phase stability of the DDS output. The specific implementation method is as follows... Figure 2 As shown.

[0028] like Figure 3 The diagram shows the principle block diagram of a specific implementation of the present invention. For radar systems, a crystal oscillator typically generates the system's reference clock, which is then output to the signal processing unit (SPD) after being divided by a power divider. The SPD uses this clock to generate various timing control signals, including the PRF signal sent to the frequency synthesizer. Inside the frequency synthesizer, various clock frequencies are generated using the reference clock, including frequency multiplication to generate the system clock SYSCLK for the DDS chip. Simultaneously, the reference clock is input to the FPGA as its reference clock. Upon each power-up, the FPGA outputs the reference clock as a synchronization signal to the SYNCIN pin of the DDS. The DDS internally samples the SYNCIN signal using SYSCLK. When a rising edge of SYNCIN is detected, the internal frequency divider is reset, regenerating the SYNC_CLK signal. Since SYSCLK is generated by multiplying the reference clock, there is a fixed phase relationship between the two. Resetting the frequency divider using the reference clock ensures that SYNC_CLK has a fixed phase relative to the reference clock each time power is applied. The PRF signal input to the SPD is generated by the reference clock, and the FPGA's sampling of it does not result in metastability. The FPGA then generates the DDS's IO_UPDATE signal based on the PRF. IO_UPDATE is sampled by SYNC_CLK inside DDS, and the waveform is output when a rising edge is detected.

[0029] The synchronization signal ensures that the internal SYNC_CLK of the DDS has a fixed phase relationship with the reference clock. Therefore, the relative relationship of the entire clock system is determined, completely solving the multi-phase problem of DDS frequency division and eliminating the phenomenon of DDS phase jitter.

[0030] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A system for eliminating DDS phase jitter, characterized in that, include: A frequency synthesizer and a signal processor, wherein the frequency synthesizer includes a crystal oscillator, a power divider, an FPGA, a frequency multiplier, and a DDS; The DDS is a single chip; The crystal oscillator generates the reference clock for the entire system, which is then divided by a power divider and output to the signal processor. The signal processor uses this clock to generate various timing control signals, including the pulse repetition frequency (PRF) sent to the frequency synthesizer; Inside the frequency synthesizer, various clock frequencies are generated through a reference clock, including the system clock SYSCLK generated by the frequency multiplier for the DDS chip; at the same time, the reference clock is input to the FPGA as its reference clock. Each time the FPGA powers on, it outputs the reference clock as a synchronization signal to the SYNCIN pin of the DDS. The DDS internally samples the SYNCIN signal through SYSCLK. When the rising edge of SYNCIN is detected, the internal frequency divider is reset and the SYNC_CLK signal is regenerated. The FPGA generates the DDS IO_UPDATE signal based on the PRF. The IO_UPDATE signal is sampled by SYNC_CLK inside the DDS. When the rising edge is detected, the waveform is output. The synchronization signal ensures that the internal SYNC_CLK of the DDS has a fixed phase relationship with the reference clock.

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