Methods for implementing cross-region RAM access

Abstract

This invention discloses a method for cross-region access to RAM memory. It involves real-time detection of the first byte address and size of the access word in a D-bus data access operation. When the access word size is 16 bits, if the first byte address is 0x1FFF_FFFF, D-bus data access is performed on the byte at address 0x1FFF_FFFF. Simultaneously, D-bus data access for the byte at address 0x0000_0000 is automatically mapped to S-bus data access for the register at address 0x2000_0000 in the on-chip SRAM area. D-bus data access is performed on bytes at other addresses in the D-bus area; otherwise, D-bus data access is performed on bytes with addresses from 0x0000_0000 to 0x1FFF_FFFE. This invention enables cross-region access to RAM configured in the code area under ARM address space allocation, maximizing the on-chip SRAM space and providing greater flexibility in dynamic allocation within the on-chip SRAM area.

Description

Technical Field

[0001] This invention relates to processor data access technology, and in particular to a method for implementing cross-region RAM access. Background Technology

[0002] The ARM architecture, formerly known as the Advanced Reduced Instruction Set Machine (RISC Machine) and even earlier as the AcornRISC Machine, is a 32-bit Reduced Instruction Set Computing (RISC) processor architecture. It also includes derivative products based on the ARM design, with important products including Marvell's XScale architecture and Texas Instruments' OMAP series. The ARM family accounts for 75% of all 32-bit embedded processors, making it the most prevalent 32-bit architecture worldwide. ARM processors are widely used in embedded system design due to their low power consumption and energy efficiency, making them highly suitable for the mobile communications field.

[0003] The ARM Cortex-M4 is a 32-bit processor with an addressable range of 2^32, or 4GB. Through 32-bit addressing, the ARM Cortex-M4 processor can access memory space ranging from 2 to 32 bytes = 4GB. The ARM Cortex-M4 divides this 4GB space from low to high address into the code area, on-chip SRAM area, on-chip peripheral area, and external RAM area. The address space allocation is as follows: Figure 1 As shown: the space 0x0000_0000-0x1FFF_FFFF is the code area, and data access uses D-BUS (D bus); the space 0x2000_0000-0x3FFF_FFFF is the on-chip SRAM area, and data access uses S-BUS (S bus).

[0004] The 32-bit addressing capability of the ARM Cortex-M4 processor ensures possible architecture-defined memory mapping for future upgrades and expansions. Its 4GB memory space is divided into multiple regions for predefined memory and peripherals to optimize processor design performance.

[0005] The ARM Cortex-M4 has three bus systems: the I-code bus for accessing instructions in the code space (instruction fetch only); the D-code bus (D bus) for accessing data in the code space (loadstore unit module, debug module, data manipulation only); and the System bus (S bus) for accessing other address spaces (both instruction fetch and data manipulation). These three buses can initiate read / write operations simultaneously and independently, but must access different data regions.

[0006] In actual product development, considering the high-efficiency execution of programs on SRAM (Static Random-Access Memory), a portion of SRAM is configured in the code area. Furthermore, to ensure contiguous SRAM address space, the SRAM addresses configured in the code area are connected to the 0x2000_0000 address space. Thus, when performing 16-bit / 32-bit cross-code data access on a word including addresses 1FFF_FFFD, 1FFF_FFFE, and / or 1FFF_FFFF, the ARM architecture interprets the cross-code byte address as a code address and always uses D-BUS for access. What should have been an access to addresses 2000_0000~2000_0002 becomes an access to 0000_0000~0000_0002, failing to achieve correct cross-code RAM access. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a method for realizing cross-region access of RAM memory, which can enable cross-region access of RAM configured in the code area under the ARM address space allocation, thereby maximizing the on-chip SRAM area space and providing more freedom for dynamic allocation on the on-chip SRAM area.

[0008] To solve the above technical problems, the present invention provides a method for cross-region access of RAM memory. The RAM memory includes a code area and an on-chip SRAM area. The address of the code area is 0x0000_0000 to 0x1FFF_FFFF, and data access is performed using the D bus. The address of the on-chip SRAM area is 0x2000_0000 to 0x3FFF_FFFF, and data access is performed using the S bus. Each byte is 8 bits, and the method includes the following steps:

[0009] S1. Real-time detection of the first byte address and size of the access word in D bus data access actions;

[0010] S2. When the access word size is 16 bits, proceed to step S3;

[0011] S3. If the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S4; otherwise, proceed to step S14.

[0012] S4. Perform D-bus data access on the byte at address 0x1FFF_FFFF. Simultaneously, automatically map the D-bus data access of the byte at address 0x0000_0000 that appears on the D-bus to the S-bus data access of the register at address 0x2000_0000 in the on-chip SRAM area. Perform D-bus data access on bytes at other addresses that appear on the D-bus. Then proceed to step S15.

[0013] S14. Perform D-bus data access on bytes with byte addresses from 0x0000_0000 to 0x1FFF_FFFE, and then proceed to step S15;

[0014] S15. This D-bus data access operation has ended.

[0015] Preferably, in step S2, when the access word size is 32 bits, step S6 is performed;

[0016] S6. If the address of the first byte of the accessed word is 0x1FFF_FFFD, proceed to step S7; if the address of the first byte of the accessed word is 0x1FFF_FFFE, proceed to step S8; if the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S9; if the address of the first byte of the accessed word is not 0x1FFF_FFFD, 0x1FFF_FFFE, or 0x1FFF_FFFF, proceed to step S14.

[0017] S7. Perform D-bus data access on bytes with addresses 0x1FFF_FFFD, 0x1FFF_FFFE, and 0x1FFF_FFF that appear on the D-bus. Automatically map the D-bus data access on bytes with address 0x0000_0000 to the S-bus data access on the on-chip SRAM area register with address 0x2000_0000. Perform D-bus data access on bytes with addresses 0x0000_0001 to 0x1FFF_FFFC that appear on the D-bus, and then proceed to step S15.

[0018] S8. Perform D-bus data access on bytes with addresses 0x1FFF_FFFE and 0x1FFF_FFF that appear on the D-bus. Automatically map D-bus data access on bytes with addresses 0x0000_0000 to 0x0000_0001 that appear on the D-bus to S-bus data access on registers with addresses 0x2000_0000 to 0x2000_0001 in the on-chip SRAM area. Perform D-bus data access on bytes with addresses 0x0000_0002 to 0x1FFF_FFFD that appear on the D-bus, and then proceed to step S15.

[0019] S9. Perform D-bus data access on the byte with address 0x1FFF_FFF that appears on the D-bus. Automatically map the D-bus data access on the bytes with addresses 0x0000_0000 to 0x0000_0002 that appear on the D-bus to the S-bus data access on the registers with addresses 0x2000_0000 to 0x2000_0002 in the on-chip SRAM area. Perform D-bus data access on the bytes with addresses 0x0000_0003 to 0x1FFF_FFFE that appear on the D-bus, and then proceed to step S15.

[0020] Preferably, the data access action is a read operation or a write operation.

[0021] Preferably, the RAM memory is an ARM architecture processor-addressable RAM memory.

[0022] Preferably, the RAM memory is an ARM Cortex-M4 processor-addressable RAM memory.

[0023] Preferably, the RAM memory further includes an on-chip peripheral area, the address of which is 0x4000_0000 to 0x5FFF_FFFF.

[0024] Preferably, the RAM memory further includes off-chip RAM, with the address of the off-chip RAM being 0x6000_0000 to 0x9FFF_FFFF.

[0025] Preferably, the RAM memory further includes an off-chip device area with addresses ranging from 0xA000_0000 to 0xDFFF_FFFF.

[0026] The method for cross-region access to RAM memory of the present invention enables cross-region access to RAM configured in the code area under the ARM address space allocation. It realizes cross-region access to RAM in ARM architecture processors with continuous RAM space allocation around 2000_000, and achieves correct data access. Since the address spaces configured in the code area and the on-chip SRAM area are continuous, the on-chip SRAM area space is maximized. The program that the software application puts into the on-chip SRAM area can be larger, and the dynamic allocation on the on-chip SRAM area is more flexible. Attached Figure Description

[0027] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of the addressing range of the ARM Cortex-M4 processor;

[0029] Figure 2 This is a flowchart of an embodiment of the method for implementing cross-region access of RAM memory according to the present invention;

[0030] Figure 3 This is a schematic diagram of an embodiment of the method for implementing cross-region access of RAM memory according to the present invention. Detailed Implementation

[0031] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] Example 1

[0033] A method for implementing cross-region access of RAM memory, wherein the RAM memory includes a code area and an on-chip SRAM area; the code area has addresses from 0x0000_0000 to 0x1FFF_FFFF, and accesses data using a D-BUS (D bus); the on-chip SRAM area has addresses from 0x2000_0000 to 0x3FFF_FFFF, and accesses data using an S-BUS (S bus); each byte is 8 bits; such as Figure 2 , Figure 3 As shown, it includes the following steps:

[0034] S1. Real-time detection of the first byte address and size of the access word in the D bus data access action;

[0035] S2. When the access word size is 16 bits, proceed to step S3;

[0036] S3. If the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S4; otherwise, proceed to step S14.

[0037] S4. Perform D-bus data access on the byte at address 0x1FFF_FFFF. Simultaneously, automatically map the D-bus data access of the byte at address 0x0000_0000 that appears on the D-bus to the S-bus data access of the register at address 0x2000_0000 in the on-chip SRAM area. Perform D-bus data access on bytes at other addresses that appear on the D-bus. Then proceed to step S15.

[0038] S14. Perform D-bus data access on bytes with byte addresses from 0x0000_0000 to 0x1FFF_FFFE, and then proceed to step S15;

[0039] S15. This D-bus data access operation has ended.

[0040] The method for implementing cross-region RAM access in Example 1 enables cross-region RAM access configured in the code area under the ARM address space allocation. This allows for continuous RAM space allocation in ARM architecture processors around address space 2000_000, ensuring correct data access. Since the address spaces configured in the code area and the on-chip SRAM area are continuous, the on-chip SRAM area space is maximized. This allows for larger programs to be placed in the on-chip SRAM area, and provides greater flexibility in dynamic allocation within the on-chip SRAM area.

[0041] Example 2

[0042] Based on the method for implementing cross-regional access of RAM memory in Embodiment 1, in step S2, when the access word size is 32 bits, step S6 is performed;

[0043] S6. If the address of the first byte of the accessed word is 0x1FFF_FFFD, proceed to step S7; if the address of the first byte of the accessed word is 0x1FFF_FFFE, proceed to step S8; if the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S9; if the address of the first byte of the accessed word is not 0x1FFF_FFFD, 0x1FFF_FFFE, or 0x1FFF_FFFF, proceed to step S14.

[0044] S7. Perform D-bus data access on bytes with addresses 0x1FFF_FFFD, 0x1FFF_FFFE, and 0x1FFF_FFF that appear on the D-bus. Automatically map the D-bus data access on bytes with address 0x0000_0000 to the S-bus data access on the on-chip SRAM area register with address 0x2000_0000. Perform D-bus data access on bytes with addresses 0x0000_0001 to 0x1FFF_FFFC that appear on the D-bus, and then proceed to step S15.

[0045] S8. Perform D-bus data access on bytes with addresses 0x1FFF_FFFE and 0x1FFF_FFF that appear on the D-bus. Automatically map D-bus data access on bytes with addresses 0x0000_0000 to 0x0000_0001 that appear on the D-bus to S-bus data access on registers with addresses 0x2000_0000 to 0x2000_0001 in the on-chip SRAM area. Perform D-bus data access on bytes with addresses 0x0000_0002 to 0x1FFF_FFFD that appear on the D-bus, and then proceed to step S15.

[0046] S9. Perform D-bus data access on the byte with address 0x1FFF_FFF that appears on the D-bus. Automatically map the D-bus data access on the bytes with addresses 0x0000_0000 to 0x0000_0002 that appear on the D-bus to the S-bus data access on the registers with addresses 0x2000_0000 to 0x2000_0002 in the on-chip SRAM area. Perform D-bus data access on the bytes with addresses 0x0000_0003 to 0x1FFF_FFFE that appear on the D-bus, and then proceed to step S15.

[0047] Example 2

[0048] The method for cross-region access of RAM memory based on Embodiment 1, wherein the data access action is a read operation or a write operation.

[0049] Preferably, the RAM memory is an ARM architecture processor-addressable RAM memory.

[0050] Preferably, the RAM memory is an ARM Cortex-M4 processor-addressable RAM memory.

[0051] Preferably, the RAM memory further includes an on-chip peripheral area with addresses ranging from 0x4000_0000 to 0x5FFF_FFFF.

[0052] Preferably, the RAM memory further includes external RAM with addresses from 0x6000_0000 to 0x9FFF_FFFF.

[0053] Preferably, the RAM memory further includes an external device area with addresses from 0xA000_0000 to 0xDFFF_FFFF.

[0054] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for implementing cross-region access of RAM memory, wherein the RAM memory includes a code area and an on-chip SRAM area; the address of the code area is 0x0000_0000~0x1FFF_FFFF, and data access is performed using a D bus; the address of the on-chip SRAM area is 0x2000_0000~0x3FFF_FFFF, and data access is performed using an S bus; each byte is 8 bits, characterized in that, Includes the following steps: S1. Real-time detection of the first byte address and size of the access word in D bus data access actions; S2. When the access word size is 16 bits, proceed to step S3; S3. If the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S4; otherwise, proceed to step S14. S4. Perform D-bus data access on the byte at address 0x1FFF_FFFF. Simultaneously, automatically map the D-bus data access of the byte at address 0x0000_0000 that appears on the D-bus to the S-bus data access of the register at address 0x2000_0000 in the on-chip SRAM area. Perform D-bus data access on bytes at other addresses that appear on the D-bus. Then proceed to step S15. S14. Perform D-bus data access on bytes with byte addresses from 0x0000_0000 to 0x1FFF_FFFE, and then proceed to step S15; S15. This D-bus data access operation has ended.

2. The method for realizing cross-regional access of RAM memory according to claim 1, characterized in that, In step S2, when the access word size is 32 bits, proceed to step S6; S6. If the address of the first byte of the accessed word is 0x1FFF_FFFD, proceed to step S7; if the address of the first byte of the accessed word is 0x1FFF_FFFE, proceed to step S8; if the address of the first byte of the accessed word is 0x1FFF_FFFF, proceed to step S9; if the address of the first byte of the accessed word is not 0x1FFF_FFFD, 0x1FFF_FFFE, or 0x1FFF_FFFF, proceed to step S14. S7. Perform D-bus data access on bytes with addresses 0x1FFF_FFFD, 0x1FFF_FFFE, and 0x1FFF_FFF that appear on the D-bus. Automatically map the D-bus data access on bytes with address 0x0000_0000 to the S-bus data access on the on-chip SRAM area register with address 0x2000_0000. Perform D-bus data access on bytes with addresses 0x0000_0001 to 0x1FFF_FFFC that appear on the D-bus, and then proceed to step S15. S8. Perform D-bus data access on bytes with addresses 0x1FFF_FFFE and 0x1FFF_FFF that appear on the D-bus. Automatically map D-bus data access on bytes with addresses 0x0000_0000 to 0x0000_0001 that appear on the D-bus to S-bus data access on registers with addresses 0x2000_0000 to 0x2000_0001 in the on-chip SRAM area. Perform D-bus data access on bytes with addresses 0x0000_0002 to 0x1FFF_FFFD that appear on the D-bus, and then proceed to step S15. S9. Perform D-bus data access on the byte with address 0x1FFF_FFF that appears on the D-bus. Automatically map the D-bus data access on the bytes with addresses 0x0000_0000 to 0x0000_0002 that appear on the D-bus to the S-bus data access on the registers with addresses 0x2000_0000 to 0x2000_0002 in the on-chip SRAM area. Perform D-bus data access on the bytes with addresses 0x0000_0003 to 0x1FFF_FFFE that appear on the D-bus, and then proceed to step S15.

3. The method for realizing cross-region access of RAM memory according to claim 2, characterized in that, The data access action is either a read operation or a write operation.

4. The method for realizing cross-regional access of RAM memory according to claim 1, characterized in that, The RAM memory is an ARM architecture processor-addressable RAM memory.

5. The method for realizing cross-regional access of RAM memory according to claim 1, characterized in that, The RAM memory is an ARM Cortex-M4 processor-addressable RAM memory.

6. The method for realizing cross-regional access of RAM memory according to claim 1, characterized in that, The RAM memory also includes an on-chip peripheral area, with addresses ranging from 0x4000_0000 to 0x5FFF_FFFF.

7. The method for implementing cross-region access of RAM memory according to claim 1, characterized in that, The RAM memory also includes off-chip RAM, with addresses ranging from 0x6000_0000 to 0x9FFF_FFFF.

8. The method for implementing cross-region access of RAM memory according to claim 1, characterized in that, The RAM memory also includes an off-chip device area, with addresses ranging from 0xA000_0000 to 0xDFFF_FFFF.

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