Data processing method, data processing apparatus, electronic device, and storage medium

Abstract

A data processing method, a data processing apparatus, an electronic device and a storage medium. The data processing method is used for a first node in a plurality of nodes connected in communication with each other, the first node comprising a directory listening extension filter for the first node, the directory listening extension filter comprising a first consistent directory, a directory vector of each directory entry in the first consistent directory comprising a first part and a second part for object data, the first part being used to indicate whether the object data is cached in other nodes except the first node, and the second part being used to indicate whether the object data is cached in the first node. The data processing method comprises: in response to the directory listening extension filter receiving a query requirement for first data, querying a directory entry of the first consistent directory to determine whether the first data is cached in the first node and whether the first data is cached in other nodes except the first node. The method can alleviate the bandwidth occupation pressure of node partition transmission.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a data processing method, a data processing apparatus, an electronic device, and a storage medium. Background Technology

[0002] Currently, in computer systems with multiple processors and multiple caches, caches can store large amounts of data, which may be exclusive or may contain copies of the same data at different addresses. When different caches operate on data at the same cached address, consistency issues arise. To address this, many techniques have emerged to maintain data consistency. For example, when multiple caches store the same data copies, if a processor wants to modify data stored in one cache, the copies of that data in other caches will be marked invalid to avoid consistency errors. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a data processing method for a first node among a plurality of communicatively connected nodes, wherein the first node includes a directory snooping extended filter for the first node, the directory snooping extended filter including a first consistency directory, and each directory entry in the first consistency directory having a directory vector for object data including a first part and a second part, the first part indicating whether other nodes besides the first node cache the object data, and the second part indicating whether the first node caches the object data; the data processing method includes: in response to the directory snooping extended filter receiving a query request for first data, querying the directory entries of the first consistency directory to determine whether the first data is cached within the first node and whether it is cached within other nodes besides the first node.

[0004] For example, in a data processing method according to at least one embodiment of the present disclosure, the first node further includes a first processor core, and the data processing method further includes: generating a first access request for the first data by the first processor core, wherein the storage address of the first data is located in other nodes besides the first node; generating the query request based on the first access request; and sending a first listening request by the directory listening extended filter according to the first query result of querying the directory entries of the first consistency directory.

[0005] For example, in a data processing method according to at least one embodiment of the present disclosure, the first node further includes a second processor core, the second processor core including at least one cache, and the directory listening extended filter sends a first listening request based on a first query result of querying the directory entries of the first consistency directory, including: in response to determining that the first data has been cached in the cache of the second processor core based on the first query result, the directory listening extended filter sends the first listening request to the second processor core.

[0006] For example, the data processing method according to at least one embodiment of the present disclosure further includes: the second processor core responding to the first access request according to the first listening request and sending the first data from the cache of the second processor core to the first processor core.

[0007] For example, in a data processing method according to at least one embodiment of the present disclosure, sending a first listening request by the directory listening extended filter based on a first query result of querying the directory entries of the first consistency directory includes: in response to determining, based on the first query result, that the first data has been cached in other nodes besides the first node, sending the first listening request to the other nodes besides the first node.

[0008] For example, the data processing method according to at least one embodiment of this disclosure further includes: the first node receiving an external listening request regarding the cache consistency status of the first data; and the external listening request generating the query requirement.

[0009] For example, the data processing method according to at least one embodiment of the present disclosure further includes: in response to querying the directory entries of the first consistency directory and determining that the first node does not cache the first data, the first node forwards the external listening request and does not process the external listening request.

[0010] For example, in a data processing method according to at least one embodiment of the present disclosure, the plurality of nodes are divided into a plurality of node partitions, each of the plurality of node partitions including at least one node, and the first part indicates whether other nodes besides the first node have cached the first data by recording area information.

[0011] For example, in a data processing method according to at least one embodiment of the present disclosure, the inter-node consistency extension unit of the first node queries the first consistency directory of the directory listening extension filter according to the query requirements.

[0012] For example, in a data processing method according to at least one embodiment of this disclosure, the first node further includes a first processor core, a first memory controller, and a directory listening filter for the first memory controller. The directory listening filter includes a second consistency directory, and the directory vector of each directory entry in the second consistency directory also includes the first part and the second part for the object data. The data processing method further includes: generating a second access request for second data by the first processor core, wherein the storage address of the second data is located in the first node; querying the directory entries of the second consistency directory according to the second access request to obtain a second query result, used to determine whether the second data is cached in the first node and whether it is cached in other nodes besides the first node; and issuing a second listening request by the second directory listening filter according to the second query result.

[0013] For example, in a data processing method according to at least one embodiment of the present disclosure, the first node further includes a second processor core, the second processor core including at least one cache, and the data processing method further includes: in response to the second query result determining that the second data has been cached in the cache of the second processor core, the second processor core responds to the second access request according to the second listening request and sends the second data from the cache of the second processor core to the first processor core.

[0014] At least one embodiment of this disclosure provides an electronic device including a plurality of nodes communicatively connected to each other, wherein the plurality of nodes includes a first node, the first node including a directory snooping extended filter for the first node, the directory snooping extended filter including a first consistency directory, each directory entry in the first consistency directory having a directory vector for object data including a first part and a second part, the first part indicating whether other nodes besides the first node cache the object data, and the second part indicating whether the first node caches the object data; the first node is configured to, in response to the directory snooping extended filter receiving a query request for first data, query the directory entries of the first consistency directory to determine whether the first data is cached within the first node and whether it is cached within other nodes besides the first node.

[0015] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a first processor core and an inter-node consistency extension unit. The first processor core is configured to generate a first access request for the first data, the storage address of the first data is located in other nodes besides the first node, and the inter-node consistency extension unit is configured to generate the query request based on the first access request. The directory listening extension filter is configured to send a first listening request based on a first query result of querying the directory entries of the first consistency directory.

[0016] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a second processor core, the second processor core including at least one cache, and the directory listening extended filter is further configured to send the first listening request to the second processor core in response to determining, based on the first query result, that the first data has been cached in the cache of the second processor core.

[0017] For example, in an electronic device according to at least one embodiment of the present disclosure, the second processor core is configured to respond to the first access request in response to the first listening request and send the first data from the cache of the second processor core to the first processor core.

[0018] For example, in an electronic device according to at least one embodiment of the present disclosure, the directory listening extended filter is further configured to send the first listening request to the other nodes besides the first node in response to determining, based on the first query result, that the first data has been cached in other nodes besides the first node.

[0019] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes an inter-node consistency extension unit, the inter-node consistency extension unit being configured to receive an external listening request for the cache consistency status of the first data; the directory listening extension filter is further configured to generate the query request from the external listening request.

[0020] For example, in an electronic device according to at least one embodiment of the present disclosure, the inter-node consistency extension unit is further configured to, in response to querying the directory entry of the first consistency directory and determining that the first data is not cached in the first node, forward the external listening request and not process the external listening request.

[0021] For example, in an electronic device according to at least one embodiment of the present disclosure, the plurality of nodes are divided into a plurality of node partitions, each of the plurality of node partitions including at least one node, and the first part indicates whether other nodes besides the first node have cached the first data by recording area information.

[0022] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a switching unit, and the inter-node consistency extension unit is configured to communicate with the directory listening extension filter through the switching unit.

[0023] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a first processor core, a first memory controller, and a directory listening filter for the first memory controller. The directory listening filter includes a second consistency directory, and the directory vector of each directory entry in the second consistency directory also includes the first part and the second part for the object data. The first processor core is configured to generate a second access request for the second data, wherein the storage address of the second data is located in the first node. The first memory controller is configured to query the directory entries of the second consistency directory according to the second access request to obtain a second query result, which is used to determine whether the second data is cached in the first node and whether it is cached in other nodes besides the first node. The second directory listening filter is configured to issue a second listening request according to the second query result.

[0024] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a second processor core, the second processor core including at least one cache, the second processor core being configured to, in response to a second query result determining that the second data has been cached in the cache of the second processor core, respond to the second access request according to the second listening request, and send the second data from the cache of the second processor core to the first processor core.

[0025] At least one embodiment of this disclosure also provides a data processing apparatus including a memory and at least one processor. The memory is configured to store computer-executable instructions; the at least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the method as described in any of the above embodiments.

[0026] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, when the computer-executable instructions are executed by at least one processor, the method described in any of the above embodiments is implemented. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 A schematic diagram of a processor node is shown.

[0029] Figure 2 This diagram illustrates a directory organization structure for a consistent directory with a directory listener filter.

[0030] Figure 3 A schematic diagram of a processor node of an electronic device according to at least one embodiment of the present disclosure is shown.

[0031] Figure 4 A schematic diagram of the directory organization structure of a consistency directory of a directory listening filter according to at least one embodiment of the present disclosure is shown.

[0032] Figure 5A A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown, wherein the electronic device in this embodiment is a two-node system.

[0033] Figure 5B A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown, wherein the electronic device in this embodiment is a three-node system.

[0034] Figure 5C A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown, wherein the electronic device in this embodiment is a multi-node system.

[0035] Figure 6 A schematic diagram of the directory organization structure of a consistent directory according to at least another embodiment of the directory listening filter of the present disclosure is shown.

[0036] Figure 7 A schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure is shown.

[0037] Figure 8 A schematic diagram of a non-transitory storage medium provided in one embodiment of the present disclosure is shown. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0041] In multiprocessor (or multiprocessor core) systems, techniques such as snooping and filtering have been proposed to improve the efficiency of data consistency maintenance. Snooping and filtering techniques can help track the cache states in multiple caches, including: a single copy of a certain data in a cache with exclusive access, multiple copies of a certain data in several caches sharing the same data, or a certain data existing only in main memory, etc.

[0042] In a multi-processor (or processor core) multi-cache computer system, a directory listener filter tracks the state of the processor cache and stores the tracked state information in the listener filter. When the consistency agent listens on the bus and detects a consistent transaction, it queries the cache consistency information tracked in the listener filter and issues the corresponding listener request to complete the consistency maintenance.

[0043] Figure 1 A schematic diagram of a processor node 100 is shown, which is, for example, a single processor chip or an independent part of a processor chip, and together with other processor nodes constitutes a larger system such as an electronic device.

[0044] like Figure 1 As shown, processor node 100 is a basic multiprocessor multi-cache system that uses directory sniffing filters to maintain cache coherency. Processor node 100 includes n+1 processor cores 10~1n, n+1 caches (hereinafter also referred to as "caches") 20~2n, a coherent interconnect bus 14, m+1 memory controllers 40~4m, m+1 system memory 30~3m, and m+1 directory sniffing filters (or "coherent directory sniffing filters") 50~5m, where n and m are both integers greater than or equal to 0.

[0045] For example, each of caches 20-2n is configured to store data storage information corresponding to at least one piece of data. For example, caches 20-2n can be multiple dedicated caches used by processor cores 10-1n respectively. In addition, the processor node 100 may also include a shared cache for processor cores 10-1n.

[0046] like Figure 1 As shown, the above m+1 memory controllers 40~4m correspond to the m+1 system memories 30~3m respectively; the above m+1 memory controllers 40~4m correspond to the m+1 directory snooping filters 50~5m respectively. These memory controllers are used to manage and control access to and operation of the system memories, and as consistency nodes, they connect the corresponding directory snooping filters and system memories to the consistency interconnect bus 14.

[0047] These directory listener filters are used to maintain the consistency of data in the corresponding system memory within the caches 20-2n. More specifically, directory listener filters 50-5m help track the cached data status in caches 20-2n; for example, for a given piece of data, the cached data status may include: one or more single copies of the cached data in caches 20-2n, multiple copies of the cached data, or the data existing only in main memory. Directory listener filters 10-1n track the cached data status of the caches 20-2n of processor cores 10-1n and store the tracked status information in the directory of directory listener filters 10-1n. When the consistency broker listens to the bus and detects a consistent transaction, it queries the tracked status information in directory listener filters 10-1n, and the corresponding directory listener filter or directory listener extended filter issues a corresponding listener request to complete the consistency maintenance.

[0048] For example, such as Figure 1 As shown, the coherence interconnect bus 14 is directly coupled to caches 20-2n and also directly coupled to memory controllers 40-4m. The coherence interconnect bus 14 is a common communication trunk for information transmission; for example, the coherence interconnect bus 14 is a transmission harness composed of electronic components such as wires in the chip.

[0049] like Figure 1 As shown, the processor node 100 also includes a consistency extension unit 15, which is used to communicate with other processor nodes (e.g., chips) to maintain data cache consistency among multiple nodes by querying the aforementioned directory listener filters 10~1n.

[0050] Figure 2 This is a diagram illustrating a directory organization structure for a directory listener filter's consistency mechanism. For example... Figure 2 As shown, the directory is a data table containing multiple directory entries (or target items). Each directory entry can include the following data items: Directory validity bit: Indicates whether the directory entry is valid.

[0051] Owner ID: If the data stored at the address corresponding to this directory entry is exclusively occupied by a certain cache, the ID of that cache is recorded, and when other caches access the data stored at this address, they can directly send a listening request to the cache that exclusively occupies the data.

[0052] Directory vectors indicate which caches have backups of the data stored at a given address. Directory vectors can be used for precise recording, such as recording whether every cache in the system caches the data, or for fuzzy recording, such as recording only which nodes or even which region nodes cache the data.

[0053] Cache status information: indicates the status of the data backup in the corresponding cache at the address corresponding to the directory entry, such as shared state, exclusive state, modified state, etc.

[0054] Directory address flag: indicates the address information corresponding to the data stored at the address of the directory entry, usually recording the high N bits of the address.

[0055] Depending on which MSI / MESI / MOESI protocol the system cache state uses, the request type and listening type will differ, and the embodiments disclosed herein do not impose any limitations on this.

[0056] The inventors of this disclosure noted during their research that, in the data items of the aforementioned directory entries, the directory vector can be precisely recorded, such as recording whether each cache has cached the data, or it can be vaguely recorded, such as only recording which processor nodes or even processor nodes in which region have cached the data. Correspondingly, the more precise the directory vector recording, the better the system performance, but the storage overhead also increases accordingly. Although degrading the precision of the directory recording can solve the storage overhead problem, it also leads to many meaningless listener requests and responses used for consistency maintenance, which consume system bandwidth and waste power.

[0057] Based on the above understanding, at least one embodiment of this disclosure provides a data processing method and an electronic device.

[0058] This disclosure provides an electronic device in at least one embodiment, the electronic device including a plurality of nodes communicatively connected to each other, wherein the plurality of nodes includes a first node, the first node including a directory snooping extended filter for the first node, the directory snooping extended filter including a first consistency directory, each directory entry in the first consistency directory having a directory vector for object data including a first part and a second part, the first part indicating whether other nodes besides the first node cache the object data, and the second part indicating whether the first node caches the object data; the first node is configured to, in response to the directory snooping extended filter receiving a query request for first data, query the directory entries of the first consistency directory to determine whether the first data is cached within the first node and whether it is cached within other nodes besides the first node.

[0059] Corresponding to the above-mentioned electronic device, at least one embodiment of this disclosure provides a data processing method, which includes the following steps: in response to receiving a query request for first data by a directory listening extended filter, querying the directory entries of a first consistency directory to determine whether the first data is cached in a first node and whether it is cached in other nodes besides the first node.

[0060] In the above embodiments, the first node can be any of multiple nodes in an electronic device, such as a single chip or a portion of a single chip, and the first node itself is a multiprocessor multi-cache system. During operation, the first node can act as a requesting node, a passing node, or a home node, and thereby process generated or received listening requests accordingly. The directory listening extended filter is used for the entire first node, rather than being set for the memory controller as mentioned later. The directory vector of each directory entry in the consistency directory of the directory listening extended filter can include two or more parts, thereby recording the directory vector hierarchically, which enables hierarchical processing of listening requests.

[0061] The "object data" mentioned above refers to the data corresponding to each directory entry in the directory itself; therefore, different directory entries correspond to different object data. The "first data" mentioned above and the "second data" mentioned later refer to the data that is the object of the current operation. The "query request" is the premise of the query operation, which can be in the form of a query request or a non-query request, and the consistency directory is queried based on the query request.

[0062] For example, multiple nodes in an electronic device can be identical to the first node, and also hierarchically record the directory vectors of the consistent directories (whether it is a directory sniffing extended filter or a directory sniffing filter), thereby enabling hierarchical processing of sniffing requests used for cache consistency maintenance.

[0063] The electronic device and data processing method provided in the above embodiments of this disclosure can realize hierarchical recording of directory vectors and correspondingly perform hierarchical processing of listening requests, thereby reducing the number of meaningless listening requests and responses, alleviating the bandwidth occupation pressure of inter-node (e.g., inter-chip) transmission, and reducing the power consumption of inter-chip transmission due to the reduction of data traffic between nodes; in some embodiments, the access latency can also be effectively shortened, which improves the overall performance of the electronic device.

[0064] For example, in an electronic device of at least one embodiment, the first node further includes a first processor core and an inter-node consistency extension unit. The first processor core is configured to generate a first access request for first data, the storage address of which is located in other nodes besides the first node. The inter-node consistency extension unit is configured to generate a query request based on the first access request. The directory listening extension filter is configured to send a first listening request based on the first query result of querying directory entries in the first consistency directory. In this embodiment, the first node is a requesting node, and therefore the inter-node consistency extension unit of the first node needs to handle inter-node communication.

[0065] For example, in an electronic device of at least one embodiment, the first node further includes a second processor core, the second processor core including at least one cache; the directory listening extended filter is further configured to send a first listening request to the second processor core in response to determining, based on a first query result, that the first data has been cached in the cache of the second processor core.

[0066] For example, in an electronic device of at least one embodiment, a second processor core is configured to respond to a first access request in response to a first listening request and send first data from the cache of the second processor core to the first processor core.

[0067] For example, in an electronic device of at least one embodiment, the directory listening extended filter is further configured to send a first listening request to the nodes other than the first node in response to determining, based on a first query result, that the first data has been cached in other nodes besides the first node.

[0068] For example, in an electronic device of at least one embodiment, the first node further includes an inter-node consistency extension unit; the inter-node consistency extension unit is configured to receive an external listening request for the cache consistency status of the first data; the directory listening extension filter is further configured to generate a query request from the external listening request. In this embodiment, the first node is a node that passes through the listening request (i.e., the external listening request).

[0069] For example, in an electronic device of at least one embodiment, the inter-node consistency extension unit is further configured to, in response to querying a directory entry in the first consistency directory and determining that no first data is cached within the first node, forward the external listening request without processing it. In the case where the first node is a passing node, if it can be determined through the first part of the first consistency directory that the data involved in the listening request is not cached within that node, then the first node itself does not need to process the listening request except for forwarding it, thereby reducing the operations of the first node itself in processing the listening request and the resulting possible responses.

[0070] For example, in an electronic device of at least one embodiment, the first node further includes a first processor core, a first memory controller, and a directory listening filter for the first memory controller. The directory listening filter includes a second consistency directory, and the directory vector of each directory entry in the second consistency directory also includes a first part and a second part for the object data. The first processor core is configured to generate a second access request for second data, wherein the storage address of the second data is located in the first node. The first memory controller is configured to query the directory entries of the second consistency directory according to the second access request to obtain a second query result, used to determine whether the second data is cached in the first node and whether it is cached in other nodes besides the first node. The second directory listening filter is configured to issue a second listening request according to the second query result. In this embodiment, the first node is the requesting node, and the data to be read is also located in the first node. In this case, the directory listening filter corresponding to the memory controller handles the listening request and other operations.

[0071] For example, in an electronic device of at least one embodiment, the first node further includes a second processor core, the second processor core including at least one cache; the second processor core is configured to, in response to a second query result determining that second data has been cached in the cache of the second processor core, respond to a second access request according to a second listening request, and send the second data from the cache of the second processor core to the first processor core.

[0072] In any of the above embodiments, for example, the inter-node consistency extension unit is used to communicate with other processor nodes (e.g.), receive listen requests and query directory listen extension filters, and perform cache consistency maintenance between processor nodes.

[0073] This inter-node consistency extension unit can filter listener requests that do not involve the first node, thereby reducing the response to unnecessary listener requests within the first node. This reduces bandwidth consumption pressure and power consumption within the node. Furthermore, providing this inter-node consistency extension unit facilitates flexible expansion of electronic devices. Without modifying other nodes, electronic devices can be expanded to any number of nodes. Moreover, as the number of processor nodes within an electronic device increases linearly, there is no need to increase the capacity of the directory memory within the processor nodes. This provides a performance optimization solution for building many-core systems.

[0074] For example, the capacity of the first consistent directory and the capacity of the second consistent directory in the directory snooping extended filter within the same node can be set and maintained independently, and there is no necessary relationship between them. For instance, the eviction of the first consistent directory can be performed without notifying other related consistent directories; it can directly clear or overwrite the relevant directory entries. The eviction of the second consistent directory, however, will send a snooping request to notify the relevant consistent directories to perform the eviction operation. Alternatively, the eviction of the first consistent directory can also notify the relevant consistent directories.

[0075] For example, in an electronic device of at least one embodiment, the directory snooping extended filter communicates directly with the inter-node consistency extended unit; or, for example, the first node further includes a switching unit; the inter-node consistency extended unit is configured to communicate (indirectly) with the directory snooping extended filter through the switching unit; for example, the switching unit, the inter-node consistency extended unit, and the directory snooping extended filter are all connected to the consistency interconnect bus, and the inter-node consistency extended unit and the directory snooping extended filter communicate through the switching unit.

[0076] For example, in an electronic device of at least one embodiment, a first node includes p processor cores, and a second part of the directory vector includes q bits for marking the p processor cores respectively, where p and q are both positive integers, and q is greater than or equal to p. For example, the first node includes 4 processor cores, and the second part of the directory vector includes 4 bits for marking the 4 processor cores respectively, for example, the first / second / third / fourth bits of the 4 bits are used to mark the first / second / third / fourth processor core respectively.

[0077] For example, in an electronic device of at least one embodiment, multiple nodes are divided into multiple node partitions, each of which includes at least one node. The first part of the directory vector is multi-bit wide, with each bit representing information about a node. It indicates whether other nodes besides the first node cache the first data by recording area information. For example, in addition to the first and second parts mentioned above, the directory vector may also include a third part. For example, the first part indicates whether a node partition including other nodes caches object data, the third part indicates whether the node partition where the first node itself is located caches object data, and the second part is used to indicate whether at least one cache caches object data if the first node caches object data. Therefore, in this embodiment, the directory vector also includes node partition information, which allows for partition management of listening requests, etc., based on node partitions, further alleviating the bandwidth occupancy pressure of inter-node partition transmission. Since the data flow transmitted between node partitions is reduced, the overall power consumption of the system is also reduced. In some examples of this embodiment, the access latency can also be effectively shortened, improving the overall system performance.

[0078] Correspondingly, in the data processing method of at least one embodiment of this disclosure, operation steps corresponding to the above-described structure are also performed, which will not be described in detail here.

[0079] Some embodiments and examples of this disclosure will now be described with reference to the accompanying drawings.

[0080] Figure 3 A schematic diagram of a processor node of an electronic device according to at least one embodiment of the present disclosure is shown. The electronic device includes a plurality of processor nodes, including node 200. Processor node 200 is, for example, a single processor chip or an independent part of a processor chip, and constitutes the electronic device together with other processor nodes.

[0081] For example, multiple chips in this electronic device can be packaged using either a multi-chip module (MCM) or a chiplet. MCM (Multi-Chip Module) packaging technology encapsulates multiple independent chips within a single module. Chiplet refers to breaking down a complete chip design into multiple smaller modules (chips), each module being called a chiplet; these chiplets can be designed and manufactured independently, and then integrated together using interconnect technology to form a complete chip system.

[0082] In embodiments of this disclosure, a node refers, for example, to a chip that includes one or more processor cores, one or more memories, and one or more (inter-chip) coherence extension units.

[0083] like Figure 3 As shown, processor node 200 is a multi-processor, multi-cache system that uses directory sniffing filters to maintain cache coherency. Processor node 200 includes n+1 processor cores 110~11n, n+1 caches (hereinafter also referred to as "caches") 120~12n, a coherency interconnect bus 114, m+1 memory controllers 140~14m, m+1 system memory 130~13m, m+1 directory sniffing filters 150~15m, a coherency extension unit 115, and a directory sniffing extension filter 15X, where n and m are both integers greater than or equal to 0.

[0084] Here, directory snooping filters 150~15m are examples of the above-mentioned "directory snooping filters", including the second consistent directory; directory snooping extended filter 15X is an example of the above-mentioned "directory snooping extended filter", including the first consistent directory; and consistency extension unit 115 is an example of the above-mentioned "inter-node consistency extension unit".

[0085] For example, each of caches 120-12n is configured to store data storage information corresponding to at least one piece of data. For example, caches 120-12n can be multiple dedicated caches used by processor cores 110-11n respectively. In addition, the processor node 200 may also include shared caches for processor cores 110-11n, for example, one shared cache shared by every two processor cores.

[0086] like Figure 3As shown, the above m+1 memory controllers 140~14m correspond to m+1 system memories 130~13m respectively; the above m+1 memory controllers 140~14m correspond to m+1 directory snooping filters 150~15m respectively. These memory controllers are used to manage and control access to and operation of system memories, and as consistency nodes, they connect the corresponding directory snooping filters and system memories to the consistency interconnect bus 114.

[0087] These directory snooping filters are used to maintain the consistency of data in the corresponding system memory within the caches 120-12n. More specifically, directory snooping filters 150-15m can help track the cached data status in caches 120-12n; for example, for a certain data, the cached data status may include: one or more caches 120-12n containing only a single copy of the cached data, multiple copies of the cached data, or the data existing only in main memory. Directory snooping filters 150-15n and directory snooping extended filters 15X track the cached data status of caches 120-12n in processor cores 110-11n and store the tracked status information in the directories of directory snooping filters 150-15n and directory snooping extended filters 15X. When the consistency broker snooping bus detects a consistent transaction, it queries directory snooping extended filters 15X or, if necessary, the tracked status information in directory snooping filters 150-15n, and the corresponding directory snooping filter or directory snooping extended filter issues a snooping request to complete the consistency maintenance.

[0088] For example, such as Figure 3 As shown, the coherence interconnect bus 114 is directly coupled to caches 120-12n and also directly coupled to memory controllers 140-14m. The coherence interconnect bus 114 is a common communication trunk for information transmission; for example, the coherence interconnect bus 114 is a transmission harness composed of electronic components such as wires in the chip.

[0089] like Figure 3 As shown, in processor node 200, the coherence extension unit 115 is used to communicate with other processor nodes (e.g., chips) and is also connected to the directory listener extension filter 15X to hierarchically manage listener requests for node 200 by querying the directory listener extension filter 15X.

[0090] Although Figure 3 The specific number of directory snooping filters, processor cores, memory controllers, caches, and system memory is shown, but embodiments of this disclosure are not limited to these specific numbers, which can be set to any value as needed.

[0091] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), wearable electronic devices, etc.; fixed terminals such as digital TVs, desktop computers, smart home devices, etc.; and server devices such as local area network servers, wide area network servers, cloud servers, etc.

[0092] For example, in at least one embodiment of this disclosure, the system memory can be main memory (e.g., DRAM), or it can be external memory connected to the processor node 200, such as hard disk, floppy disk, optical disk, USB flash drive, etc.

[0093] For example, memory controllers, directory snooping filters, and consistency extension units can be implemented using software, hardware, firmware, or any feasible combination thereof. For instance, they can include logic devices such as registers, latches, flip-flops, caches, inverters, etc. For example, the processor core can be a central processing unit (CPU) or other processing units with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA) or a tensor processing unit (TPU); for example, the central processing unit (CPU) can be based on x86, RISC-V, or ARM architectures.

[0094] The embodiments disclosed herein do not limit the type of processor core, the microarchitecture used, the instruction set, etc. For example, the x86 instruction set and corresponding microarchitecture can be used, the Arm instruction set and corresponding microarchitecture can be used, or the RISC-V instruction set and corresponding microarchitecture can be used, etc.

[0095] Similarly, the embodiments of this disclosure do not limit the type of cache, system memory, etc. It should be noted that, in the embodiments of this disclosure, a processor's dedicated cache refers to a cache that can only be accessed by that processor, while a shared cache can be accessed by multiple processors.

[0096] For example, when processor core 110 needs to read certain data, it first accesses at least one dedicated cache 120 used by processor core 110. When the dedicated cache 120 does not store the data information that processor core 110 needs to read, processor core 110 then accesses the next-level cache. After accessing the dedicated cache, processor core 120 can continue to access at least one shared cache (not shown in the figure) or system memory used by processor core 110.

[0097] For example, each cache includes a cache control module that can access each storage unit in the cache to read the content stored in that unit and then parse that content. When determining whether the data to be read in a read request issued by the processor core is stored in a certain cache, the cache control module performs this determination. That is, the cache control module reads and parses the content from the storage unit, compares the parsed content with the data to be read determined based on the read request, and thus determines whether the data stored in the storage unit matches the data to be read.

[0098] Figure 4 This is a schematic diagram of the directory organization structure of a consistent directory of a directory sniffing filter according to at least one embodiment of the present disclosure. This directory organization structure is used for the above-mentioned directory sniffing extended filter 15X, and can also be further used for directory sniffing filters 150~15n.

[0099] like Figure 4 As shown, the consistency directory is a data table containing multiple directory entries (or target items). Each directory entry can include multiple data items, and... Figure 2 Compared to the scenario shown, a directory vector includes multiple parts, such as: The first part indicates whether other nodes have backups.

[0100] The second part represents the cache ID vector of this node.

[0101] For example, in one example, the first part is 1 bit wide, where a value of "1" indicates that the caches of other nodes (excluding the current node) have a backup of the data corresponding to the current directory entry, and a value of "0" indicates that the caches of other nodes do not have a backup of the data. Whether the current node's own cache has a backup of the data can be determined by querying the second part.

[0102] For example, in another example, the size of the first part is more than 1 bit, and each bit represents a node in the system to indicate whether that node has a backup of a certain data; for example, if the system has 5 nodes, the size of the first part is 5 bits, and each bit represents one of the 5 nodes to indicate whether that node has a backup of a certain data.

[0103] For example, in another example, the first part is a degenerate record, and the second part is a precise record. The first part can be one bit wide or more bits wide, where each bit represents a direction towards the remote node, for example: There is only one direction to the remote node, so a width of 1 bit can be used; or There are two directions to reach the remote node; one can take a width of 2 bits. There are 4 directions to reach the remote node, and the width can be 4 bits.

[0104] In this case, the specific bit width of the first part can be determined by the interconnection structure of the system. Once the interconnection structure of the system is determined, the bit width of the first part of the directory vector, "whether other nodes have backups", can be selected accordingly.

[0105] Similarly, once the number of processor cores in each node is determined, the bit width of the second part of the directory vector, "the local node cache ID vector," is also determined.

[0106] For example, for the second part of a precise record, if the current node includes two caches, two bits can be used to correspond to the two caches of the current node respectively, with each bit valued as "1" or "0" indicating whether the corresponding cache has a backup of the data; or, if the current node includes four caches, four bits can be used to correspond to the four caches of the current node respectively, with each bit valued as "1" or "0" indicating whether the corresponding cache has a backup of the data.

[0107] For the meaning and examples of the other data items for each of the above directory items, please refer to the above references. Figure 2 The description will not be repeated here.

[0108] In one example, each directory entry can be 32 bits. For instance, the directory validity bit is 1 bit, the owner ID is 4 bits, the directory vector is 3 bits (where the first part (whether other nodes have backups) is 1 bit and the second part (this node's cache ID vector) is 2 bits), the cache status information is 3 bits, and the directory address flag is 21 bits. For example, during operation, the consistency directory is stored in static physical memory (SRAM). For example, if the access linewidth of this SRAM is 128 bits, meaning that each read and write operation is performed at a 128-bit granularity, then each read and write operation involves 4 directory entries. The organization of SRAM can be varied, and the embodiments of this disclosure do not limit this. For example, reads and writes can be performed at other granularities; furthermore, the embodiments of this disclosure do not specifically limit the content and bit width covered by each directory information entry.

[0109] Figure 5AA schematic diagram of an electronic device according to an embodiment of the present disclosure is shown. The electronic device in this embodiment is a two-node system. As shown, the system has two nodes, and the topology for cache consistency maintenance of each node can be, for example... Figure 3 The example shown.

[0110] In a multi-node system, the "requesting node" refers to the node that sends the access request, while the "home node" refers to the node where the memory to be accessed by the access request resides. That is, the requesting node and the home node are relative to a particular operation and are not fixed.

[0111] for Figure 5A In such a two-node system, for example, in operation 1, the left node's processor core 0 sends a read request to access the right node's memory. In operation 1, the left node is the requesting node, and the right node is the home node. For example, in operation 2, the left node's processor core 1 sends a read request to access the left node's memory. In operation 2, both the requesting node and the home node refer to the left node. For example, in operation 3, the right node's processor core 0 sends a read request to access the left node's memory. In operation 3, the right node is the requesting node, and the left node is the home node.

[0112] exist Figure 5A In this diagram, we will use the left-hand node as the requesting node and the right-hand node as the home node as an example for a non-restrictive description. The requesting node and the home node are functionally identical; however, the diagram also schematically shows the processor core and inter-chip coherence extension unit for the requesting node, while the home node also schematically shows the system memory.

[0113] Each of the two nodes has, for example, two processor cores and two corresponding caches, and communicates with each other through their respective inter-chip coherence extension units. Furthermore, the directory vectors of the directory listener extension filters and the directory entries in the directory listener filters of both nodes consist of a 1-bit first part and a 2-bit second part. The 1-bit first part indicates whether the remote node has a backup of the corresponding data; the 2 bits of the second part are used to indicate whether the local node has backups of the corresponding data in its two caches.

[0114] like Figure 5AIn the illustrated states, when both processor core caches of the requesting node have data backups, the directory vector of the directory entry in the home node's directory listener extended filter (and directory listener filter) is {remote node vector = 1b, local node vector = 00b}, indicating that there is no backup of the data in the home node's cache, but there is a backup of the data in the requesting node's cache. If the directory vector of the requesting node's directory listener extended filter (and directory listener filter) is {remote node vector = 0b, local node vector = 11b}, it indicates that there are backups of the data in both caches of the requesting node, but no backup of the data in the home node's cache. In this case, when the directory listener filter or directory listener extended filter in the home node sends a listen request, it only needs to send it to the requesting node.

[0115] In at least one example, for a multi-node system, when an extended directory listener filter is added, the directory vector of the directory listener filter corresponding to the memory controller within a node can be more concise, only needing to record the cache status of the current node and whether other nodes have the backup.

[0116] The following is combined with Figure 5A The two-node system shown illustrates some exemplary processes for handling data access requests.

[0117] Scenario 1: The directory listener filter 0 of the right-hand node is not hit.

[0118] First, the processor core 0 of the requesting node (the left node in the diagram) issues a read request 1 to access the system memory 0 corresponding to the memory controller 0 of the home node (the right node in the diagram) in order to access data A (an example of the first data) in the system memory 0. At this time, data A has no cached backup in the requesting node.

[0119] Then, read request 1 is sent to the inter-chip consistency extension unit of the requesting node via the interconnect within the requesting node (e.g., a network on-chip (NOC)). This inter-chip consistency extension unit queries the consistency directory (an example of the first consistency directory) of the directory listener extension filter, and the query result is a miss. The inter-chip consistency extension unit continues to forward read request 1 to the home node; read request 1 is routed to the home node's memory controller 0 via the home node's inter-chip consistency extension unit and the interconnect within the home node (e.g., a NOC). Memory controller 0 queries the directory listener filter 0 based on the address of the data A to be read, and the query result is also a miss.

[0120] The memory controller 0 sends a read request to the system memory 0 and returns the data A to be read. The address of the data A is recorded in a directory entry in the consistency directory of the directory listener filter 0. For example, the specific row of the SRAM in the directory is stored by the low-order index of the address. The high-order bits of the address are written to the directory address flag field in the directory entry. The directory validity is set to 1. The owner ID is pointed to the processor core 0 (cache) of the left node. The directory vector is set to 3'b100, indicating that other nodes have a backup of the data but the cache in this node does not have a backup of the data. The cache state is set to an appropriate state, such as exclusive state.

[0121] When the data A being read returns from the home node to the inter-chip consistency extension unit of the requesting node, the inter-chip consistency extension unit records the address of data A in a directory entry in the consistency directory of the directory listener extension filter. For example, it stores the specific row of the SRAM of the directory through the low-order index of the address, writes the high-order bits of the address into the directory address flag field in the directory entry, sets the directory validity bit to 1, points the owner ID to the cache of the local node's processor core 0, and sets the directory vector to 3'b001, indicating that other nodes do not have a backup of the data, but the cache of the local node's processor core 0 has the backup. Then, the data A being read is transmitted to the requesting node's processor core 0 through the intra-node routing path and cached in the cache of processor core 0.

[0122] Scenario 2: The directory listener filter 0 of the right-hand node is hit.

[0123] After the processor core 0 has a backup of data A in its cache through the above operations, the requesting node's processor core 1 issues a read request 2. The address of the data A to be read is the same as that in read request 1, which requires accessing the home node's memory controller 0.

[0124] Similarly, read request 2 is routed to the inter-segment consistency extension unit of the requesting node. This unit queries the consistency directory (an example of the first consistency directory) of the directory listener extension filter. The query result is a hit, and it confirms through directory vector 3'b001 that other nodes do not have a backup of the data, but the cache of processor core 0 of this node has the backup. Therefore, the directory listener extension filter only sends a listener request to processor core 0 of the requesting node (without sending a listener request outside the node). After receiving the listener request, processor core 0 of the requesting node directly returns the cached data A to processor core 1 of the requesting node. The data A cached by processor core 0 can be invalidated or shared depending on the type of listener request (actual needs); the cache of processor core 1 of the requesting node caches the data A.

[0125] The requesting node's processor core 1 sends a read response confirmation message to the requesting node's inter-chip consistency extension unit; the requesting node's inter-chip consistency extension unit updates the directory entry in the consistency directory of the directory listening extension filter 0 corresponding to data A, and sets the directory vector to 3'b011, indicating that other nodes do not have a backup of this data, but the caches of processor core 0 and processor core 1 of this node both have a backup of this data.

[0126] Then, the inter-chip consistency extension unit of the requesting node sends an update request to the directory listener filter 0 corresponding to the memory controller 0 of the home node; after passing through the inter-chip consistency extension unit of the home node, the directory listener filter 0 corresponding to the memory controller 0 of the home node receives the directory update request and updates the consistency directory of the directory listener filter 0. Here, the directory vector is kept as 3'b100, indicating that other nodes have a backup of the data while the cache in this node does not have a backup of the data, but the cache state is set to an appropriate state, such as set to shared state.

[0127] at this time, Figure 5A The status after the operation is completed is shown.

[0128] Figure 5B A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown, wherein the electronic device in this embodiment is a three-node system. For example... Figure 5B As shown, the system has 3 nodes, and the topology for maintaining cache consistency on each node can be, for example... Figure 3 The illustrated embodiment. In this three-node system, the three nodes are connected in series, as shown in the figure. The left and right nodes are respectively connected to the middle node, thereby enabling them to communicate with each other.

[0129] exist Figure 5BIn this diagram, we will use the left-hand node as the requesting node, the middle node as the passing node, and the right-hand node as the home node as an example for a non-restrictive description. The requesting node, passing node, and home node are functionally identical; however, in the diagram, the requesting node only schematically shows the processor core, inter-chip consistency extension unit, and directory listener extension filter; the passing node only schematically shows the inter-chip consistency extension unit and directory listener extension filter; and the home node only schematically shows the inter-chip consistency extension unit, directory listener extension filter, memory controller 0, directory listener filter 0, and system memory 0.

[0130] Each of the three nodes has, for example, two processor cores and two corresponding caches, and communicates with each other through its respective inter-chip coherence extension unit. Furthermore, the directory vector of the directory listener extension filter for each of the two nodes, and the directory entries in the directory listener filter's directory, consists of a 2-bit first part and a 2-bit second part. The 2 bits of the first part indicate whether the corresponding data is backed up in the two remote nodes; the 2 bits of the second part are used to indicate whether the corresponding data is backed up in the two caches of the local node.

[0131] like Figure 5B In the state shown, the directory vector of the home node's directory listening extended filter (and directory listening filter) is {remote node vector = 10b, local node vector = 00b}, indicating that there is no backup of the data corresponding to the directory entry in the home node's cache, but there is a backup of the data in the cache of the remote node to the left of the home node.

[0132] The directory vector of the directory sniffing extended filter (and the directory sniffing filter) of the traversing node is {remote node vector = 10b, local node vector = 00b}, which means that there is no backup of the data corresponding to the directory entry in the two caches of the traversing node, but there is a backup of the data in the cache of the remote node to the left of the traversing node.

[0133] The directory vector of the directory listener extended filter (and directory listener filter) of the request node is {remote node vector = 00b, local node vector = 11b}, which means that the data corresponding to the directory entry is backed up in both caches of the request node, but not in the caches of other nodes (nodes to the left and / or nodes to the right).

[0134] For example, when the home node's directory listener filter sends a listener request as needed, it only needs to send it to the left node, without needing to send the listener request internally within the home node. Upon receiving the listener request (which is an external listener request), the inter-chip consistency extension unit of the passing node queries the directory of the same node's directory listener extension filter. Based on the query result, it only sends the listener request to the left node, without needing to send and process the listener request internally within the passing node. Similarly, upon receiving the listener request (which is an external listener request), the requesting node's inter-chip consistency extension unit queries the directory of the same node's directory listener extension filter, and then, based on the result, sends the listener request to processor core 0 and processor core 1, and processes the listener request accordingly.

[0135] The directory vector of the hierarchical records in the embodiments of this disclosure can be extended to any multi-node system without modifying the directory storage capacity and design.

[0136] Figure 5C A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown. The electronic device in this embodiment is a multi-node system. As shown, the system has more than three nodes, for example, m rows and n columns (m and n are both positive integers greater than or equal to 2) of nodes. The topology for cache consistency maintenance of each node can be, for example... Figure 3 The illustrated embodiment. In this system, multiple nodes (e.g., via a network on-chip (NOC)) are connected and communicate with each other in a network manner.

[0137] In this embodiment, the first part of the directory vector indicating the status of remote nodes has a width of 4 bits. These 4 bits represent whether the routing is upward, downward, left, or right, respectively, according to the routing rules; that is, the nodes above, below, left, and right do not have corresponding data backups. The width of the second part of the directory vector indicating the status of local nodes depends on the number of processors on each node. Once the node design is fixed, this second part is also a fixed value and will not change as the number of nodes in the system increases. Therefore, regardless of the number of nodes in the system or the number of processor cores on each node, each node in this embodiment can accurately record the directory vector hierarchically, allowing listening requests to more precisely locate the cache position to process the listening request on the forwarded path.

[0138] In the above embodiments, the directory snooping extended filter interfaces with the inter-chip consistency extended unit. However, the connection location of the directory snooping extended filter is not limited to the inter-chip consistency extended unit, and it can also interface with other units in the system.

[0139] Figure 6A schematic diagram of a processor node 300 of an electronic device according to at least one embodiment of the present disclosure is shown. The electronic device includes a plurality of processor nodes, the plurality of processor nodes including node 300. The processor node 300 is, for example, a single processor chip or an independent part of a processor chip, and constitutes the electronic device together with other processor nodes.

[0140] like Figure 6 As shown, processor node 300 is a multi-processor, multi-cache system that uses directory snooping filters to maintain cache coherency. Processor node 300 includes n+1 processor cores 210-21n, n+1 caches (hereinafter also referred to as "caches") 220-22n, a coherency interconnect bus 214, m+1 memory controllers 240-24m, m+1 system memories 230-23m, m+1 directory snooping filters 250-25m, a coherency extension unit 215, and a directory snooping extension filter 25X, where n and m are both integers greater than or equal to 0. Here, directory snooping filters 250-25m are examples of the aforementioned "directory snooping filters," and directory snooping extension filter 25X is an example of the aforementioned "directory snooping extension filter."

[0141] Except for the differences described below, processor node 300 is the same as processor node 200, so it will not be described again.

[0142] like Figure 6 As shown, in processor node 300, the coherence extension unit 215 is used to communicate with other processor nodes (e.g., chips) and is communicatively connected to the switching unit 210; the directory listener extension filter 25X is also communicatively connected to the switching unit 210. The coherence extension unit 215 and the directory listener extension filter 25X communicate indirectly through the switching unit 210, thereby allowing hierarchical management of listener requests for node 300 by querying the directory listener extension filter 25X. The switching unit 210 is connected to the coherence interconnect bus 214 and configured to control communication within node 300 via the coherence interconnect bus 214; furthermore, inter-node interconnection can also be accomplished through the switching unit 210 and the coherence extension unit 215 together.

[0143] For example, in Figure 6In the scenario shown, multiple nodes are divided into multiple node partitions, each containing at least one node. The first part of the directory vector indicates whether other nodes besides the first node cache the first data by recording region information. For example, in addition to the first and second parts, the directory vector may also include a third part. The first part indicates whether a node partition containing other nodes caches a certain data, the third part indicates whether the node partition containing the first node itself caches that data, and the second part is used to indicate which cache within the first node partition caches that data if the first node caches it.

[0144] Some embodiments of this disclosure also provide another data processing apparatus. Figure 7 This is a schematic diagram of a data processing apparatus provided for some embodiments of the present disclosure.

[0145] like Figure 7 As shown, the data processing apparatus 500 according to an embodiment of the present disclosure may include a processor 501 and a memory 502, which can be interconnected via a bus 503.

[0146] Processor 501 can perform various actions and processes according to the program or code stored in memory 502. Specifically, processor 501 can be an integrated circuit chip with signal processing capabilities. For example, the processor 501 can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the various methods and steps disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor, and can be an x86 architecture or an ARM architecture, etc.

[0147] The memory 502 is used for non-temporary storage of computer-executable instructions, and the processor 501 is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor 501, they implement the data processing method provided in at least one embodiment of this disclosure.

[0148] For example, memory 502 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0149] Embodiments of this disclosure also provide a non-transitory storage medium, which can be a non-transitory computer-readable storage medium. The non-transitory storage medium is used to non-transitory store computer-executable instructions that, when executed by a computer, implement the data processing methods provided in some embodiments of this disclosure.

[0150] Figure 8 This is a schematic diagram of a non-transitory storage medium provided in some embodiments of this disclosure.

[0151] like Figure 8 As shown, the non-temporary storage medium 600 can non-temporarily store computer-executable instructions 610, which, when executed by a computer, implement the data processing method provided in any embodiment of this disclosure.

[0152] Similarly, the non-transitory storage medium in the embodiments of this disclosure may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory used in the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0153] Embodiments of this disclosure also provide a computer program product or non-transitory storage medium, the computer program product including computer instructions, or the computer instructions stored in the non-transitory storage medium. A processor of a computer device reads the computer instructions, executes the computer instructions, and causes the computer device to perform a data processing method according to any embodiment of this disclosure.

[0154] The technical effects of the aforementioned data processing device and non-transitory storage medium are the same as those of the aforementioned data processing method, and will not be repeated here.

[0155] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing at least one executable instruction for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0156] In general, the various exemplary embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of embodiments of this disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0157] The following points should be noted regarding this disclosure: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0158] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0159] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0160] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A data processing method for a first node among a plurality of nodes that are communicatively connected to each other, wherein, The first node includes a directory listening extended filter for the first node. The directory listening extended filter includes a first consistent directory. The directory vector of each directory entry in the first consistent directory includes a first part and a second part for object data. The first part is used to indicate whether other nodes besides the first node cache the object data, and the second part is used to indicate whether the first node caches the object data. The data processing method includes: In response to the directory listening extended filter receiving a query request for the first data, the directory entries of the first consistency directory are queried to determine whether the first data is cached in the first node and whether it is cached in other nodes besides the first node; The first node receives an external listening request regarding the cache consistency status of the first data; In response to the first node being a passing node that is a listening request from outside the node, the query request is generated by the listening request from outside the node. In response to the directory listening extended filter querying the directory entries of the first consistency directory and determining that the first data is not cached in the first node, the first node forwards the external listening request without processing it.

2. The data processing method according to claim 1, wherein, The first node also includes a first processor core. The data processing method further includes: The first processor core generates a first access request for the first data, wherein the storage address of the first data is located in a node other than the first node. The query requirement is generated based on the first access request; Based on the first query result of querying the directory entries of the first consistency directory, the directory listening extended filter sends a first listening request.

3. The data processing method according to claim 2, wherein, The first node also includes a second processor core, which includes at least one cache. Based on the first query result of querying the directory entries of the first consistency directory, the directory listening extended filter sends a first listening request, including: In response to determining, based on the first query result, that the first data has been cached in the cache of the second processor kernel, the directory listening extended filter sends the first listening request to the second processor kernel.

4. The data processing method according to claim 3 further includes: The second processor core responds to the first access request based on the first listening request and sends the first data from the cache of the second processor core to the first processor core.

5. The data processing method according to claim 2, wherein, Based on the first query result of querying the directory entries of the first consistency directory, the directory listening extended filter sends a first listening request, including: In response to determining, based on the first query result, that the first data has been cached in nodes other than the first node, the first listening request is sent to the other nodes other than the first node.

6. The data processing method according to claim 1, wherein, The plurality of nodes are divided into a plurality of node partitions, each of which includes at least one node. The first part indicates whether other nodes besides the first node have cached the first data by recording area information.

7. The data processing method according to claim 1, wherein, The first node's inter-node consistency extension unit queries the first consistency directory of the directory listening extension filter according to the query requirements.

8. The data processing method according to claim 1, wherein, The first node further includes a first processor core, a first memory controller, and a directory snooping filter for the first memory controller. The directory snooping filter includes a second consistent directory, and the directory vector for each directory entry in the second consistent directory also includes the first portion and the second portion for the object data. The data processing method further includes: The first processor core generates a second access request for the second data, wherein the storage address of the second data is located within the first node. Based on the second access request, the directory entries of the second consistency directory are queried to obtain a second query result, which is used to determine whether the second data is cached in the first node and whether it is cached in other nodes besides the first node. Based on the second query result, the second directory listening filter issues a second listening request.

9. The data processing method according to claim 8, wherein, The first node also includes a second processor core, which includes at least one cache. The data processing method further includes: In response to the second query result determining that the second data has been cached in the cache of the second processor core, the second processor core responds to the second access request according to the second listen request and sends the second data from the cache of the second processor core to the first processor core.

10. An electronic device comprising a plurality of nodes communicatively connected to each other, wherein, The plurality of nodes includes the first node. The first node includes a directory listening extended filter for the first node. The directory listening extended filter includes a first consistent directory. The directory vector of each directory entry in the first consistent directory includes a first part and a second part for object data. The first part is used to indicate whether other nodes besides the first node cache the object data, and the second part is used to indicate whether the first node caches the object data. The first node is configured to, in response to the directory listening extended filter receiving a query request for the first data, query the directory entries of the first consistency directory to determine whether the first data is cached within the first node and whether it is cached in other nodes besides the first node. The first node further includes an inter-node consistency extension unit, which is configured to receive an external listening request for the cache consistency status of the first data. The directory listening extended filter is further configured to generate the query request in response to the first node being a passing node of the external listening request; The inter-node consistency extension unit is further configured to, in response to querying the directory entries of the first consistency directory and determining that the first data is not cached in the first node, forward the external listening request and not process the external listening request.

11. The electronic device according to claim 10, wherein, The first node also includes a first processor core. The first processor core is configured to generate a first access request for the first data, the storage address of which is located on a node other than the first node. The inter-node consistency extension unit is configured to generate the query request based on the first access request. The directory listening extended filter is configured to send a first listening request based on the first query result of querying the directory entries of the first consistent directory.

12. The electronic device according to claim 11, wherein, The first node also includes a second processor core, which includes at least one cache. The directory listening extended filter is further configured to send the first listening request to the second processor kernel in response to determining, based on the first query result, that the first data has been cached in the cache of the second processor kernel.

13. The electronic device according to claim 12, wherein, The second processor core is configured to respond to the first access request according to the first listening request and send the first data from the cache of the second processor core to the first processor core.

14. The electronic device according to claim 11, wherein, The directory listening extended filter is further configured to send the first listening request to the nodes other than the first node in response to determining, based on the first query result, that the first data has been cached in other nodes besides the first node.

15. The electronic device according to claim 10, wherein, The plurality of nodes are divided into a plurality of node partitions, each of which includes at least one node. The first part indicates whether other nodes besides the first node have cached the first data by recording area information.

16. The electronic device according to claim 10, wherein, The first node also includes a switching unit. The inter-node consistency extension unit is configured to communicate with the directory snooping extension filter through the exchange unit.

17. The electronic device according to claim 10, wherein, The first node further includes a first processor core, a first memory controller, and a directory snooping filter for the first memory controller. The directory snooping filter includes a second consistent directory, and the directory vector for each directory entry in the second consistent directory also includes the first portion and the second portion for the object data. The first processor core is configured to generate a second access request for the second data, wherein the storage address of the second data is located within the first node. The first memory controller is configured to query the directory entries of the second consistency directory according to the second access request to obtain a second query result, which is used to determine whether the second data is cached in the first node and whether it is cached in other nodes besides the first node. The second directory listening filter is configured to issue a second listening request based on the second query result.

18. The electronic device according to claim 17, wherein, The first node also includes a second processor core, which includes at least one cache. The second processor core is configured to, in response to the second query result determining that the second data has been cached in the cache of the second processor core, respond to the second access request according to the second listen request, and send the second data from the cache of the second processor core to the first processor core.

19. A data processing apparatus, comprising: Memory, configured to store computer-executable instructions; as well as At least one processor configured to execute the computer-executable instructions, The computer-executable instructions, when executed by the at least one processor, implement the method according to any one of claims 1-9.

20. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the method according to any one of claims 1-9 is implemented.

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