Weight updating method, storage-computation integrated system, electronic device and storage medium

Abstract

A weight updating method, a memory-compute integrated system, an electronic device, and a storage medium. The weight updating method comprises: obtaining a target weight matrix; receiving a calculation result obtained after a memory-compute integrated array mapped as the target weight matrix performs forward calculation, and performing inverse solution processing on the calculation result to obtain an inverse solution weight matrix; and obtaining an updated weight matrix based on the target weight matrix and the inverse solution weight matrix, wherein the updated weight matrix is used to update the weight of the memory-compute integrated array mapped as the target weight matrix. The weight updating method obtains the inverse solution weight matrix which fuses non-ideal factors in the forward calculation by performing inverse solution processing on the calculation result of the forward calculation, obtains the updated weight matrix used to guide the actual weight updating based on the inverse solution weight matrix and the target weight matrix, and can effectively improve the efficiency of the weight updating, improve the calculation accuracy, and reduce the time and power consumption.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a weight update method, a memory computing system, an electronic device, and a storage medium. Background Technology

[0002] In-memory computing technology has been developing continuously in recent years. As a new computing strategy, in-memory computing technology can perform calculations directly on the memory, which can effectively reduce the time and energy consumption of data transfer between storage units and computing units. It breaks through the bottleneck of the storage wall in the von Neumann architecture, has the advantage of high energy efficiency, and can simplify the complexity of matrix-vector multiplication to O(1), thereby realizing parallel computing in the array naturally, with the advantage of high computing power. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a weight update method, the weight update method comprising: obtaining a target weight matrix; receiving a calculation result obtained by performing forward computation on an in-memory computing array mapped to the target weight matrix, and performing inverse solving on the calculation result to obtain an inverse weight matrix; and obtaining an updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix.

[0004] For example, at least one embodiment of the weight update method provided in this disclosure further includes: receiving a first weight matrix, wherein the first weight matrix is ​​obtained by performing a read operation on the values ​​stored in each in-memory computing device of the in-memory computing array mapped to the target weight matrix.

[0005] For example, in at least one embodiment of the weight update method provided in this disclosure, obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix includes: subtracting the inverse weight matrix from the target weight matrix to obtain the second weight matrix; and subtracting the first weight matrix from the second weight matrix to obtain the updated weight matrix.

[0006] For example, in a weight update method provided in at least one embodiment of this disclosure, obtaining an updated weight matrix based on the target weight matrix and the inverse weight matrix includes: subtracting the inverse weight matrix from the target weight matrix to obtain a plurality of deviation weight values; retaining deviation weight values ​​greater than or equal to a threshold to obtain a second weight matrix; and subtracting the first weight matrix from the second weight matrix to obtain the updated weight matrix.

[0007] For example, at least one embodiment of the weight update method provided in this disclosure further includes: determining the in-memory computing devices that need to be updated in the in-memory computing array according to the updated weight matrix; and performing a weight update operation on the in-memory computing devices that need to be updated.

[0008] For example, in a weight update method provided in at least one embodiment of this disclosure, the step of receiving the calculation result obtained after the in-memory computing array mapped to the target weight matrix performs forward computation, and performing inverse processing on the calculation result to obtain the inverse weight matrix, includes: acquiring input data; loading the input data onto the in-memory computing array mapped to the target weight matrix to perform the forward computation through the in-memory computing array; receiving the output data obtained after the in-memory computing array performs the forward computation; and performing inverse processing based on the input data and the output data to obtain the inverse weight matrix.

[0009] For example, in the weight update method provided in at least one embodiment of this disclosure, the input data is a full-rank matrix.

[0010] At least one embodiment of this disclosure also provides an in-memory computing system, the in-memory computing system including an in-memory computing array and a processor, the processor being configured to: acquire a target weight matrix; receive a calculation result obtained by performing forward computation on the in-memory computing array mapped to the target weight matrix, and perform inverse solving on the calculation result to obtain an inverse weight matrix; and obtain an updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix.

[0011] For example, at least one embodiment of the present disclosure provides a memory computing system that further includes: a read circuit configured to perform a read operation on the values ​​stored in each memory computing device of the memory computing array mapped to the target weight matrix to obtain a first weight matrix, wherein the processor is further configured to receive the first weight matrix.

[0012] For example, at least one embodiment of the in-memory computing system provided in this disclosure further includes: a programming circuit configured to map the target weight matrix onto the in-memory computing array, and after obtaining the updated weight matrix, to map the updated weight matrix onto the in-memory computing array to perform the weight update.

[0013] For example, in a memory computing system provided in at least one embodiment of this disclosure, the programming circuit includes: an input register configured to receive input data from the processor; a digital-to-analog converter configured to convert the input data from a digital signal to an analog voltage signal; an analog-to-digital converter configured to convert the output data from an analog current signal to a digital signal; and an output register configured to output the digital signal to the processor.

[0014] For example, in at least one embodiment of the in-memory computing system provided in this disclosure, the analog-to-digital conversion circuit includes: a first channel configured to sample the current flowing through each column of in-memory computing devices in the in-memory computing array; and a second channel configured to quantize the sampled current, wherein the sampling operation of the first channel on the current flowing through the current column of in-memory computing devices and the quantization operation of the second channel on the current obtained from sampling the previous column of in-memory computing devices are performed in parallel.

[0015] At least one embodiment of this disclosure also provides an electronic device, including: a memory that non-transitoryly stores computer-executable instructions; and a processor configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the processor, implement the weight update method described in any embodiment of this disclosure.

[0016] At least one embodiment of this disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the weight update method described in any embodiment of this disclosure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0018] Figure 1A This is a schematic diagram of a storage-computing array.

[0019] Figure 1B This is a schematic diagram of an exemplary in-memory computing unit;

[0020] Figure 2A A schematic diagram illustrating a verification operation for an in-memory computing array;

[0021] Figure 2B A schematic diagram illustrating computational operations performed by a type of in-memory computing array;

[0022] Figure 3 A flowchart of a weight update method provided in at least one embodiment of this disclosure;

[0023] Figure 4 This is a schematic diagram of a memory computing device that needs to be updated in a memory computing array provided in at least one embodiment of the present disclosure;

[0024] Figure 5 A flowchart illustrating an exemplary weight update method provided for at least one embodiment of this disclosure;

[0025] Figure 6A A schematic block diagram of an in-memory computing system provided for at least one embodiment of this disclosure;

[0026] Figure 6B A schematic block diagram of another in-memory computing system provided for at least one embodiment of this disclosure;

[0027] Figure 7 A schematic diagram of an exemplary analog-to-digital converter circuit provided for at least one embodiment of this disclosure; and

[0028] Figure 8 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0031] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numerals in each drawing.

[0032] Figure 1A A schematic diagram of a memory computing array is shown. Figure 1A As shown, the in-memory computing array includes multiple in-memory computing units and multiple word lines, bit lines, and source lines. The multiple in-memory computing units form an M-row N-column array, where M and N are both positive integers. Each in-memory computing unit typically includes a switching element and an in-memory computing device.

[0033] exist Figure 1A In the middle, WL <1> WL <2> ...WL <m>These represent the word lines for the first, second, ..., Mth rows, respectively. The control terminal (e.g., the gate of a transistor) of the switching element in each in-memory computing unit is connected to the corresponding word line for that row; BL <1> BL <2> BL <n>These represent the bit lines of the first column, second column, ..., Nth column, respectively. The in-memory computing unit in each column is connected to the corresponding bit line of that column; SL <1> SL <2> ……SL <m>These represent the source lines of the first row, the second row, ..., the Mth row, respectively. One end of the switching element (e.g., the source of a transistor) in the in-memory computing unit of each row is connected to the corresponding source line of that row.

[0034] In-memory computing units can function as both storage and computation units. For example, when used as storage, different resistance (or conductance, etc.) values ​​of the in-memory computing device can be used to store different data. When used as a computation unit, the conductance value of the in-memory computing device can be used as a number in a multiplication calculation (e.g., a multiplier). The in-memory computing array performs multiplication-accumulation calculations by applying an input voltage to the in-memory computing device, causing the input voltage and the current generated by the device to accumulate on the column lines. For example, multiplication can be performed based on Ohm's law, and addition can be performed based on Kirchhoff's current law.

[0035] For example, in embodiments of this disclosure, operations on the in-memory computing array include read operations, programming operations, and computation operations.

[0036] A read operation retrieves the values ​​stored in each in-memory computing device (IMD) within an in-memory computing array, such as 0, 1, or other values. IMD devices typically consist of an upper electrode, a lower electrode, and a dielectric layer between them. When the amplitude of the input voltage applied between the upper and lower electrodes of an IMD device is less than its threshold voltage, the device's resistance value remains unchanged. In this case, the current stored value of the IMD device can be read by applying a read voltage. The operation of applying a read voltage to an IMD device is called a read operation.

[0037] Programming operations can change the resistance values ​​of individual in-memory computing devices (IMDs) in an in-memory computing array, thereby altering the values ​​stored by each IMD. The resistance value of an IMD can be changed when the amplitude of the input voltage applied between its upper and lower electrodes exceeds its threshold voltage. For example, the resistance value of an IMD can be decreased or increased based on the set or reset voltage applied between its upper and lower electrodes, thus placing the IMD in different resistance states. For instance, when an IMD is in a low-resistance state, its corresponding stored value is 0; when it is in a high-resistance state, its corresponding stored value is 1. For example, the set voltage can be a positive voltage pulse, and the reset voltage can be a negative voltage pulse. In the embodiments of this disclosure, the operation of applying a set or reset voltage to an IMD can be referred to as a programming operation (or a write operation).

[0038] Figure 1B A schematic diagram of an exemplary in-memory computing unit is shown. Figure 1B As shown, the in-memory computing unit includes a transistor M1 and an in-memory computing device (RRAM). For example, when transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL, and transistor M1 is turned on when the word line terminal WL is high. The first terminal of transistor M1 can be the source and is configured to be connected to the source line terminal SL, so that transistor M1 can receive a reset voltage through the source line terminal SL. The second terminal of transistor M1 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of the in-memory computing device (RRAM). The first terminal (e.g., the positive terminal) of the in-memory computing device (RRAM) is connected to the bit line terminal BL, so that the in-memory computing device (RRAM) can receive a set voltage through the bit line terminal BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL, and transistor M1 is turned on when the word line terminal WL is low. It should be noted that the structure of the in-memory computing unit can also be implemented in other ways, such as a structure in which the second terminal of the in-memory computing device (RRAM) is connected to the source line terminal SL, etc. The embodiments disclosed herein do not limit this.

[0039] The word line terminal WL applies a voltage to the gate of transistor M1, thereby controlling its on or off state. When performing write operations on the Residual RAM (RRAM), such as set or reset operations, transistor M1 must first be turned on; that is, a turn-on voltage must be applied to the gate of transistor M1 through the word line terminal WL. After transistor M1 is turned on, voltages can be applied to the RRAM through the source line terminal SL and the bit line terminal BL to change its resistance state. For example, a set voltage can be applied through the bit line terminal BL to put the RRAM in a low-resistance state; conversely, a reset voltage can be applied through the source line terminal SL to put the RRAM in a high-resistance state. For example, the resistance of the high-resistance state can be more than ten times, such as more than one hundred or one thousand times, the resistance of the low-resistance state.

[0040] After programming the in-memory computing device, a verification operation can also be performed to ensure that the resistance value of the in-memory computing device reaches the expected resistance value. Figure 2A This is a schematic diagram illustrating a verification operation performed on a memory-based computing array. Figure 2A As shown, when performing verification operations on in-memory computing devices (IMCs), it is typically necessary to first turn on the transistor M1 corresponding to the IMC to be read (e.g., RRAM1) (e.g., by applying an on-state voltage to the gate of transistor M1 through the word line terminal WL), then ground the source line terminal SL, and provide a DC voltage to the IMC RRAM1 to be read. When verifying IMC RRAM1, it is necessary to turn off the transistors (e.g., M2) of other IMCs (e.g., RRAM2). For example, a DC voltage can be applied to the bit line terminal BL, and a sensing amplifier (SA) can be used to read the current flowing through IMC RRAM1; the SA can output a digital output code based on the detected current, which directly reflects the value stored in the IMC. For example, when the resistance value reflected by the SA deviates from the expected resistance value, the in-memory computing device can be set or reset accordingly to change the resistance value of the in-memory computing device. Then, the verification operation is performed again, that is, the current flowing through the in-memory computing unit is read again by the SA until the value stored in the in-memory computing unit reaches the expected resistance value.

[0041] Currently, programming and verification operations are typically performed device-by-device using serial or parallel methods. For example, in-memory computing devices can be programmed and verified one by one in a serpentine sequence until the conductance value of each device falls within the expected range. Because this method requires programming and verification operations on all in-memory computing devices individually, the weight mapping process is very slow, resulting in extremely low programming efficiency.

[0042] The computational operation refers to matrix multiplication and addition calculations performed using in-memory computing devices. For example, after writing the values ​​of the parameter elements in the parameter matrix into an in-memory computing array (e.g., mapping the weight matrix of a neural network to an in-memory computing array), multiple input voltages less than a threshold voltage can be input to multiple bit lines of the in-memory computing array. The output current can be obtained by summing the current generated by the interaction of multiple input voltages with multiple in-memory computing devices in a row or column.

[0043] For example, analog signals can be input to multiple column signal input terminals of the in-memory computing array after the conductance setting (programming) is completed. For example, the analog signals can be voltage signals, thereby controlling the in-memory computing array to perform matrix multiplication operations. According to Kirchhoff's laws, the output current of the in-memory computing array can be obtained according to the following formula (1):

[0044]

[0045] In the above formula (1), V n I represents the voltage input to the nth column signal input terminal out of multiple column signal input terminals. m This represents the current signal output from the m-th row signal output terminal out of multiple row signal output terminals. G mn This represents the overall conductance of the in-memory computing unit located in the m-th row and n-th column. According to Kirchhoff's laws, in-memory computing arrays can perform multiplication and accumulation calculations in parallel.

[0046] For example, to calculate the input vector V by multiplying it with matrix G to obtain the corresponding vector I, the value of each element G11 to Gmn in matrix G can be mapped to the conductance value of each in-memory computing device in the in-memory computing array. For example, ... Figure 1A The conductance values ​​of the in-memory computing devices in the m×n in-memory computing units of the in-memory computing array are programmed as each element G11~Gmn in the corresponding matrix G; the values ​​of each element V1, V2...Vn of the input vector V are mapped to multiple input voltages and applied to each bit line BL of the in-memory computing array accordingly. <1> BL <2> BL <n>Above; on each word line WL <1> WL <2> ...WL <m>After applying the turn-on voltage to each transistor in the corresponding row, according to Ohm's law and Kirchhoff's current law, the current in each source line SL... <1> SL <2> ……SL <m>The output current value is the value of the corresponding element I1, I2...Im in the vector I. For example, the source line SL <1> The output current value is determined by n bit lines BL <1> BL <2> BL <n>The input voltage values ​​V1, V2...Vn applied are multiplied by the source line SL respectively. <1> The source line SL is obtained by summing the conductance values ​​G11, G12...G1n of the n in-memory computing devices. <1> The output current value is the value of element I1 in vector I. Therefore, the result of matrix-vector multiplication can be obtained by measuring the output current values ​​of all rows.

[0047] It should be noted that, in the embodiments of this disclosure, the orientation of the "rows" and "columns" of the in-memory computing array is not limited to... Figure 1A It's not a fixed situation, but can be set as needed.

[0048] For example, Figure 2B This is a schematic diagram of a computing array performing computational operations. Figure 2B In-memory computing arrays and Figure 1A The word lines, bit lines, source lines, and in-memory computing arrays are connected to the in-memory computing units in different ways. For example, Figure 2B In the in-memory computing array shown, multiple bit lines BL1~BLn and multiple word lines WL1~WLn are parallel. The control terminal (e.g., the gate of a transistor) of the switching element in the in-memory computing unit in each row is connected to the corresponding word line of that row. One end of the switching element (e.g., the drain of a transistor) in the in-memory computing unit in each column is connected to the corresponding bit line of that column. The in-memory computing device in the in-memory computing unit in each column is connected to the corresponding source line of that column.

[0049] Although Figure 2B and Figure 1A The structures of in-memory computing arrays are different, but Figure 2B The "column" of the in-memory computing array shown can be equivalent to Figure 1A A "row" in a storage-based computing array. For example, [the row]... Figure 2B After swapping the row and column directions, matrix multiplication can be performed according to formula (1) above. For example, using... Figure 2B When the in-memory computing array shown performs matrix multiplication, the weight values ​​can be mapped to the conductance values ​​of each in-memory computing device in the array, and the input data can be mapped to voltage pulses at the n row signal input terminals. After simulation calculation, the output current can be directly read from the column signal output terminal of the in-memory computing array (e.g., from the source line SL1), and this output current is the result of the matrix multiplication. In the examples provided below, unless otherwise specified, ... Figure 2B The computing operation is illustrated using the in-memory computing array shown as an example.

[0050] Through the above computational operations, in-memory computing arrays can be used to accelerate matrix multiplication operations in data-intensive computing (such as computations in neural networks, including but not limited to forward and backward computations), thereby reducing the time and power consumption overhead of data movement.

[0051] However, due to the long source and bit lines and their high line resistance in in-memory computing arrays, the IR drop caused by the line resistance and parasitic resistance in the external circuitry of the in-memory computing array leads to a deviation between the actual voltage applied to the in-memory computing device and the input voltage during computation. When the scale of the in-memory computing array is large, the IR drop problem causes severe distortion of the output current, resulting in inaccurate simulation results. Furthermore, as the technology node continues to shrink, the line resistance in the in-memory computing array and the parasitic resistance in the external circuitry continuously increase, leading to an increasingly severe IR drop phenomenon that seriously affects the accuracy of the calculation.

[0052] For example, such as Figure 2A As shown, on each trace of the in-memory computing array, there is a line resistance R0 between adjacent in-memory computing units, and a parasitic resistance R1 exists in the peripheral circuit connected to each trace. For example, when the trace is long, the input voltage on the in-memory computing device far from the input voltage terminal will decrease by ΔV = I × R. Therefore, the input voltage received by the far-end in-memory computing device is less than the expected voltage, and the current generated by the interaction of this input voltage and the resistance of the in-memory computing device will also be smaller.

[0053] When verifying a single in-memory computing unit, such as Figure 2A As shown, since only one in-memory computing unit is activated in a column, the accumulated current Iread in the vertical direction is close to 0. Therefore, the voltage drop ΔVread on the source line can be ignored, and the current read by SA can accurately reflect the conductance value of the selected device. However, during forward calculations, as... Figure 2B As shown, since all the in-memory computing units on a column are turned on at the same time, the current on the source line is the cumulative current and Icalc of all the in-memory computing devices. This cumulative current and Icalc is large, and its effect with the line resistance and parasitic resistance leads to a large voltage difference. As a result, the current gathered on the source line cannot strictly reflect the matrix-vector multiplication result of the input and weights, which leads to a decrease in the accuracy of the forward calculation.

[0054] In other words, since the verification environment for each device is different from the environment for forward computation of the in-memory computing array, even if the verification result of a single in-memory computing device is ideal, additional errors (such as IR voltage drop) will be introduced when the array performs forward computation, resulting in a significant loss of computational accuracy.

[0055] At least one embodiment of this disclosure provides a weight update method, which includes: obtaining a target weight matrix; receiving a calculation result obtained by performing forward computation on an in-memory computing array mapped to the target weight matrix, and performing inverse solving on the calculation result to obtain an inverse weight matrix; and obtaining an updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix.

[0056] At least one embodiment of this disclosure also provides an in-memory computing system, which includes an in-memory computing array and a processor. The processor is configured to: acquire a target weight matrix; receive the computation result obtained by the in-memory computing array mapped to the target weight matrix after performing forward computation, and perform inverse solving on the computation result to obtain an inverse weight matrix; and obtain an updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix.

[0057] The weight update method and in-memory computing system of the above embodiments of this disclosure can obtain an inverse weight matrix that incorporates non-ideal factors from the forward computation by performing inverse processing on the calculation results. Based on the inverse weight matrix and the target weight matrix, an updated weight matrix is ​​obtained to guide the actual weight update, which can effectively improve the efficiency of weight update, improve calculation accuracy, and reduce time and power consumption. Furthermore, in at least one embodiment, the position of error weights and the degree of deviation of weights can be accurately located using a low-complexity, high-speed forward computation process, avoiding the costly read operation of each individual device across the entire array. This allows for fast and accurate weight updates, thereby improving the accuracy of forward computation in the in-memory computing array.

[0058] Figure 3 A flowchart illustrating a weight update method provided in at least one embodiment of this disclosure. Figure 3 As shown, the weight update method includes the following steps S100 to S300:

[0059] Step S100: Obtain the target weight matrix;

[0060] Step S200: Receive the calculation result obtained by the in-memory computing array mapped to the target weight matrix after performing forward calculation, and perform inverse solving on the calculation result to obtain the inverse weight matrix;

[0061] Step S300: Obtain the updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory array mapped to the target weight matrix.

[0062] In step S100, the target weight matrix obtained refers to the parameter matrix in the matrix multiplication operation task. For example, for the matrix multiplication operation described above, which multiplies vector V by matrix G to obtain the corresponding vector I, matrix G can be obtained as the target weight matrix.

[0063] Then, the value of each element G11 to Gmn in matrix G is mapped to each in-memory computing device in the in-memory computing array. For example, the value of each element G11 to Gmn in matrix G can be mapped one by one to the m×n in-memory computing units of the in-memory computing array through programming operations.

[0064] Then, forward computation is performed by the in-memory array mapped to the target weight matrix to obtain the calculation result of the forward computation, which includes errors caused by non-ideal factors such as IR voltage drop.

[0065] In step S200, the calculation result obtained after the in-memory computing array performs forward computation is received, and the calculation result is inversely processed to obtain an inverse weight matrix. This inverse weight matrix incorporates non-ideal factors from the forward computation. Therefore, in step S300, the target weight matrix can be adjusted based on this inverse weight matrix to obtain an updated weight matrix. Finally, the updated weight matrix is ​​remapped onto the in-memory computing array. When the in-memory computing array, mapped to the updated weight matrix, performs the matrix multiplication operation described above, the calculation result will eliminate errors caused by non-ideal factors such as IR voltage drop, thereby improving the calculation accuracy.

[0066] Therefore, the weight update method provided in the above embodiments of this disclosure takes into account different array operation environments such as forward computation and reading of single devices. It uses a low-complexity, high-speed forward computation process to inversely solve the weight matrix that incorporates non-ideal factors such as IR voltage drop. Based on this weight matrix, an updated weight matrix that truly reflects the hardware matrix multiplication can be calculated, thereby improving the accuracy of forward computation of the in-memory computing array mapped to the updated weight matrix.

[0067] For example, in at least one example of the embodiments of this disclosure, step S200, namely receiving the calculation result obtained after the in-memory computing array mapped to the target weight matrix performs forward calculation, and performing inverse processing on the calculation result to obtain the inverse weight matrix, may include: acquiring input data; loading the input data onto the in-memory computing array mapped to the target weight matrix to perform forward calculation through the in-memory computing array; receiving the output data obtained after the in-memory computing array performs forward calculation; and performing inverse processing based on the input data and the output data to obtain the inverse weight matrix.

[0068] For example, after the in-memory computing array is mapped to a target weight matrix, a set of input data can be loaded onto the array to perform forward computation. Here, the set of input data can include multiple input vectors. For instance, the input vectors can be mapped to input voltage values, and multiple input voltage values ​​can be applied to multiple in-memory computing units in a column to obtain the output current of the multiple in-memory computing units in the column. The total output current of the column is the result of multiplying and adding the conductance values ​​of the in-memory computing devices in that column with the input voltage signals. The output current value can be converted into a digital value by an analog-to-digital converter in the output circuit, thereby obtaining the output data of the in-memory computing array after performing forward computation.

[0069] The inverse solution process for the weights is similar to linear regression of a system of equations. The essence of solving a single column of the weight matrix is ​​solving a system of linear equations Ax = b. For example, if A is the input data of size B×M, x is a column of the weight matrix to be solved (in-memory array mapped to the target weight matrix in this embodiment of the disclosure), of size M×1, and b is the corresponding output of that column, of size B×1, then the necessary and sufficient condition for the existence and uniqueness of the vector x to be solved is rank(A)≥M. That is, to ensure the uniqueness of the solution to the matrix, the input data A must be a full-rank matrix.

[0070] For example, in at least one example of the embodiments of this disclosure, the weight update method further includes: receiving a first weight matrix, wherein the first weight matrix is ​​obtained by performing a read operation on the values ​​stored in each in-memory computing device of the in-memory computing array mapped to the target weight matrix.

[0071] For example, after mapping the target weight matrix to the in-memory computing array, the first weight matrix can be obtained by reading the values ​​stored in each in-memory computing device of the array mapped to the target weight matrix. For instance, the current flowing through the in-memory computing device can be read using the SA (Search Engine Array), and then the current value can be quantized into the magnitude of the value stored in the in-memory computing unit to obtain the first weight matrix. The obtained first weight matrix can be used as a "reference" for the next weight update.

[0072] Next, the processor (e.g., CPU) performs the corresponding data processing. For example, the CPU uses the aforementioned series of input and output data to inversely solve for the inverse solution weight matrix W_solve, which reflects the forward computation. Then, the CPU uses this inverse solution weight matrix W_solve and the previously obtained target weight matrix W_target to generate a new target weight matrix, i.e., update the weight matrix W_target_temp.

[0073] For example, in at least one example of the embodiments of this disclosure, step S300, namely obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix, may include: subtracting the inverse weight matrix from the target weight matrix to obtain the second weight matrix; and subtracting the first weight matrix from the second weight matrix to obtain the updated weight matrix.

[0074] For example, the second weight matrix W_diff can be obtained by subtracting the target weight matrix W_target from the inverse weight matrix W_solve using the algorithmic logic unit (ALU), i.e., W_diff = W_solve – W_target. Then, the second weight matrix W_diff is subtracted from the first weight matrix W_read received from the output circuit of the in-memory computing array to obtain the updated weight matrix W_target_temp, which truly reflects the weights of the hardware matrix multiplication, i.e., W_target_temp = W_read – W_diff. Updating the weights of the in-memory computing array based on this updated weight matrix W_target_temp can effectively improve the efficiency of weight updates, increase computational accuracy, and reduce time and power consumption.

[0075] For example, in at least one example of the embodiments of this disclosure, the weight update method further includes: determining the in-memory computing devices that need to be updated in the in-memory computing array according to the updated weight matrix; and performing a weight update operation on the in-memory computing devices that need to be updated.

[0076] For example, such as Figure 4 As shown, the weights that need to be updated are determined based on the updated weight matrix. Then, the corresponding in-memory computing devices whose conductance values ​​need to be adjusted are determined based on the weights that need to be updated. Then, the weights that need to be updated are mapped to their corresponding in-memory computing devices through programming operations. The in-memory computing array mapped to the updated weight matrix will be used for the target matrix multiplication calculation task, thereby improving the calculation accuracy.

[0077] In some embodiments of this disclosure, a threshold can be set based on the calculation precision to further reduce the number of weights that need to be updated. For example, weight update operations can be performed only on weights that deviate significantly.

[0078] For example, in at least one example of the embodiments of this disclosure, step S300, namely obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix, may include: subtracting the inverse weight matrix from the target weight matrix to obtain multiple deviation weight values; retaining deviation weight values ​​greater than or equal to a threshold to obtain a second weight matrix; and subtracting the first weight matrix from the second weight matrix to obtain the updated weight matrix.

[0079] For example, the algorithm's logic unit (ALU) can subtract the target weight matrix W_target from the inverse weight matrix W_solve to obtain multiple deviation weight values. These deviation weight values ​​are then compared with a preset threshold range. If the deviation value is within the preset threshold range (e.g., less than threshold T1), the weight at that point is not updated; for example, the weight at that point in the second weight matrix can be set to 0. If the deviation value is greater than or equal to the preset threshold T1, it indicates that the weight at that point is significantly affected by non-ideal factors and needs to be updated. That is, deviation weight values ​​greater than or equal to the threshold are retained to obtain the second weight matrix W_diff. Then, the second weight matrix W_diff is subtracted from the first weight matrix W_read received from the output circuit of the in-memory computing array to obtain the updated weight matrix W_target_temp, which truly reflects the weights of the hardware matrix multiplication.

[0080] For example, in at least one example of the embodiments of this disclosure, step S300, namely obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix, may include: subtracting the inverse weight matrix from the target weight matrix to obtain a second weight matrix; subtracting the first weight matrix from the second weight matrix to obtain multiple updated weight values; and retaining updated weight values ​​that are greater than or equal to a threshold to obtain the updated weight matrix.

[0081] For example, the algorithm can subtract the target weight matrix W_target from the inverse weight matrix W_solve using an algorithmic logic unit (ALU) to obtain a second weight matrix. Then, the first weight matrix is ​​subtracted from the second weight matrix to obtain multiple updated weight values. These updated weight values ​​are compared with a preset threshold range. If the updated weight value is within the preset threshold range (e.g., less than threshold T2), the weight at that point is no longer updated; for example, the weight at that point in the updated weight matrix can be set to 0. If the updated weight value is greater than or equal to the preset threshold T2, it indicates that the weight at that point is significantly affected by non-ideal factors and needs to be updated. In other words, updated weight values ​​greater than or equal to the threshold are retained to obtain the updated weight matrix W_target_temp.

[0082] By setting the comparison threshold as described above, the number of weights that need to be updated can be significantly reduced, thereby enabling precise location of the error weights and their deviation distance and direction. This avoids the costly read operation of reading each individual device across the entire array, allowing for fast and accurate weight updates while meeting the accuracy requirements of forward computation.

[0083] Figure 5 A flowchart illustrating an exemplary weight update method provided for at least one embodiment of this disclosure. Figure 5 As shown, the target weight matrix W_target can first be mapped onto each in-memory computing device in the in-memory computing array. Then, the first weight matrix W_read is obtained by performing a read operation on the in-memory computing array. Subsequently, input data X is loaded into the in-memory computing array. For example, the input data X includes multiple input vectors. The input data X is converted into an input voltage (analog signal) by a DAC and then applied to the in-memory computing array that has been mapped to the target weight matrix W_target. The in-memory computing array performs forward calculation to obtain the output current. The output current (analog signal) is converted into a digital signal by an ADC, thereby obtaining the output data Y after the in-memory computing array performs forward calculation.

[0084] Then, the processor performs inverse solution calculation based on the full-rank input data X and the ADC output to obtain the inverse solution weight matrix, that is, the inverse solution weight matrix W_solve = X. -1 ×Y. Based on the inverse weights and target weights, the location of the in-memory computing unit that has a significant impact on the accuracy loss of the forward computation and the degree of weight deviation can be located. Then, based on the target weight matrix W_target, the first weight matrix W_read obtained by performing a read operation on the in-memory computing array, and the inverse weight matrix W_solve, the target weight matrix for the new round of mapping is calculated, that is, the weight matrix W_target_temp is updated.

[0085] Finally, based on the updated weight matrix W_target_temp, the weight update operation is selectively performed on the in-memory computing devices that need to be updated in the in-memory computing array. For example, the conductance (or resistance) value of the in-memory computing device that needs to be updated is changed through programming operations (set operation or reset operation).

[0086] At least one embodiment of this disclosure also provides an in-memory computing system. Figure 6A This is a schematic block diagram of a memory computing system provided for at least one embodiment of this disclosure. Figure 6A As shown, the in-memory computing system includes an in-memory computing array and a processor.

[0087] This in-memory computing array can be as follows: Figure 1A The in-memory computing array shown can include multiple in-memory computing units and multiple word lines, bit lines, and source lines. For example, multiple in-memory computing units can form an M-row N-column array, where M and N are both positive integers.

[0088] It should be noted that, in the embodiments of this disclosure, the row and column arrangement directions of the multiple bit lines, word lines, and source lines in the in-memory computing array are not limited to... Figure 1A The configuration can be set as needed, rather than being the case in the previous version. Each in-memory computing unit includes at least one switching element and at least one in-memory computing device. The structure of the in-memory computing unit can be 1T1R (one switching element and one in-memory computing device), 2T2R (two switching elements and two in-memory computing devices), or other possible structures. The embodiments of this disclosure do not limit the type or structure of the in-memory computing unit. The switching element can be a transistor or other switching device with the same characteristics. For example, the transistor used here can be a thin-film transistor or a field-effect transistor (e.g., a MOS field-effect transistor). The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in structure. The embodiments of this disclosure do not limit the type of transistor used.

[0089] In embodiments of this disclosure, the in-memory computing device in the in-memory computing unit includes, but is not limited to, memristors (e.g., the memristor may be resistive random access memory (RRAM)), static random access memory (SRAM), dynamic random access memory (DRAM), phase change memory (PCM), flash memory, magnetic random access memory (MRAM), or other suitable non-volatile storage devices.

[0090] For example, the processor in this in-memory computing system is configured to: acquire the target weight matrix; receive the computation result obtained after the in-memory computing array mapped to the target weight matrix performs forward computation, and perform inverse processing on the computation result to obtain the inverse weight matrix; and obtain an updated weight matrix based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix. For example, the processor can be a central processing unit (CPU), tensor processor (TPU), neural network processor (NPU), data processor (DPU), AI accelerator, or graphics processing unit (GPU), etc., which have data processing capabilities and / or program execution capabilities; it can also be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0091] For example, at least one embodiment of the in-memory computing system provided in this disclosure further includes a read circuit. The read circuit is configured to perform a read operation on the values ​​stored in each in-memory computing device of the in-memory computing array mapped to a target weight matrix, to obtain a first weight matrix, wherein the processor is further configured to receive the first weight matrix. For example, the read circuit may include a sensitive amplifier (SA) for reading the resistance values ​​of the programmed in-memory computing devices.

[0092] For example, in embodiments of this disclosure, the in-memory computing array and processor in an in-memory computing system can reside on the same chip or on different chips. For example, as Figure 6A As shown, the in-memory computing array can interact with the on-chip processor via an interactive interface. For example, the processor can receive the computation result obtained by the in-memory computing array after performing forward computation (mapped to a target weight matrix) from the output circuit of the in-memory computing array via the interactive interface, and then perform inverse processing on the computation result to obtain the inverse weight matrix; for example, the processor can receive the first weight matrix from the read circuit via the interactive interface.

[0093] For example, in embodiments of this disclosure, the in-memory computing array and processor in an in-memory computing system may be located in the same electronic device or in different electronic devices.

[0094] For example, Figure 6B This is a schematic block diagram of another in-memory computing system provided for at least one embodiment of this disclosure. (See diagram below.) Figure 6B As shown, the in-memory computing array can reside in the hardware of the lower-level machine. The hardware is connected to the upper-level machine (taking a PC as an example) through an interactive interface, thereby receiving instructions or transmitting data from the upper-level machine. For example, the PC can receive the calculation result obtained by the in-memory computing array after performing forward calculation, which is mapped to the target weight matrix, from the output circuit of the in-memory computing array through the interactive interface. The calculation result can then be inversely processed to obtain the inverse weight matrix. For example, the PC can receive the first weight matrix from the read circuit through the interactive interface.

[0095] For example, at least one embodiment of the in-memory computing system provided in this disclosure further includes a programming circuit. The programming circuit is configured to map a target weight matrix onto an in-memory computing array, and after obtaining an updated weight matrix, to map the updated weight matrix onto the in-memory computing array to perform weight updates.

[0096] For example, in at least one embodiment of the in-memory computing system provided in this disclosure, the programming circuit includes an input register, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and an output register. For instance, the input register is configured to receive input data from the processor; the DAC is configured to convert the input data from a digital signal to an analog voltage signal for input to multiple column signal input terminals of the in-memory computing array during forward computation; the ADC is configured to convert the output data from an analog current signal to a digital signal; and the output register is configured to output a digital signal to the processor.

[0097] For example, the in-memory computing system may also include word line driver circuits, bit line driver circuits, and source line driver circuits (not shown in the figure), through which various operations on the in-memory computing array are realized.

[0098] For example, a word line driver circuit includes multiplexers (Muxes) for switching the control voltage applied to the word lines; a bit line driver circuit includes multiplexers for switching the bit line input voltage; and a source line driver circuit also includes multiplexers (Muxes) for switching the source line input voltage. For example, a source line driver circuit may include N ADCs for converting analog signals to digital signals.

[0099] For example, in-memory computing arrays include programming mode and computing mode.

[0100] For example, when programming an in-memory computing array, the array is in programming mode, and the values ​​of the weight elements in the weight matrix can be written into the array. For instance, the word line input voltage, source line input voltage, and bit line input voltage can be switched to their respective voltage ranges using control signals from the multiplexers in the word line driver circuit, source line driver circuit, and bit line driver circuit. For example, when setting an in-memory computing device, the word line input voltage is set to 2V, the source line input voltage is set to 0V, and the bit line input voltage is set to 2V; similarly, when resetting an in-memory computing device, the word line input voltage is set to 5V, the source line input voltage is set to 2V, and the bit line input voltage is set to 0V.

[0101] For example, when performing computation operations on a memory-computing array, the memory-computing array is in computation mode (e.g., forward computation). At this time, the memory-computing devices in the memory-computing array are in a conductive state that can be used for computation. The bit line input voltage input at the column signal input terminal does not change the conductance value of the memory-computing device. For example, the computation can be completed by performing multiplication and addition operations through the memory-computing array.

[0102] For example, when the in-memory computing array is in computing mode, the word line input voltage can be switched to the corresponding voltage range by the control signal of the multiplexer in the word line driver circuit. For example, when an enable signal is applied, the word line input voltage of the corresponding row is set to 5V, and when no enable signal is applied, the word line input voltage of the corresponding row is set to 0V (e.g., when the GND signal is turned on). The source line input voltage can be switched to the corresponding voltage range by the control signal of the multiplexer in the source line driver circuit. For example, the source line input voltage can be set to 0V, so that the current signals of multiple row signal output terminals can flow into the analog-to-digital conversion circuit. The bit line input voltage can be switched to the corresponding voltage range by the control signal of the multiplexer in the bit line driver circuit. For example, the bit line input voltage can be set to 0.1V-0.3V, so that matrix multiplication can be performed using the characteristics of the in-memory computing array.

[0103] For example, Figure 6A and Figure 6B The in-memory computing system shown can be used to implement the weight update method in the above embodiments of this disclosure. For example, firstly, the target weight matrix W_target can be mapped one by one to each in-memory computing device in the in-memory computing array through a programming circuit, and the first weight matrix W_read can be obtained through a read circuit. The first weight matrix W_read can be sent to a data processing module (e.g., a processor or PC) outside the in-memory computing array through an interactive interface. Subsequently, input data is loaded through an input register, and the input data is converted into an input voltage (analog signal) by a DAC. The input voltage is applied to the in-memory computing array that has been mapped to the target weight matrix W_target. The in-memory computing array performs forward calculation to obtain the output current. The output current (analog signal) is converted into a digital signal by an ADC, and the digital signal is sent to the processor through the interactive interface via an output register. That is, the processor receives the calculation result of the forward calculation.

[0104] The processor calculates the inverse solution weight matrix based on the full-rank input data X and the ADC output, that is, the inverse solution weight matrix W_solve = X. -1 ×Y. Based on the inverse weights and target weights, the location of the in-memory computing unit that has a significant impact on the accuracy loss of the forward computation and the degree of weight deviation can be located. Then, it is superimposed on the previous read result (the first weight matrix W_read) as the target weight matrix for the new round of mapping, that is, the weight matrix W_target_temp is updated.

[0105] Subsequently, the read circuit and the programming circuit selectively map the weights of the in-memory computing devices that need to be updated in the in-memory computing array according to the updated weight matrix W_target_temp.

[0106] Figure 7 This is a schematic diagram of an exemplary analog-to-digital converter (ADC) circuit provided in at least one embodiment of the present disclosure. For example, in the in-memory computing system provided in at least one embodiment of the present disclosure, the ADC circuit includes a first channel and a second channel. The first channel is configured to sample the current flowing through each column of in-memory computing devices in the in-memory computing array; the second channel is configured to quantize the sampled current, wherein the sampling operation of the first channel on the current flowing through the current column of in-memory computing devices and the quantization operation of the second channel on the current obtained from sampling the previous column of in-memory computing devices are performed in parallel.

[0107] Figure 7 The illustrated analog-to-digital converter (ADC) circuit features a compact, high-speed dual-channel ADC structure, where the first and second channels can have identical structures. For example, the first channel can sample the current flowing through a column of in-memory computing devices in the in-memory array, while the second channel can quantize the current sampled from the first column. In other words, while one channel of the ADC is sampling the current of a vertical line in the in-memory array, the other channel is performing quantization. Thus, the sampling and quantization processes of the ADC can be performed simultaneously, with the additional overhead consisting only of a class AB output stage and several switches and capacitors. This compact dual-channel ADC structure further enhances the speed of forward computation, thereby accelerating the overall weight update speed and increasing the computing power of the entire in-memory computing system.

[0108] At least one embodiment of this disclosure also provides a schematic diagram of a non-transitory computer-readable storage medium. One or more computer-executable instructions can be stored non-transitory on the storage medium. For example, when the computer-executable instructions are executed by a processor, one or more steps in the weight update method described above can be performed. The technical effects of this non-transitory storage medium are the same as those of the weight update method described above, and will not be repeated here.

[0109] For example, the aforementioned non-transiently readable storage medium is implemented as a memory, such as volatile memory and / or non-volatile memory. In the above embodiments, the memory can be volatile memory, such as random access memory (RAM) and / or cache. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. The memory can also store various applications (code, instructions) and data, as well as various data used and / or generated by the applications.

[0110] At least one embodiment of this disclosure also provides an electronic device, including a memory and a processor. The memory stores computer-executable instructions non-transitoryly, and the processor is configured to execute the computer-executable instructions. The computer-executable instructions, when executed by the processor, implement the weight update method as described in any of the above embodiments. The technical effects of this electronic device are the same as those of the weight update method described above, and will not be repeated here.

[0111] Figure 8 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0112] For example, such as Figure 8 As shown, in some examples, electronic device 1000 includes a processing device (e.g., central processing unit, graphics processing unit, etc.) 1001, which may include the processor in the in-memory computing system of any of the above embodiments, capable of performing various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. The RAM 1003 also stores various programs and data required for the operation of the computer system. The processor 1001, ROM 1002, and RAM 1003 are connected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0113] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable storage media 1011, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 8 An electronic device 1000 including various devices is shown, but it should be understood that it is not required to implement or include all of the devices shown, and more or fewer devices may be implemented or included alternatively.

[0114] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0115] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigator, or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0116] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0117] The following points should be noted regarding this disclosure:

[0118] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0119] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0120] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0121] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.< / n> < / m> < / m> < / n> < / m> < / n> < / m>

Claims

1. A weight update method, comprising: Obtain the target weight matrix; The calculation result obtained by the in-memory computing array mapped to the target weight matrix after performing forward calculation is received, and the calculation result is inversely processed to obtain the inverse weight matrix; An updated weight matrix is ​​obtained based on the target weight matrix and the inverse weight matrix, wherein the updated weight matrix is ​​used to update the weights of the in-memory computing array mapped to the target weight matrix. Receive a first weight matrix, wherein the first weight matrix is ​​obtained by performing a read operation on the values ​​stored in each in-memory computing device of the in-memory computing array mapped to the target weight matrix; The step of obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix includes: Subtracting the target weight matrix from the inverse weight matrix yields the second weight matrix; subtracting the second weight matrix from the first weight matrix yields the updated weight matrix. or, Subtracting the inverse weight matrix from the target weight matrix yields multiple deviation weight values; The deviation weight values ​​that are greater than or equal to the threshold are retained to obtain the second weight matrix; The updated weight matrix is ​​obtained by subtracting the first weight matrix from the second weight matrix.

2. The weight update method according to claim 1 further includes: The in-memory computing devices that need to be updated in the in-memory computing array are determined based on the updated weight matrix. Perform a weight update operation on the in-memory computing device that needs to be updated.

3. The weight update method according to claim 1, wherein, The process of receiving the computation result obtained by the in-memory computing array mapped to the target weight matrix after performing forward computation, and performing inverse processing on the computation result to obtain the inverse weight matrix, includes: Get the input data; The input data is loaded onto the in-memory array that is mapped to the target weight matrix, so that the forward computation is performed through the in-memory array; Receive the output data obtained after the in-memory computing array performs the forward computation; The inverse solution weight matrix is ​​obtained by performing inverse solution processing based on the input data and the output data.

4. The weight update method according to claim 3, wherein, The input data is a full-rank matrix.

5. A memory computing system, comprising a memory computing array and a processor, wherein the processor is configured as follows: Obtain the target weight matrix; The calculation result obtained by the in-memory computing array mapped to the target weight matrix after performing forward calculation is received, and the calculation result is inversely processed to obtain the inverse weight matrix; An updated weight matrix is ​​obtained based on the target weight matrix and the inverse weight matrix, wherein, The updated weight matrix is ​​used to update the weights of the in-memory computing array that has been mapped to the target weight matrix. The in-memory computing system also includes: The read circuit is configured to perform a read operation on the values ​​stored in each in-memory computing device of the in-memory computing array mapped to the target weight matrix, to obtain the first weight matrix. The processor is further configured to receive the first weight matrix. Wherein, when the processor executes the process of obtaining the updated weight matrix based on the target weight matrix and the inverse weight matrix, it is configured to: Subtracting the target weight matrix from the inverse weight matrix yields the second weight matrix; subtracting the second weight matrix from the first weight matrix yields the updated weight matrix. or, Subtracting the inverse weight matrix from the target weight matrix yields multiple deviation weight values; The deviation weight values ​​that are greater than or equal to the threshold are retained to obtain the second weight matrix; The updated weight matrix is ​​obtained by subtracting the first weight matrix from the second weight matrix.

6. The in-memory computing system according to claim 5 further includes: The programming circuit is configured to map the target weight matrix onto the in-memory computing array, and after obtaining the updated weight matrix, map the updated weight matrix onto the in-memory computing array to perform the weight update.

7. The in-memory computing system according to claim 6, wherein, The programming circuit includes: An input register is configured to receive input data from the processor; A digital-to-analog converter circuit is configured to convert the input data from a digital signal into an analog voltage signal; An analog-to-digital converter circuit is configured to convert output data from an analog current signal into a digital signal. An output register is configured to output the digital signal to the processor.

8. The in-memory computing system according to claim 7, wherein, The analog-to-digital conversion circuit includes: The first channel is configured to sample the current flowing through each column of in-memory computing devices in the in-memory computing array; The second channel is configured to perform quantization on the sampled current. The sampling operation of the current flowing through the current column of the in-memory computing device by the first channel and the quantization operation of the current obtained by the sampling of the previous column of the in-memory computing device by the second channel are performed in parallel.

9. An electronic device, comprising: Memory stores computer-executable instructions non-transiently; The processor is configured to run computer-executable instructions. The computer-executable instructions are executed by the processor to implement the weight update method according to any one of claims 1-4.

10. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the weight update method according to any one of claims 1-4.

Images