Driving method of display panel, display panel, display device

Abstract

Embodiments of the present disclosure provide a display panel driving method, a display panel and a display device, and relate to the technical field of display, to improve the display device in the light test, to appear horizontal lines / screening and other undesirable phenomena, to improve product yield. The display panel driving method comprises: in the first sub-stage, providing a first voltage signal to one control signal line, and providing a second voltage signal to other control signal lines. A multiplexing circuit transmits a data signal of a data bus to a data line in response to the first voltage signal of one control signal line. In the second sub-stage, a third voltage signal is provided to the target control signal line, and the second voltage signal is provided to the other control signal lines. The target control signal line is the control signal line receiving the first voltage signal in the first sub-stage. The voltage value of the third voltage signal is between the voltage value of the first voltage signal and the voltage value of the second voltage signal. The display panel driving method is used for the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method for a display panel, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Display (OLED), Quantum Dot Light Emitting Display (QLED), and Mini / Micro Light Emitting Display (MLED) have been widely integrated into people's daily lives. For example, smartphones, wearable watches, televisions, laptops, and in-vehicle displays have gradually become ubiquitous in people's lives.

[0003] In related technologies, the source driver circuit is connected to the data line through a multiplexer (MUX) to reduce the number of data lines, the fan-out area, and the area of ​​the source driver circuit, thereby reducing the bezel of the display device. However, during lamp-on testing, defects such as horizontal stripes / split screens may occur, leading to a decrease in product yield. Summary of the Invention

[0004] The purpose of this disclosure is to provide a driving method for a display panel, a display panel, and a display device to improve the display device's performance during lamp testing, thereby increasing product yield.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a driving method for a display panel is provided. The display panel includes a plurality of sub-pixels, a plurality of data lines connected to the plurality of sub-pixels, a plurality of multiplexing circuits, a plurality of data buses, and a plurality of control signal lines. At least one of the plurality of multiplexing circuits is configured to, under the control of the plurality of control signal lines, time-division multiplex a data signal transmitted by one of the plurality of data buses to at least two of the plurality of data lines.

[0007] The process of transmitting the data signal from one data bus to at least two data lines through the at least one multiplexing circuit is a data writing stage. The data writing stage includes multiple sub-writing stages spaced apart. Each sub-writing stage includes a first sub-segment and at least one second sub-segment, which are consecutively arranged. The driving method includes:

[0008] In the first sub-segment, a first voltage signal is provided to one of the control signal lines, and a second voltage signal is provided to the other control signal lines. One of the multiplexing circuits, in response to the first voltage signal on one of the control signal lines, transmits data signals from the data bus to one of the data lines.

[0009] In the second sub-segment, a third voltage signal is provided to the target control signal line, and a second voltage signal is provided to the other control signal lines. The target control signal line is the control signal line that receives the first voltage signal in the first sub-segment. The voltage value of the third voltage signal is between the voltage values ​​of the first voltage signal and the second voltage signal.

[0010] The display panel driving method provided in this disclosure, during the voltage signal boosting process (converting a first voltage signal to a second voltage signal) received by the control signal line, first converts the first voltage signal to a third voltage signal, and then converts the third voltage signal to a second voltage signal. This transforms the large jump between the first and second voltage signals into two smaller jumps, thereby reducing the interference of the voltage jump of the control signal line on the data signal, improving the accuracy of data signal transmission, improving the defective phenomenon of horizontal stripes or screen splitting that occurs during lamp lighting tests of the display device, and improving product yield.

[0011] Furthermore, during the voltage reduction process of the voltage signal received by the control signal line (the second voltage signal is converted into the first voltage signal), the second voltage signal is first converted into the third voltage signal, and then the third voltage signal is converted into the first voltage signal. This transforms the large jump between the second and first voltage signals into two smaller jumps, thereby reducing the interference of the voltage jump of the control signal line on the data signal, improving the accuracy of data signal transmission, improving the defective phenomenon of horizontal stripes or screen splitting that occurs when the display device is tested for lamp illumination, and improving the product yield.

[0012] In some embodiments, the absolute value of the difference between the voltage of the third voltage signal and the voltage of the second voltage signal is a first voltage difference, the absolute value of the difference between the voltage of the first voltage signal and the voltage of the second voltage signal is a second voltage difference, and the ratio of the first voltage difference to the second voltage difference is 1 / 4 to 3 / 4.

[0013] In some embodiments, the duration of the second segment is less than the duration of the first segment.

[0014] In some embodiments, the ratio of the duration of the second segment to the duration of the first segment is 1 / 8 to 1 / 4.

[0015] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels with different emission colors. The plurality of data lines are divided into multiple data line groups, and one multiplexing circuit is connected to at least one of the multiple data line groups. Furthermore, each data line group includes a first data line, a second data line, and a third data line. The plurality of sub-pixels are arranged in multiple rows and columns, with the first data line connected to a column of red sub-pixels, the second data line connected to a column of green sub-pixels, and the third data line connected to a column of blue sub-pixels.

[0016] The plurality of sub-write stages includes at least one first sub-write stage, at least one second sub-write stage, and at least one third sub-write stage. In the first sub-write stage, data signals from the data bus are transmitted to a first data line. In the second sub-write stage, data signals from the data bus are transmitted to a second data line. In the third sub-write stage, data signals from the data bus are transmitted to a third data line. The at least one second sub-write stage follows the at least one first sub-write stage and the at least one third sub-write stage.

[0017] In some embodiments, the at least one third sub-write stage is located before or after the at least one first sub-write stage. The time interval between adjacent first and third sub-write stages is a first time difference, and the time interval between the second sub-write stage and an adjacent one of the first and third sub-write stages is a second time difference. The second time difference is greater than or equal to the first time difference.

[0018] In some embodiments, one of the multiplexing circuits is connected to at least two of the plurality of data line groups, and the plurality of sub-write stages include a plurality of first sub-write stages, a plurality of second sub-write stages, and a plurality of third sub-write stages, wherein the plurality of third sub-write stages are located before or after the plurality of first sub-write stages.

[0019] The time interval between the plurality of first sub-write stages is a third time difference, the time interval between the plurality of second sub-write stages is a fourth time difference, and the time interval between the plurality of third sub-write stages is a fifth time difference. The time interval between any two adjacent first, second, and third sub-write stages is a sixth time difference. The third, fourth, and fifth time differences are all less than or equal to the sixth time difference.

[0020] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels with different emission colors. The plurality of data lines are divided into a plurality of data line groups, and one of the multiplexing circuits is connected to at least one of the plurality of data line groups. Furthermore, each data line group includes a first data line, a second data line, and a third data line; the first data line is connected to a column of red sub-pixels, the second data line is connected to a column of green sub-pixels, and the third data line is connected to a column of blue sub-pixels.

[0021] The plurality of sub-write stages includes at least one first sub-write stage, at least one second sub-write stage, and at least one third sub-write stage. In the first sub-write stage, the data signal of the data bus is transmitted to a first data line. In the second sub-write stage, the data signal of the data bus is transmitted to a second data line. In the third sub-write stage, the data signal of the data bus is transmitted to a third data line. The duration of the first segment of the second sub-write stage is greater than or equal to the duration of the first segment of the first sub-write stage. The duration of the first segment of the first sub-write stage is greater than or equal to the duration of the first segment of the third sub-write stage.

[0022] On the other hand, a display panel is provided. The display panel is used to perform the driving method of the display panel as described in any of the above embodiments. The display panel includes a display area and a peripheral area located on at least one side of the display area, and further includes a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexed circuits, a plurality of data buses, and a plurality of control signal lines.

[0023] The plurality of sub-pixels are located in the display area and arranged in multiple rows and columns. Each row includes at least two sub-pixels arranged along a first direction, and each column includes at least two sub-pixels arranged along a second direction. The plurality of data lines are located in the display area and connected to the plurality of sub-pixels. The plurality of data lines extend along the second direction and are spaced apart along the first direction. One data line is connected to one column of sub-pixels. The plurality of multiplexing circuits are located in the peripheral area and are spaced apart along the first direction. Each multiplexing circuit is connected to at least two of the plurality of data lines. The plurality of data buses are located in the peripheral area and are located on the side of the plurality of multiplexing circuits away from the display area. One data bus is connected to one multiplexing circuit. The plurality of control signal lines are located in the peripheral area and extend along the first direction. Each multiplexing circuit is connected to the plurality of control signals. The multiplexing circuit is configured to, under the control of a first voltage signal of the plurality of control signal lines, transmit the data signal of one data bus to at least two data lines in a time-division multiplexing manner.

[0024] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels with different emission colors. The plurality of data lines are divided into a plurality of data line groups, and one of the multiplexing circuits is connected to at least one of the plurality of data line groups.

[0025] Furthermore, the data line group includes a first data line, a second data line, and a third data line. The first data line is connected to a column of red sub-pixels, the second data line is connected to a column of green sub-pixels, and the third data line is connected to a column of blue sub-pixels.

[0026] In another aspect, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip is connected to a data bus of the display panel and the control signal lines. The driver chip is configured to provide a first voltage signal, a second voltage signal, and a third voltage signal to the control signal lines. Furthermore, during a data writing phase, the first voltage signal and the third voltage signal are provided to one of the control signal lines, and the second voltage signal is provided to the other control signal lines, wherein the voltage value of the third voltage signal is located between the voltage values ​​of the first voltage signal and the second voltage signal.

[0027] The above-described display panel and display device have the same beneficial effects as the driving method of the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0030] Figure 2 This is a structural diagram of another display device according to some embodiments;

[0031] Figure 3 for Figure 1 A cross-sectional view of the display device shown along section line AA';

[0032] Figure 4 This is a top view of a display panel according to some embodiments;

[0033] Figure 5 This is a timing diagram of a data writing phase according to some embodiments;

[0034] Figure 6 This is a circuit diagram showing the connection between the data line and the driver chip of a display panel according to some embodiments;

[0035] Figure 7 This is a circuit diagram showing the connection between the data line and the driver chip of another display panel according to some embodiments;

[0036] Figure 8 This is a timing diagram of another data writing phase according to some embodiments;

[0037] Figure 9 This is a timing diagram of yet another data writing phase according to some embodiments;

[0038] Figure 10 This is a timing diagram of another data writing phase according to some embodiments. Detailed Implementation

[0039] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0040] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0041] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0042] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0043] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0044] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0045] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0046] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0047] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0048] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0049] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors) or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example.

[0052] In embodiments of this disclosure, "low level" refers to a voltage that enables the included P-type transistor to conduct but does not enable the included N-type transistor to conduct (i.e., the N-type transistor is turned off); correspondingly, "high level" refers to a voltage that enables the included N-type transistor to conduct but does not enable the included P-type transistor to conduct (i.e., the P-type transistor is turned off).

[0053] In this document, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second electrodes of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0054] In the circuits provided in the embodiments of this disclosure, all transistors are P-type transistors, as an example.

[0055] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0056] For example, see Figure 1 The display device 1000 can be any product or component with display function, such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, virtual reality (VR) device, etc.

[0057] For example, such as Figure 1 As shown, the display device 1000 can be a portable display product; for example, the display device 1000 can be... Figure 1 The mobile phone shown. For example, see [link to relevant documentation]. Figure 2 The display device 1000 can be a wearable device; for example, the display device 1000 can be... Figure 2 The watch shown.

[0058] It should be noted that the shape of the display surface of the display device 1000 is not unique depending on the application scenario. The shape of the display surface of the display device 1000 can be any of the following: circular, elliptical, or polygonal. This embodiment of the present disclosure does not impose any specific limitation.

[0059] The aforementioned display device 1000 may include any one of a liquid crystal display (LCD), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), and a mini / micro light-emitting diode (MLED), and the embodiments disclosed herein are not specifically limited thereto.

[0060] The following uses OLED as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other display device 1000 can be considered as long as the same technical concept is applied.

[0061] In some embodiments, see Figure 3 The display device 1000 includes a display panel 100 configured to display an image. The display panel 100 has a display side 100A and a back side 100B disposed opposite to each other.

[0062] It should be noted that display side 100A refers to the side of display panel 100 where the image is displayed. Figure 3 The upper side of the display panel 100), and the back side 100B refers to the side opposite to the display side 100A. Figure 3 (Lower side of the central display panel 100).

[0063] For example, see Figure 3 and Figure 4 The display device 1000 also includes a housing 200, a cover plate 300, a circuit board 400, a driver chip 20, and other electronic components. The display panel 100, the circuit board 400, and the driver chip 20 can be disposed within the housing 200. Furthermore, the driver chip 20 can be disposed on the circuit board 400 or on the display panel 100; this embodiment does not impose specific limitations herein. Figure 4 The following is an example of a driver chip 20 being installed on a display panel 100.

[0064] For example, such as Figure 3 and Figure 4As shown, the longitudinal section of the housing 200 can be, for example, U-shaped. The display panel 100, circuit board 400, and driver chip 20 are disposed inside the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on the side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the required signals to the display panel 100, thereby driving the display panel 100 to realize image display.

[0065] It should be noted that the circuit board 400 may also include a timing controller (TCON), a power management chip, and an adjustable resistor voltage divider circuit (generating Vcom), etc.

[0066] In some embodiments, see Figure 4 The display panel 100 has a display area A and a peripheral area B disposed on at least one side of the display area A. Figure 4 The diagram illustrates the arrangement of the surrounding area B around the display area A.

[0067] The display area A is the area for displaying images, and it is configured to have multiple sub-pixels P, which can be understood as the smallest light-emitting unit in the display panel 100. The peripheral area B is the area where images are not displayed, and it is configured to house driving circuits, such as gate driving circuit 10 and driving chip 20.

[0068] In some embodiments, such as Figure 4 As shown, display area A is provided with multiple sub-pixels P, which are arranged in multiple rows and columns. Each row includes at least two sub-pixels P arranged along the first direction X, and each column includes at least two sub-pixels P arranged along the second direction Y.

[0069] It should be noted that the first direction X is the row direction of the arrangement of multiple sub-pixels P, and the second direction Y is the column direction of the arrangement of multiple sub-pixels P. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular.

[0070] In addition, the multiple sub-pixels P may include, for example, a red sub-pixel R that emits red light, a green sub-pixel G that emits green light, and a blue sub-pixel B that emits blue light, so that the display panel 100 can emit light of multiple colors, thereby achieving full-color display.

[0071] In some embodiments, such as Figure 4As shown, the display panel 100 may further include multiple grid lines 30 and multiple data lines 40. The grid lines 30 are disposed in the display area A and extend along a first direction X, and the multiple grid lines 30 are arranged at intervals along a second direction Y. The data lines 40 are disposed in the display area A and extend along the second direction Y, and the multiple data lines 40 are arranged at intervals along the first direction X.

[0072] Understandably, a sub-pixel P includes pixel circuitry 50, and a gate line 30 can be connected to the gate driving circuitry 10 and the pixel circuitry 50 of a row of sub-pixels P. A data line 40 can be connected to the driving chip 20 and the pixel circuitry 50 of a column of sub-pixels P.

[0073] It should be understood that, see reference Figure 4 and Figure 5 One frame cycle includes a data writing phase P1. In the data writing phase P1, the driver chip 20 writes data signals to all data lines 40, and the gate driver circuit 10 provides scan signals to the gate lines 30 to drive each pixel circuit 50 in a row to write the corresponding data signals. It should be noted that one frame cycle refers to the process by which the display panel 100 displays a still image.

[0074] In some embodiments, see Figure 4 and Figure 6 The display panel 100 may further include multiple multiplexed circuits 60, multiple data buses 70, and multiple control signal lines 80. The multiple multiplexed circuits 60 are located in the peripheral area B and are arranged at intervals along the first direction X. The multiple data buses 70 are located in the peripheral area B and are located on the side of the multiple multiplexed circuits 60 away from the display area A. The multiple control signal lines 80 are located in the peripheral area B and extend along the first direction X.

[0075] The multiplexing circuit 60 is configured, under the control of multiple control signal lines 80, to time-division multiplex the data signal transmitted by one of the multiple data buses 70 to at least two data lines 40 connected to the multiplexing circuit 60. This reduces the number of circuit traces (data buses 70) connected to the driver chip 20, thereby reducing the fan-out area of ​​the circuit traces (data buses 70) and decreasing the area occupied by the lower bezel of the display panel 100. The process of a data bus 70 transmitting a data signal to the data line 40 connected to it through at least one multiplexing circuit 60 is the aforementioned data writing stage P1.

[0076] For example, such as Figure 6 As shown, each multiplexed circuit 60 is connected to at least two data lines 40 and to the driver chip 20 via a data bus 70 and multiple control signal lines 80. For example, as Figure 6 As shown, each multiplexed circuit 60 is connected to three data lines 40. For example, as... Figure 7As shown, each multiplexing circuit 60 is connected to nine data lines 40. Of course, each multiplexing circuit 60 can also be connected to two, four, six, or other numbers of data lines 40, and this embodiment of the present disclosure does not impose a specific limitation.

[0077] In this case, at least two data lines 40 connected to the multiplexing circuit 60 can transmit corresponding data signals through a data bus 70. Compared to all data lines 40 being directly connected to the driver chip 20, the data lines 40 being connected to the driver chip 20 through the multiplexing circuit 60 and the data bus 70 can reduce the number of circuit traces connected to the driver chip 20 from the number of data lines 40 to the number of data buses 70, reduce the area fanned out by the data lines 40, and reduce the area occupied by the lower bezel of the display panel 100.

[0078] The following describes some embodiments of the present disclosure using the example of each multiplexed circuit 60 being connected to nine data lines 40. However, the implementation of the present disclosure is not limited to this, and it is also possible to consider connecting the multiplexed circuit 60 to other numbers of data lines 40, as long as the same technical concept is applied.

[0079] In some embodiments, see Figure 6 and Figure 7 The multiplexing circuit 60 includes multiple transistors T. The control electrode of the multiple transistors T in the multiplexing circuit 60 is connected to multiple control signal lines 80 in a one-to-one correspondence. The first electrode of the multiple transistors T in the multiplexing circuit 60 is connected to the same data bus 70. The second electrode of the multiple transistors T in the multiplexing circuit 60 is connected to a data line 40 respectively.

[0080] At this time, refer to Figure 5 The data writing phase P1 includes multiple sub-writing phases P10 spaced apart and a charging phase P20, with the charging phase P20 located after the multiple sub-writing phases P10.

[0081] In the multiple sub-writing stages P10, spaced apart, the driver chip 20 sequentially transmits first voltage signals to multiple control signal lines 80 and sequentially provides data signals to the data bus 70, causing multiple transistors T of the multiplexing circuit 60 to sequentially turn on and transmit the data signals sequentially provided to the data bus 70 to different data lines 40, thereby writing data signals to all data lines 40. In the charging stage P20, the gate driver circuit 10 provides scan signals to the gate line 30 to drive each pixel circuit 50 in a row to write the corresponding data signal.

[0082] It should be noted that the first voltage signal is configured to have a voltage that enables transistor T to conduct. For example, transistor T is a P-type transistor, and the first voltage signal is a low-level signal, such as -7V.

[0083] However, the data signal can be affected by the jumps in the control signal received by the multiplexing circuit, causing defects such as horizontal stripes or screen splitting to appear on the display device during the lamp test, resulting in a decrease in product yield.

[0084] Based on this, see Figure 5 , Figure 7 and Figure 8 Some embodiments of this disclosure provide a driving method for a display panel 100, wherein a sub-write stage P10 includes a first sub-segment P101 and at least one second sub-segment P102. Furthermore, the first sub-segment P101 and all the second sub-segments P102 are consecutively configured. Consecutive configuration means that the start time of one of the first sub-segments P101 and the end time of the other are the same.

[0085] For example, such as Figure 8 As shown, the write phase P10 includes a first sub-segment P101 and a second sub-segment P102, with the second sub-segment P102 located before or after the first sub-segment P101. That is, the deadline of the second sub-segment P102 is the same as the start time of the first sub-segment P101, or the start time of the second sub-segment P102 is the same as the deadline of the first sub-segment P101. Figure 8 The example shown is that the second sub-segment P102 is located before the first sub-segment P101.

[0086] For example, such as Figure 5 As shown, the sub-write stage P10 includes a first sub-segment P101 and two second sub-segments P102. One of the two second sub-segments P102 is located before the first sub-segment P101, and the other is located after the first sub-segment P101. That is, the deadline of one of the two second sub-segments P102 is the same as the start time of the first sub-segment P101, and the start time of the other is the same as the deadline of the first sub-segment P101.

[0087] The following example illustrates some embodiments of this disclosure, using the sub-write stage P10 as an example, which includes a first sub-segment P101 and two second sub-segments P102. However, the implementation of this disclosure is not limited to this, and it is also possible to include a second sub-segment P102, as long as the same technical concept is applied.

[0088] In the first sub-segment P101, the driver chip 20 provides a first voltage signal to one control signal line 80 and a second voltage signal to the other control signal lines 80. A multiplexing circuit 60, in response to the first voltage signal of one control signal line 80 and the second voltage signals of the other control signal lines 80, turns on the transistor T that receives the first voltage signal and turns off the transistor T that receives the second voltage signal, thereby transmitting the data signal of the data bus 70 to the corresponding data line 40.

[0089] It should be noted that the second voltage signal is configured to have a voltage that turns off transistor T. For example, transistor T is a P-type transistor, and the second voltage signal is a high-level signal, such as +7V.

[0090] In the second sub-segment P102, the driver chip 20 provides a third voltage signal to the target control signal line and a second voltage signal to other control signal lines 80. The target control signal line is the control signal line 80 that receives the first voltage signal in the first sub-segment P101.

[0091] The voltage value of the third voltage signal lies between the voltage values ​​of the first and second voltage signals. Based on this, the difference between the voltage of the third voltage signal and the voltage of the first voltage signal is the third voltage difference; the absolute value of the difference between the voltage of the third voltage signal and the voltage of the second voltage signal is the first voltage difference; the absolute value of the difference between the voltage of the first voltage signal and the voltage of the second voltage signal is the second voltage difference; and the sum of the first and third voltage differences equals the second voltage difference.

[0092] As can be seen from the above, during the voltage signal boosting process (converting the first voltage signal to the second voltage signal) received by the control signal line 80, the first voltage signal is first converted to the third voltage signal, and then the third voltage signal is converted to the second voltage signal. This converts the large jump between the first and second voltage signals (i.e., the second voltage difference) into two smaller jumps (the first voltage difference and the third voltage difference), thereby reducing the interference of the voltage jump of the control signal line 80 on the data signal, improving the accuracy of data signal transmission, improving the defective phenomenon of horizontal stripes or screen splitting that appears in the display panel 100 during lamp lighting test, and improving product yield.

[0093] Furthermore, during the voltage signal reduction process (converting the second voltage signal to the first voltage signal) received by the control signal line 80, the second voltage signal is first converted to the third voltage signal, and then the third voltage signal is converted back to the first voltage signal. This transforms the large jump between the second and first voltage signals (the second voltage difference) into two smaller jumps (the first voltage difference and the third voltage difference), thereby reducing the interference of the voltage jumps of the control signal line 80 on the data signal, improving the accuracy of data signal transmission, improving the defective phenomenon of horizontal stripes or screen splitting that occurs in the display panel 100 during lamp lighting tests, and improving product yield.

[0094] It should be noted that a voltage jump refers to the absolute value of the difference between two voltages after one voltage is gradually increased or decreased.

[0095] In some embodiments, see Figure 5 The ratio of the first voltage difference to the second voltage difference is 1 / 4 to 3 / 4. This effectively reduces the voltage jumps in the control signal line 80, thereby reducing the interference of the voltage jumps in the control signal line 80 on the data signal and preventing the display device 1000 (see...) from interfering with the data signal. Figure 1 To improve product yield, defects such as horizontal stripes or split screens may occur during the lighting test.

[0096] For example, such as Figure 5 and Figure 7 As shown, the ratio of the first voltage difference to the second voltage difference is 1 / 2. For example, the voltage of the first voltage signal is -7V, the voltage of the second voltage signal is +7V, and the voltage of the third voltage signal is 0V. In this case, the first voltage difference is equal to the second voltage difference, which reduces the maximum value of the two voltage jumps of the control signal line 80, thereby further reducing the influence of the voltage jumps of the control signal received by the multiplexing circuit 60 on the data signal, and improving the display device 1000 (see...). Figure 1 This improves the uniformity of brightness and enhances the display effect.

[0097] In some embodiments, see Figure 5 The duration of the second sub-segment P102 is shorter than the duration of the first sub-segment P101, so that the data writing time is more sufficient, improving the accuracy of data signal transmission, improving the brightness uniformity of the display panel 100, and enhancing the display effect.

[0098] For example, see Figure 5 The duration of the second sub-segment P102 is 1 / 8 to 1 / 4 of the duration of the first sub-segment P101. For example, the duration of the second sub-segment P102 is 1 / 3 of the duration of the first sub-segment P101. For instance, the duration of the first sub-segment is 1.5 milliseconds, and the duration of the second sub-segment P102 is 0.5 milliseconds.

[0099] In some embodiments, see Figure 6 and Figure 7 Multiple data lines 40 are divided into multiple data line groups 410, and a multiplexing circuit 60 is connected to at least one data line group 410. For example, the multiplexing circuit 60 is connected to three data line groups 410.

[0100] like Figure 6 and Figure 7 As shown, the data line group 410 includes a first data line 41, a second data line 42 and a third data line 43. The first data line 41 is connected to a column of red sub-pixels R, the second data line 42 is connected to a column of green sub-pixels G, and the third data line 43 is connected to a column of blue sub-pixels B.

[0101] like Figure 5 and Figure 9 As shown, the multiple sub-write stages P10 of the data write stage P1 include at least one first sub-write stage P11, at least one second sub-write stage P12, and at least one third sub-write stage P13.

[0102] In the first sub-write stage P11, the data signal of the data bus 70 is transmitted to a first data line 41, i.e., the data signal is transmitted to the red sub-pixel R. In the second sub-write stage P12, the data signal of the data bus 70 is transmitted to a second data line 42, i.e., the data signal is transmitted to the green sub-pixel G. In the third sub-write stage P13, the data signal of the data bus 70 is transmitted to a third data line 43, i.e., the data signal is transmitted to the blue sub-pixel B.

[0103] In some embodiments, see Figure 9 and Figure 10 The second sub-write stage P12 is located after all the first sub-write stages P11 and the third sub-write stage P13, that is, the data signal is finally transmitted to the green sub-pixel G.

[0104] It should be understood that the human eye is sensitive to red, green, and blue light to different degrees. The human eye is more sensitive to green light than to red light, and more sensitive to red light than to blue light. That is, the brightness change of the green sub-pixel G caused by voltage jumps is easily perceived by the human eye.

[0105] Therefore, the data signal is transmitted to the green sub-pixel G last, so that there is no need to transmit data signals to other color sub-pixels P. This avoids the data signal transmitted to the green sub-pixel G being affected by the voltage jump of the control signal received by the multiplexing circuit 60, reduces the difference in display brightness that can be perceived by the human eye, improves the brightness uniformity of the display screen that can be perceived by the human eye, and enhances the display effect.

[0106] In addition, see Figure 9 and Figure 10 All third sub-write stages P13 are located before or after all first sub-write stages P11. Furthermore, the time interval between adjacent first sub-write stages P11 and third sub-write stages P13 is the first time difference, and the time interval between the second sub-write stage P12 and the adjacent one of the first sub-write stages P11 and third sub-write stages P13 is the second time difference T2.

[0107] Understandably, when the brightness difference of the green sub-pixel G caused by voltage jumps is the same as that of the red sub-pixel R or the blue sub-pixel B, the perceived brightness difference of the green sub-pixel G will be significantly larger.

[0108] Based on this, the second time difference T2 is greater than or equal to the first time difference T1. That is, the time interval between transmitting data signals to the green sub-pixel P and the red sub-pixel R is greater than the time interval between transmitting data signals to the red sub-pixel R and the blue sub-pixel B. In other words, the brightness difference caused by voltage jumps in the green sub-pixel G is less than the brightness difference caused by voltage jumps in the red sub-pixel R or the blue sub-pixel B. This compensates for the difference in light sensitivity of the human eye between the green sub-pixel G and other sub-pixels P (red sub-pixels R or blue sub-pixels B), thereby improving the perceived brightness uniformity of the displayed image and enhancing the display effect.

[0109] For example, such as Figure 9 As shown, the third sub-write stage P13 is located after all the first sub-write stages P11, and the second sub-write stage P12 is located after all the third sub-write stages P13. At this time, the first time difference is the time interval between adjacent first and third sub-write stages, and the second time difference is the interval between adjacent second and third sub-write stages P12 and P13.

[0110] For example, such as Figure 10 As shown, the first sub-write stage P11 is located after all the third sub-write stages P13, and the second sub-write stage P12 is located after all the first sub-write stages P11. At this time, the first time difference is the time interval between adjacent first and third sub-write stages, and the second time difference is the interval between adjacent second sub-write stage P12 and first sub-write stage P11.

[0111] Based on this, refer to Figure 7 The aforementioned multiplexing circuit 60 can, for example, be connected to multiple data line groups 410. In this case, such as... Figure 9 and Figure 10As shown, the data writing stage P10 includes multiple first sub-writing stages P11, multiple second sub-writing stages P12, and multiple third sub-writing stages P13.

[0112] Specifically, the time interval between multiple first sub-write stages P11 is the third time difference T3, the time interval between multiple second sub-write stages P12 is the fourth time difference T4, and the time interval between multiple third sub-write stages P13 is the fifth time difference T5. The time interval between adjacent first sub-write stages P11, second sub-write stages P12, and third sub-write stages P13 is the sixth time difference T6.

[0113] Furthermore, the third time difference T3, the fourth time difference T4, and the fifth time difference T5 are all less than the sixth time difference T6. In other words, the time intervals between data signals transmitted by multiple first data lines 41, the time intervals between data signals transmitted by multiple second data lines 42, and the time intervals between data signals transmitted by multiple third data lines 43 are all less than or equal to the time intervals between data signals transmitted by the first data lines 41 and the second data lines 42, and the time intervals between data signals transmitted by the second data lines 42 and the third data lines 43.

[0114] It should be noted that when at least two of the multiple sixth time differences T6 are not equal, the statement that the third time difference T3, the fourth time difference T4, and the fifth time difference T5 are all less than the sixth time difference T6 means that the third time difference T3, the fourth time difference T4, and the fifth time difference T5 are all less than the smallest sixth time difference T6.

[0115] In this scenario, the time interval between transmitting data signals to two columns of sub-pixels P with the same luminous color is shorter than the time interval between transmitting data signals to two columns of sub-pixels P with different luminous colors. This increases the time interval between transmitting data signals to two columns of sub-pixels P with different luminous colors, thereby reducing the impact of voltage fluctuations in the control signals received by the multiplexing circuit 60 on the data signals transmitted between the sub-pixels P with different luminous colors. This reduces the perceived difference in display brightness, improves the perceived uniformity of brightness in the display image, and enhances the display effect.

[0116] In some embodiments, see Figure 9 and Figure 10 The duration of the first sub-segment P101 in the second sub-write stage P12 is greater than or equal to the duration of the first sub-segment P101 in the first sub-write stage P11. The duration of the first sub-segment P101 in the first sub-write stage P11 is greater than or equal to the duration of the first sub-segment P101 in the third sub-write stage P13.

[0117] In this scenario, the impact of voltage jumps on the data signal transmitted to the green sub-pixel G is less than or equal to the impact of voltage jumps on the data signal transmitted to the red sub-pixel R. The impact of voltage jumps on the data signal transmitted to the red sub-pixel R is less than or equal to the impact of voltage jumps on the data signal transmitted to the blue sub-pixel B.

[0118] In other words, the brightness difference of the green sub-pixel G caused by voltage jumps is less than or equal to the brightness difference of the red sub-pixel R caused by voltage jumps. The brightness difference of the red sub-pixel R caused by voltage jumps is less than or equal to the brightness difference of the blue sub-pixel B caused by voltage jumps. This compensates for the differences in the human eye's sensitivity to the light among the green sub-pixel G, red sub-pixel R, and blue sub-pixel B, thereby improving the perceived brightness uniformity of the displayed image and enhancing the display effect.

[0119] The display panel 100 provided in some embodiments of this disclosure is used to execute the display panel driving method of any of the above embodiments. The display panel 100 of the embodiments of this disclosure has the same beneficial effects as the display panel driving method provided in some embodiments above, and will not be described again below.

[0120] In some embodiments, see Figure 6 and Figure 7 Multiple sub-pixels P include red sub-pixels R, green sub-pixels G and blue sub-pixels B with different emission colors, and multiple data lines 40 are divided into multiple data line groups 410. The multiplexing circuit 60 is connected to at least one data line group 410.

[0121] The data line group 410 includes a first data line 41, a second data line 42 and a third data line 43. The first data line 41 is connected to a column of red sub-pixels R, the second data line 42 is connected to a column of green sub-pixels G, and the third data line 43 is connected to a column of blue sub-pixels B.

[0122] The display device 1000 provided in some embodiments of this disclosure includes the display panel 100 and driver chip 20 of the above embodiments.

[0123] Among them, see Figure 6 and Figure 7 The driver chip 20 is configured to provide a first voltage signal, a second voltage signal, and a third voltage signal to the control signal line 80. Furthermore, in conjunction with... Figure 5 and Figure 7 During the data writing phase P10, a first voltage signal and a third voltage signal are provided to one control signal line 80, and a second voltage signal is provided to other control signal lines 80. The voltage value of the third voltage signal is between the voltage values ​​of the first voltage signal and the second voltage signal.

[0124] The display device 1000 of this disclosure has the same beneficial effects as the display panel driving method provided in some of the above embodiments, and will not be described again below.

[0125] In some embodiments, see Figure 7 , Figure 9 and Figure 10 The driver chip 20 is also configured to transmit the data signal of the data bus 70 to the second data line 42 after transmitting the data signal of the data bus 70 to the first data line 41 and the third data line 43 respectively. That is, the data signal is finally transmitted to the green sub-pixel G.

[0126] In some embodiments, see Figure 6 The multiple control signal lines 80 include a first control signal line 81, a second control signal line 82, and a third control signal line 83.

[0127] Furthermore, the multiplexing circuit 60 is configured to transmit the data signal of the data bus 70 to the first data line 41 under the control of the first voltage signal of the first control signal line 81; transmit the data signal of the data bus 70 to the second data line 42 under the control of the first voltage signal of the second control signal line 82; and transmit the data signal of the data bus 70 to the third data line 43 under the control of the first voltage signal of the third control signal line 83.

[0128] At this time, combined Figure 5 and Figure 9 The driver chip 20 is further configured such that the duration of the third voltage signal provided to the second control signal line 82 is greater than or equal to the duration of the third voltage signal provided to the first control signal line 81. The duration of the third voltage signal provided to the first control signal line 81 is greater than or equal to the duration of the third voltage signal provided to the third control signal line 83. That is, the duration of the first sub-segment P101 of the second sub-write stage P12 is greater than or equal to the duration of the first sub-segment P101 of the first sub-write stage P11. The duration of the first sub-segment P101 of the first sub-write stage P11 is greater than or equal to the duration of the first sub-segment P101 of the third sub-write stage P13.

[0129] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes multiple sub-pixels, multiple data lines connected to the multiple sub-pixels, multiple multiplexed circuits, multiple data buses, and multiple control signal lines. At least one of the multiple multiplexed circuits is configured to, under the control of the multiple control signal lines, transmit the data signal transmitted by one of the multiple data buses to at least two of the multiple data lines in a time-division manner. The process of transmitting the data signal from one data bus to the at least two data lines through the at least one multiplexing circuit is a data writing stage. The data writing stage includes multiple sub-writing stages spaced apart. Each sub-writing stage includes a first sub-segment and at least one second sub-segment, which are consecutively arranged. The driving method includes: In the first sub-segment, a first voltage signal is provided to one of the control signal lines, and a second voltage signal is provided to the other control signal lines; a multiplexing circuit, in response to the first voltage signal of one of the control signal lines, transmits the data signal of the data bus to one of the data lines; In the second sub-segment, a third voltage signal is provided to the target control signal line, and a second voltage signal is provided to the other control signal lines; the target control signal line is a control signal line that receives a first voltage signal in the first sub-segment; the voltage value of the third voltage signal is located between the voltage value of the first voltage signal and the voltage value of the second voltage signal.

2. The driving method according to claim 1, characterized in that, The absolute value of the difference between the voltage of the third voltage signal and the voltage of the second voltage signal is the first voltage difference, the absolute value of the difference between the voltage of the first voltage signal and the voltage of the second voltage signal is the second voltage difference, and the ratio of the first voltage difference to the second voltage difference is 1 / 4 to 3 / 4.

3. The driving method according to claim 1, characterized in that, The duration of the second segment is less than the duration of the first segment.

4. The driving method according to claim 3, characterized in that, The duration of the second segment is 1 / 8 to 1 / 4 of the duration of the first segment.

5. The driving method according to any one of claims 1 to 4, characterized in that, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels with different emission colors. The plurality of data lines are divided into a plurality of data line groups. One of the multiplexing circuits is connected to at least one of the plurality of data line groups. Furthermore, the data line group includes a first data line, a second data line, and a third data line. The plurality of sub-pixels are arranged in multiple rows and columns. The first data line is connected to a column of red sub-pixels, the second data line is connected to a column of green sub-pixels, and the third data line is connected to a column of blue sub-pixels. The plurality of sub-write stages include at least one first sub-write stage, at least one second sub-write stage, and at least one third sub-write stage; in the first sub-write stage, the data signal of the data bus is transmitted to a first data line; in the second sub-write stage, the data signal of the data bus is transmitted to a second data line; in the third sub-write stage, the data signal of the data bus is transmitted to a third data line; the at least one second sub-write stage is located after the at least one first sub-write stage and the at least one third sub-write stage.

6. The driving method according to claim 5, characterized in that, The at least one third sub-write stage is located before or after the at least one first sub-write stage; The time interval between adjacent first sub-write stages and third sub-write stages is the first time difference, and the time interval between the second sub-write stage and one of the adjacent first and third sub-write stages is the second time difference; the second time difference is greater than or equal to the first time difference.

7. The driving method according to claim 5, characterized in that, One of the multiplexing circuits is connected to at least two of the plurality of data line groups, and the plurality of sub-write stages include a plurality of first sub-write stages, a plurality of second sub-write stages, and a plurality of third sub-write stages, wherein the plurality of third sub-write stages are located before or after the plurality of first sub-write stages; The time interval between the plurality of first sub-write stages is the third time difference, the time interval between the plurality of second sub-write stages is the fourth time difference, and the time interval between the plurality of third sub-write stages is the fifth time difference; the time interval between two adjacent first sub-write stages, second sub-write stages, and third sub-write stages is the sixth time difference. The third time difference, the fourth time difference, and the fifth time difference are all less than or equal to the sixth time difference.

8. The driving method according to any one of claims 1 to 4, characterized in that, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels with different emission colors. The plurality of data lines are divided into a plurality of data line groups. One of the multiplexing circuits is connected to at least one of the plurality of data line groups. Furthermore, the data line group includes a first data line, a second data line, and a third data line. The first data line is connected to a column of red sub-pixels, the second data line is connected to a column of green sub-pixels, and the third data line is connected to a column of blue sub-pixels. The plurality of sub-write stages include at least one first sub-write stage, at least one second sub-write stage, and at least one third sub-write stage; in the first sub-write stage, the data signal of the data bus is transmitted to a first data line; in the second sub-write stage, the data signal of the data bus is transmitted to a second data line; and in the third sub-write stage, the data signal of the data bus is transmitted to a third data line. The duration of the first segment of the second sub-write stage is greater than or equal to the duration of the first segment of the first sub-write stage; the duration of the first segment of the first sub-write stage is greater than or equal to the duration of the first segment of the third sub-write stage.

9. A display panel, characterized in that, A driving method for performing a display panel as described in any one of claims 1 to 8, the display panel comprising: a display area and a peripheral area located on at least one side of the display area; Multiple sub-pixels are located in the display area and arranged in multiple rows and columns; each row includes at least two sub-pixels arranged along a first direction, and each column includes at least two sub-pixels arranged along a second direction. Multiple data lines are located in the display area and connected to the multiple sub-pixels. The multiple data lines extend along the second direction and are arranged at intervals along the first direction. One data line is connected to a column of sub-pixels. Multiple multiplexed circuits are located in the peripheral area and arranged at intervals along the first direction; each multiplexed circuit is connected to at least two of the multiple data lines; Multiple data buses are located in the peripheral area and on the side of the multiple multiplexed circuits away from the display area, with one data bus connected to one multiplexed circuit. Multiple control signal lines are located in the peripheral area and extend along the first direction; each multiplexing circuit is connected to the multiple control signals; the multiplexing circuit is configured to, under the control of the multiple control signal lines, transmit the data signal of one data bus to at least two data lines in a time-division manner.

10. The display panel according to claim 9, characterized in that, The plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels with different emission colors, the plurality of data lines are divided into a plurality of data line groups, and one of the multiplexing circuits is connected to at least one of the plurality of data line groups; Furthermore, the data line group includes a first data line, a second data line, and a third data line. The first data line is connected to a column of red sub-pixels, the second data line is connected to a column of green sub-pixels, and the third data line is connected to a column of blue sub-pixels.

11. A display device, characterized in that, include: The display panel as described in claim 9 or 10; A driver chip is connected to the data bus and control signal lines of the display panel; the driver chip is configured to provide the first voltage signal, the second voltage signal, and the third voltage signal to the control signal lines. Furthermore, during the data writing phase, the first voltage signal and the third voltage signal are provided to one of the control signal lines, and the second voltage signal is provided to the other control signal lines. The voltage value of the third voltage signal is located between the voltage values ​​of the first voltage signal and the second voltage signal.

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