Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: forming a first epitaxial structure on a substrate, wherein the first epitaxial structure comprises an opening area; forming an etching stop layer on a side of the first epitaxial structure away from the substrate; removing a part of the etching stop layer located in the opening area; forming a side wall corresponding to a side edge of the etching stop layer in the opening area; etching the first epitaxial structure to form an opening by taking the etching stop layer and the side wall as a mask; and forming an electrode structure in the opening. The application can reduce the opening size of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor devices play an important role in modern electronic technology, and the performance requirements for semiconductor devices are becoming increasingly stringent.

[0003] However, in the fabrication of electrodes (such as gate electrodes) in existing semiconductor devices, the aperture size is limited by the process limits of photolithography, preventing further miniaturization and resulting in a relatively large gate electrode size. This larger gate electrode size leads to a larger gate capacitance, affecting the switching speed of the semiconductor device and thus limiting its application in high-frequency fields. Summary of the Invention

[0004] This invention provides a semiconductor device and a method for fabricating the same, thereby reducing the aperture size of the semiconductor device.

[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising:

[0006] A first epitaxial structure is formed on a substrate, the first epitaxial structure including an opening region;

[0007] An etching barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0008] Remove the portion of the etching barrier layer located in the opening region;

[0009] A sidewall is formed on the side of the opening area corresponding to the etch barrier layer;

[0010] The first epitaxial structure is etched using the etching barrier layer and the sidewall as a mask to form an opening;

[0011] An electrode structure is formed within the opening.

[0012] Optionally, forming a sidewall in the opening area includes:

[0013] A sidewall material layer is formed on the entire surface, the sidewall material layer covering the etching barrier layer and the first epitaxial structure exposed by removing the etching barrier layer in the opening area;

[0014] The sidewall is formed by etching the sidewall material layer.

[0015] Optionally, the formation of the entire sidewall material layer includes:

[0016] The thickness of the sidewall material layer is determined based on the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

[0017] Optionally, the etching barrier layer includes a dielectric material layer;

[0018] The process of forming the electrode structure within the opening further includes:

[0019] Remove the medium material layer and the sidewall.

[0020] Optionally, the dielectric material layer is made of silicon oxide, and the sidewalls are made of silicon nitride; or, the dielectric material layer is made of silicon nitride, and the sidewalls are made of silicon oxide.

[0021] Optionally, the etching barrier layer includes an epitaxial material layer;

[0022] The formation of the electrode structure within the opening includes:

[0023] The electrode structure is formed to fill the opening and at least partially cover the epitaxial material layer.

[0024] Optionally, the etching selectivity ratio of the first epitaxial structure to the epitaxial material layer is greater than or equal to 5.

[0025] Optionally, the material of the epitaxial material layer includes aluminum nitride, and the material of the sidewall includes silicon nitride or silicon oxide.

[0026] Optionally, the step of forming a sidewall in the opening area further includes:

[0027] The portion of the first epitaxial structure located in the opening region is etched to form a sub-opening; wherein the sub-opening has a preset depth, the preset depth being less than the depth of the opening corresponding to the first epitaxial structure;

[0028] The step of forming a sidewall on the side of the opening area corresponding to the etching barrier layer includes:

[0029] A sidewall is formed on the side of the sub-opening.

[0030] Optionally, the preset depth is less than or equal to half the depth of the opening corresponding to the first epitaxial structure.

[0031] According to another aspect of the present invention, a semiconductor device is provided, which is prepared by the semiconductor device preparation method described above.

[0032] The technical solution of this invention employs a semiconductor device fabrication method comprising: forming a first epitaxial structure on a substrate, the first epitaxial structure including an opening region; forming an etch barrier layer on the side of the first epitaxial structure away from the substrate; removing the portion of the etch barrier layer located in the opening region; forming a sidewall on the side of the opening region corresponding to the etch barrier layer; etching the first epitaxial structure using the etch barrier layer and the sidewall as a mask to form an opening; and forming an electrode structure within the opening. Because a sidewall structure is formed at the opening of the etch barrier layer before etching the first epitaxial structure, the opening size is further reduced. Consequently, the opening size formed on the first epitaxial structure is smaller, resulting in a smaller electrode structure. This further reduces the parasitic capacitance of the semiconductor device and improves its switching speed.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention;

[0037] Figure 3 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0038] Figure 4 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0039] Figure 5 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the product structure corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention;

[0041] Figure 7A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of the product structure formed corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention;

[0043] Figure 9 A schematic diagram of the product structure corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, with reference to... Figure 1 The methods for fabricating semiconductor devices include:

[0047] Step S110: A first epitaxial structure is formed on the substrate, the first epitaxial structure including an opening region;

[0048] Specifically, Figure 2 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention, combined with... Figure 1 and Figure 2The semiconductor device in this embodiment can be a high electron mobility transistor (HEMT), heterojunction bipolar transistor (HBT), heterojunction field effect transistor (HFET), or modulation-doped FET (MODFET) semiconductor device, etc., formed by heterostructure. The first epitaxial structure 12 can be fabricated by epitaxial processing. The opening region HO of the first epitaxial structure 12 is the region where an opening needs to be formed, and this opening is subsequently used to form the electrode of the semiconductor device. Preferably, the gate parasitic capacitance in the semiconductor device has a significant impact on the switching performance of the semiconductor device, and the size of the gate parasitic capacitance is related to the size of the gate electrode. Therefore, the opening region described in this embodiment can be the region corresponding to where the gate electrode needs to be formed.

[0049] For example, the substrate 11 may be silicon, silicon carbide (SiC), gallium arsenide (GaAs), silicon germanium (SiGe), p-doped silicon, n-doped silicon, sapphire, silicon-on-insulator, or other semiconductor materials. Alternatively, the substrate 11 may also include, for example, group III elements, group IV elements, group V elements, or combinations thereof (e.g., group III-V compounds). The first epitaxial structure 12 may form a heterojunction, which may, for example, include a channel layer and a barrier layer.

[0050] Step S120: An etch barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0051] Specifically, the etch barrier layer 13 is used to prevent the first epitaxial structure 12 covered by it from being etched. The etch barrier layer 13 can be formed by processes such as epitaxy or deposition. The deposition process is such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), low-power CVD (LPCVD), or plasma-assisted vapor deposition.

[0052] Step S130: Remove the portion of the etching barrier layer located in the opening area;

[0053] Specifically, the etch barrier layer 13 can be patterned using photolithography, so that the portion of the etch barrier layer 13 located in the opening region HO is removed, while the remaining portion is retained. For example... Figure 2 As shown, a photoresist 20 can first be formed on the etch barrier layer 13. Then, the photoresist 20 is exposed and developed using a mask, so that the portion of the photoresist 20 corresponding to the opening region HO is removed. Next, using the photoresist 20 as a mask, the portion of the etch barrier layer 13 located in the opening region HO is etched away. The etching process can be dry etching or wet etching, etc.

[0054] Step S140: A sidewall is formed on the side of the etch barrier layer corresponding to the opening area;

[0055] Specifically, such as Figure 2 As shown, after the portion of the etch barrier layer 13 corresponding to the opening region HO is removed, the first epitaxial structure 12 needs to be etched using the etch barrier layer 13 as a mask. Due to the limitations of the lithography machine's precision, the minimum size that the photoresist 20 can be etched is also relatively large, which also makes the minimum size of the opening region HO relatively large. In other words, the portion of the etch barrier layer 13 that is etched away cannot be further reduced due to the limitations of the lithography machine's precision, resulting in a larger area of ​​the first epitaxial structure 12 exposed by the etch barrier layer 13. Consequently, the opening formed on the first epitaxial structure 12 is also larger, resulting in a larger gate electrode and thus a larger gate parasitic capacitance in the semiconductor device. In this embodiment, a sidewall 141 can be formed on the side of the etch barrier layer 13. Since the sidewall 141 has a certain lateral ( Figure 2 If the etch barrier layer 13 and the sidewall 141 are arranged in the same direction, then the area of ​​the first epitaxial structure 12 exposed by the overall structure composed of the etch barrier layer 13 and the sidewall 141 is relatively small.

[0056] Step S150: Using the etching barrier layer and sidewalls as a mask, the first epitaxial structure is etched to form an opening;

[0057] Specifically, the etching method for the first epitaxial structure 12 is well known to those skilled in the art, such as dry etching or wet etching. In this embodiment, due to the formation of sidewalls 141, the exposed area of ​​the first epitaxial structure 12 is small, resulting in a smaller opening HO1 formed by the etching of the first epitaxial structure 12. As can be seen from the above analysis, this embodiment can further reduce the size of the opening by forming sidewalls 141 at the position corresponding to the etching barrier layer in the opening area. This allows for a further reduction in the opening size within the limits of the lithography machine's dimensions.

[0058] Step S160: An electrode structure is formed inside the opening.

[0059] Specifically, the electrode structure may include a second epitaxial structure 15, such as a p-type gate, i.e., a p-type semiconductor material. The second epitaxial structure 15 enables the semiconductor device to be configured as an enhancement-mode device. Of course, the electrode structure can also be other structures. The second epitaxial structure 15 can be formed by epitaxy or other methods. Because the size of the opening HO1 is small, there are fewer second epitaxial structures 15 located within the opening HO1, allowing the overall size of the electrode structure to be smaller, thereby further reducing the gate parasitic capacitance of the semiconductor device.

[0060] The technical solution of this embodiment employs a semiconductor device fabrication method comprising: forming a first epitaxial structure on a substrate, the first epitaxial structure including an opening region; forming an etch barrier layer on the side of the first epitaxial structure away from the substrate; removing the portion of the etch barrier layer located in the opening region; forming a sidewall on the side of the opening region corresponding to the etch barrier layer; etching the first epitaxial structure using the etch barrier layer and the sidewall as a mask to form an opening; and forming an electrode structure within the opening. Because a sidewall structure is fabricated at the opening of the etch barrier layer before etching the first epitaxial structure, the opening size is further reduced. Consequently, the opening size formed on the first epitaxial structure is smaller, resulting in a smaller electrode structure. This further reduces the parasitic capacitance of the semiconductor device and improves its switching speed.

[0061] Optionally, Figure 3 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention is provided, referencing... Figure 3 In this embodiment, the method for fabricating the semiconductor device includes:

[0062] Step S110: A first epitaxial structure is formed on the substrate, the first epitaxial structure including an opening region;

[0063] Step S120: An etch barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0064] Step S130: Remove the portion of the etching barrier layer located in the opening area;

[0065] In the above embodiments, step S140 specifically includes:

[0066] Step S141: A sidewall material layer is formed on the entire surface. The sidewall material layer covers the etching barrier layer and the first epitaxial structure exposed by removing the etching barrier layer in the opening area.

[0067] Specifically, such as Figure 2 As shown, the sidewall material layer 14 is formed, for example, by a deposition process. Through a deposition process, a single sidewall material layer 14 can be formed over the entire surface. The material of the sidewall material layer 14 can be a dielectric material or an epitaxial material, etc.

[0068] Step S142: The sidewall is formed by etching the sidewall material layer.

[0069] Specifically, the sidewall etching is, for example, dry etching, which is anisotropic. The etching stops when the sidewall material layer 14 is etched to expose the corresponding etching barrier layer and the first epitaxial structure. Since the sidewall material layer at the corresponding location is relatively thick, this part of the sidewall material layer will not be completely etched after the etching stops, but the lower sidewall 141 will be retained.

[0070] Step S150: Using the etching barrier layer and sidewalls as a mask, the first epitaxial structure is etched to form an opening;

[0071] Step S160: An electrode structure is formed inside the opening.

[0072] Optionally, based on the above embodiments, when forming the sidewall material layer over the entire surface, the thickness of the sidewall material layer is determined according to the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

[0073] Specifically, in this embodiment, the opening size corresponding to the first epitaxial structure is the expected size. When the expected size is large, the thickness of the sidewall material layer is also large; when the expected size is small, the thickness of the sidewall material layer is also small. The thickness of the sidewall material layer is related to the lateral dimension of the sidewall. When the sidewall material layer is large, the lateral dimension of the subsequently formed sidewall is also large, thus allowing a smaller opening to be created on the first epitaxial structure. When the sidewall material layer is small, the lateral dimension of the subsequently formed sidewall is small, thus allowing a relatively large opening to be created on the first epitaxial structure. Furthermore, the thickness of the sidewall material layer also needs to consider the overall size of the semiconductor device. If the final size of the semiconductor device is large, the thickness of the corresponding sidewall material layer can be set larger; conversely, if the final size of the semiconductor device is small, the thickness of the corresponding sidewall material layer needs to be set smaller to avoid affecting the performance of the semiconductor device.

[0074] Optionally, Figure 4 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention, in conjunction with... Figure 2 and Figure 4 The method for fabricating the semiconductor device in this embodiment includes:

[0075] Step S110: A first epitaxial structure is formed on the substrate, the first epitaxial structure including an opening region;

[0076] Step S120: An etch barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0077] Specifically, in this embodiment, the material of the etching barrier layer 13 is a dielectric material. The dielectric material can be silicon oxide or silicon nitride, etc.

[0078] Step S130: Remove the portion of the etching barrier layer located in the opening area;

[0079] Step S140: A sidewall is formed on the side of the etch barrier layer corresponding to the opening area;

[0080] Specifically, the sidewall material is different from the etch barrier layer material to prevent the etch barrier layer from being etched away when the sidewall material layer is formed. For example, when the etch barrier layer 13 is made of silicon oxide, the sidewall 141 can be made of silicon nitride. When the etch barrier layer 13 is made of silicon nitride, the sidewall 141 can be made of silicon oxide.

[0081] Step S150: Using the etching barrier layer and sidewalls as a mask, the first epitaxial structure is etched to form an opening;

[0082] Step S200: Remove the medium material layer and sidewalls;

[0083] Specifically, such as Figure 2 As shown, in this embodiment, the dielectric material layer is not conducive to the subsequent epitaxial growth of the second epitaxial structure. Therefore, the dielectric material layer can be removed before forming the electrode structure. Removal methods include, for example, wet etching. After the dielectric material layer and sidewalls are etched, the first epitaxial structure 12 is exposed, which facilitates the subsequent growth of the electrode structure (such as the second epitaxial structure in the electrode structure).

[0084] Step S160: An electrode structure is formed inside the opening.

[0085] In this embodiment, a dielectric material is selected as the etching barrier layer, and then the dielectric material and sidewalls are removed subsequently. The wide variety of dielectric materials available helps reduce the fabrication cost of semiconductor devices.

[0086] Optionally, Figure 5 The flowchart illustrates another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 6 A schematic diagram of the product structure corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention is shown below. Figure 5 and Figure 6 Methods for fabricating semiconductor devices include:

[0087] Step S110: A first epitaxial structure is formed on the substrate, the first epitaxial structure including an opening region;

[0088] Step S120: An etch barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0089] Specifically, in this embodiment, the etching barrier layer 13 is made of an epitaxial material layer. The epitaxial material layer may be, for example, aluminum nitride. In this embodiment, the etching barrier layer can not only serve as a mask for etching the first epitaxial structure, but can also continue to epitaxially form a second epitaxial structure in the electrode structure.

[0090] Step S130: Remove the portion of the etching barrier layer located in the opening area;

[0091] Step S140: A sidewall is formed on the side of the etch barrier layer corresponding to the opening area;

[0092] Specifically, the sidewall material is different from the etching barrier layer material to prevent the etching barrier layer from being etched away when the sidewall material layer is formed. For example, in this embodiment, the material of the sidewall 141 can be silicon oxide or silicon nitride, etc.

[0093] Step S150: Using the etching barrier layer and sidewalls as a mask, the first epitaxial structure is etched to form an opening;

[0094] In this embodiment, forming an electrode structure within the opening includes:

[0095] Step S161: Form an electrode structure that fills the opening and at least partially covers the epitaxial material layer;

[0096] Specifically, the electrode structure in this embodiment includes a second epitaxial structure 15. Since the material of the etch barrier layer 13 is an epitaxial material, the second epitaxial structure 15 can be directly epitaxially grown on the etch barrier layer 13 without the need for... Figure 2 The step of removing the etch barrier layer 13 in the corresponding embodiment can save process steps and improve the manufacturing efficiency of semiconductor devices.

[0097] Optionally, in the above embodiments, the etching selectivity ratio of the first epitaxial structure to the epitaxial material layer is greater than or equal to 5.

[0098] Specifically, since both the first epitaxial structure and the epitaxial material layer are epitaxial materials, if the etching selectivity ratio between the first epitaxial structure and the epitaxial material layer is relatively small, the epitaxial material layer will also be etched more when etching the first epitaxial structure, thus failing to provide etching resistance. In this embodiment, by selecting an etching selectivity ratio between the first epitaxial structure and the epitaxial material layer greater than or equal to 5, a high etching resistance is ensured for the epitaxial material layer.

[0099] It should be noted that the specific material of the epitaxial layer can be selected according to the material of the first epitaxial structure. It can be aluminum nitride as mentioned above, or other feasible materials.

[0100] Optionally, Figure 7The flowchart illustrates another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 8 A schematic diagram of the product structure corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention. Figure 9 A schematic diagram of the product structure corresponding to the main steps of another semiconductor device fabrication method provided in this embodiment of the invention is shown below. Figures 7 to 9 Methods for fabricating semiconductor devices include:

[0101] Step S110: A first epitaxial structure is formed on the substrate, the first epitaxial structure including an opening region;

[0102] Step S120: An etch barrier layer is formed on the side of the first epitaxial structure away from the substrate;

[0103] Specifically, in Figure 8 In the corresponding embodiment, the etching barrier layer 13 is made of a dielectric material, which needs to be removed before the second epitaxial structure can be fabricated. Figure 9 In the corresponding embodiment, the material of the etch barrier layer 13 is an epitaxial material layer, and there is no need to remove the etch barrier layer subsequently. The second epitaxial structure can be directly epitaxially generated on the etch barrier layer 13.

[0104] Step S130: Remove the portion of the etching barrier layer located in the opening area;

[0105] Step S210: Etch the portion of the first epitaxial structure located in the opening region to form a sub-opening; wherein the sub-opening has a preset depth, the preset depth being less than the depth of the opening corresponding to the first epitaxial structure;

[0106] Specifically, in this embodiment, after patterning the etch barrier layer, the first epitaxial structure can be partially etched to form a sub-opening HO2. It should be noted that when the first epitaxial structure includes multiple layers, the sub-opening HO2 may penetrate only a portion of the layers, or penetrate a portion of the uppermost layer (i.e., the layer in contact with the etch barrier layer).

[0107] Step S143: Form a sidewall located on the side of the sub-opening;

[0108] Specifically, in this embodiment, the sidewall 141 is formed not only on the film layer where the etching barrier layer is located, but also on the film layer corresponding to the first epitaxial structure. Due to the isotropic nature of wet etching, etching the first epitaxial structure 12 not only forms an opening, but also etches away a portion of the first epitaxial structure laterally along the sidewall of the opening. In this embodiment, since the sidewall 141 is also formed on the film layer corresponding to the first epitaxial structure, the size of the opening formed by wet etching can be reduced, thereby further reducing the size of the opening and lowering the parasitic capacitance of the semiconductor device.

[0109] Step S150: Using the etching barrier layer and sidewalls as a mask, the first epitaxial structure is etched to form an opening;

[0110] Step S160: An electrode structure is formed inside the opening.

[0111] Optionally, in the above embodiments, the preset depth is less than or equal to half the depth of the opening corresponding to the first extensional structure.

[0112] Specifically, if the preset depth is too large, it may affect the gate characteristics of the semiconductor device, thereby affecting the performance of the semiconductor device. Therefore, by setting the preset depth in this embodiment, it is possible to ensure that the opening size of the semiconductor device is small while reducing the impact on the performance of the semiconductor device.

[0113] Optionally, refer to Figure 2 In the above embodiments, forming the first epitaxial structure on the substrate includes forming one or a combination of several of GaN layer 121, AlN layer 122, AlGaN layer 123, and UGaN layer 124 on the substrate. The GaN layer is a channel layer, and in this embodiment, the opening can completely penetrate the UGaN layer, AlGaN layer, and AlN layer, and can also partially penetrate the GaN layer. Before fabricating the second epitaxial structure, an AlGaN layer can be applied first.

[0114] Furthermore, it should be noted that this embodiment only illustrates the electrode structure and a portion of the semiconductor device structure. Those skilled in the art will understand that the electrode structure may also include an ohmic metal layer and electrode metal, etc. The semiconductor device may also include other electrodes, such as source electrodes and drain electrodes, etc.

[0115] This invention also provides a semiconductor device, which is fabricated by the method for fabricating a semiconductor device provided in any embodiment of this invention. The semiconductor device has characteristics such as small aperture size and small electrode size, thus exhibiting low parasitic capacitance, resulting in faster switching speeds and making it more suitable for high-frequency and other applications.

[0116] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0117] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first epitaxial structure is formed on a substrate, the first epitaxial structure including an opening region; An etching barrier layer is formed on the side of the first epitaxial structure away from the substrate; Remove the portion of the etching barrier layer located in the opening region; A sidewall is formed on the side of the opening area corresponding to the etch barrier layer; The first epitaxial structure is etched using the etching barrier layer and the sidewall as a mask to form an opening; An electrode structure is formed within the opening; The process of forming a sidewall in the opening area further includes: The portion of the first epitaxial structure located in the opening region is etched to form a sub-opening; wherein the sub-opening has a preset depth, the preset depth being less than the depth of the opening corresponding to the first epitaxial structure; The step of forming a sidewall on the side of the opening area corresponding to the etching barrier layer includes: A sidewall is formed on the side of the sub-opening.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a sidewall in the opening area includes: A sidewall material layer is formed on the entire surface, the sidewall material layer covering the etching barrier layer and the first epitaxial structure exposed by removing the etching barrier layer in the opening area; The sidewall is formed by etching the sidewall material layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The process of forming the entire sidewall material layer includes: The thickness of the sidewall material layer is determined based on the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching barrier layer includes a dielectric material layer; The process of forming the electrode structure within the opening further includes: Remove the medium material layer and the sidewall.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The dielectric material layer is made of silicon oxide, and the sidewalls are made of silicon nitride; or, the dielectric material layer is made of silicon nitride, and the sidewalls are made of silicon oxide.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching barrier layer includes an epitaxial material layer; The formation of the electrode structure within the opening includes: The electrode structure is formed to fill the opening and at least partially cover the epitaxial material layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The etching selectivity ratio between the first epitaxial structure and the epitaxial material layer is greater than or equal to 5.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The material of the epitaxial layer includes aluminum nitride, and the material of the sidewall includes silicon nitride or silicon oxide.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preset depth is less than or equal to half the depth of the opening corresponding to the first epitaxial structure.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing a semiconductor device according to any one of claims 1-9.

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